1 /* $NetBSD: amdgpu_dce120_hw_sequencer.c,v 1.3 2021/12/19 11:23:00 riastradh Exp $ */
2
3 /*
4 * Copyright 2015 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce120_hw_sequencer.c,v 1.3 2021/12/19 11:23:00 riastradh Exp $");
30
31 #include "dm_services.h"
32 #include "dc.h"
33 #include "core_types.h"
34 #include "dce120_hw_sequencer.h"
35 #include "dce/dce_hwseq.h"
36
37 #include "dce110/dce110_hw_sequencer.h"
38
39 #include "dce/dce_12_0_offset.h"
40 #include "dce/dce_12_0_sh_mask.h"
41 #include "soc15_hw_ip.h"
42 #include "vega10_ip_offset.h"
43 #include "reg_helper.h"
44
45 #define CTX \
46 hws->ctx
47 #define REG(reg)\
48 hws->regs->reg
49
50 #undef FN
51 #define FN(reg_name, field_name) \
52 hws->shifts->field_name, hws->masks->field_name
53
54 struct dce120_hw_seq_reg_offsets {
55 uint32_t crtc;
56 };
57
58 static const struct dce120_hw_seq_reg_offsets reg_offsets[] __unused = {
59 {
60 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
61 },
62 {
63 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
64 },
65 {
66 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
67 },
68 {
69 .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
70 },
71 {
72 .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
73 },
74 {
75 .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
76 }
77 };
78
79 #define HW_REG_CRTC(reg, id)\
80 (reg + reg_offsets[id].crtc)
81
82 #define CNTL_ID(controller_id)\
83 controller_id
84 /*******************************************************************************
85 * Private definitions
86 ******************************************************************************/
87 #if 0
88 static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)
89 {
90 uint32_t addr;
91 uint32_t value = 0;
92 uint32_t chunk_int = 0;
93 uint32_t chunk_mul = 0;
94 /*
95 addr = mmDCP0_DVMM_PTE_CONTROL + controller_id *
96 (mmDCP1_DVMM_PTE_CONTROL- mmDCP0_DVMM_PTE_CONTROL);
97
98 value = dm_read_reg(ctx, addr);
99
100 set_reg_field_value(
101 value, 0, DCP, controller_id,
102 DVMM_PTE_CONTROL,
103 DVMM_USE_SINGLE_PTE);
104
105 set_reg_field_value_soc15(
106 value, 1, DCP, controller_id,
107 DVMM_PTE_CONTROL,
108 DVMM_PTE_BUFFER_MODE0);
109
110 set_reg_field_value_soc15(
111 value, 1, DCP, controller_id,
112 DVMM_PTE_CONTROL,
113 DVMM_PTE_BUFFER_MODE1);
114
115 dm_write_reg(ctx, addr, value);*/
116
117 addr = mmDVMM_PTE_REQ;
118 value = dm_read_reg(ctx, addr);
119
120 chunk_int = get_reg_field_value(
121 value,
122 DVMM_PTE_REQ,
123 HFLIP_PTEREQ_PER_CHUNK_INT);
124
125 chunk_mul = get_reg_field_value(
126 value,
127 DVMM_PTE_REQ,
128 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
129
130 if (chunk_int != 0x4 || chunk_mul != 0x4) {
131
132 set_reg_field_value(
133 value,
134 255,
135 DVMM_PTE_REQ,
136 MAX_PTEREQ_TO_ISSUE);
137
138 set_reg_field_value(
139 value,
140 4,
141 DVMM_PTE_REQ,
142 HFLIP_PTEREQ_PER_CHUNK_INT);
143
144 set_reg_field_value(
145 value,
146 4,
147 DVMM_PTE_REQ,
148 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
149
150 dm_write_reg(ctx, addr, value);
151 }
152 }
153 #endif
154
dce120_enable_display_power_gating(struct dc * dc,uint8_t controller_id,struct dc_bios * dcb,enum pipe_gating_control power_gating)155 static bool dce120_enable_display_power_gating(
156 struct dc *dc,
157 uint8_t controller_id,
158 struct dc_bios *dcb,
159 enum pipe_gating_control power_gating)
160 {
161 /* disable for bringup */
162 #if 0
163 enum bp_result bp_result = BP_RESULT_OK;
164 enum bp_pipe_control_action cntl;
165 struct dc_context *ctx = dc->ctx;
166
167 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
168 return true;
169
170 if (power_gating == PIPE_GATING_CONTROL_INIT)
171 cntl = ASIC_PIPE_INIT;
172 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
173 cntl = ASIC_PIPE_ENABLE;
174 else
175 cntl = ASIC_PIPE_DISABLE;
176
177 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
178
179 bp_result = dcb->funcs->enable_disp_power_gating(
180 dcb, controller_id + 1, cntl);
181
182 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
183 * by default when command table is called
184 */
185 dm_write_reg(ctx,
186 HW_REG_CRTC(mmCRTC0_CRTC_MASTER_UPDATE_MODE, controller_id),
187 0);
188 }
189
190 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
191 dce120_init_pte(ctx, controller_id);
192
193 if (bp_result == BP_RESULT_OK)
194 return true;
195 else
196 return false;
197 #endif
198 return false;
199 }
200
dce120_update_dchub(struct dce_hwseq * hws,struct dchub_init_data * dh_data)201 static void dce120_update_dchub(
202 struct dce_hwseq *hws,
203 struct dchub_init_data *dh_data)
204 {
205 /* TODO: port code from dal2 */
206 switch (dh_data->fb_mode) {
207 case FRAME_BUFFER_MODE_ZFB_ONLY:
208 /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
209 REG_UPDATE_2(DCHUB_FB_LOCATION,
210 FB_TOP, 0,
211 FB_BASE, 0x0FFFF);
212
213 REG_UPDATE(DCHUB_AGP_BASE,
214 AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
215
216 REG_UPDATE(DCHUB_AGP_BOT,
217 AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
218
219 REG_UPDATE(DCHUB_AGP_TOP,
220 AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
221 break;
222 case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
223 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
224 REG_UPDATE(DCHUB_AGP_BASE,
225 AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
226
227 REG_UPDATE(DCHUB_AGP_BOT,
228 AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
229
230 REG_UPDATE(DCHUB_AGP_TOP,
231 AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
232 break;
233 case FRAME_BUFFER_MODE_LOCAL_ONLY:
234 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
235 REG_UPDATE(DCHUB_AGP_BASE,
236 AGP_BASE, 0);
237
238 REG_UPDATE(DCHUB_AGP_BOT,
239 AGP_BOT, 0x03FFFF);
240
241 REG_UPDATE(DCHUB_AGP_TOP,
242 AGP_TOP, 0);
243 break;
244 default:
245 break;
246 }
247
248 dh_data->dchub_initialzied = true;
249 dh_data->dchub_info_valid = false;
250 }
251
252 /**
253 * dce121_xgmi_enabled() - Check if xGMI is enabled
254 * @hws: DCE hardware sequencer object
255 *
256 * Return true if xGMI is enabled. False otherwise.
257 */
dce121_xgmi_enabled(struct dce_hwseq * hws)258 bool dce121_xgmi_enabled(struct dce_hwseq *hws)
259 {
260 uint32_t pf_max_region;
261
262 REG_GET(MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, &pf_max_region);
263 /* PF_MAX_REGION == 0 means xgmi is disabled */
264 return !!pf_max_region;
265 }
266
dce120_hw_sequencer_construct(struct dc * dc)267 void dce120_hw_sequencer_construct(struct dc *dc)
268 {
269 /* All registers used by dce11.2 match those in dce11 in offset and
270 * structure
271 */
272 dce110_hw_sequencer_construct(dc);
273 dc->hwseq->funcs.enable_display_power_gating = dce120_enable_display_power_gating;
274 dc->hwss.update_dchub = dce120_update_dchub;
275 }
276
277