1 /* $NetBSD: amdgpu_dce112_clk_mgr.c,v 1.2 2021/12/18 23:45:01 riastradh Exp $ */
2
3 /*
4 * Copyright 2012-16 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce112_clk_mgr.c,v 1.2 2021/12/18 23:45:01 riastradh Exp $");
30
31 #include "core_types.h"
32 #include "clk_mgr_internal.h"
33
34 #include "dce/dce_11_2_d.h"
35 #include "dce/dce_11_2_sh_mask.h"
36 #include "dce100/dce_clk_mgr.h"
37 #include "dce110/dce110_clk_mgr.h"
38 #include "dce112_clk_mgr.h"
39 #include "dal_asic_id.h"
40
41 /* set register offset */
42 #define SR(reg_name)\
43 .reg_name = mm ## reg_name
44
45 /* set register offset with instance */
46 #define SRI(reg_name, block, id)\
47 .reg_name = mm ## block ## id ## _ ## reg_name
48
49 static const struct clk_mgr_registers disp_clk_regs = {
50 CLK_COMMON_REG_LIST_DCE_BASE()
51 };
52
53 static const struct clk_mgr_shift disp_clk_shift = {
54 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
55 };
56
57 static const struct clk_mgr_mask disp_clk_mask = {
58 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
59 };
60
61 static const struct state_dependent_clocks dce112_max_clks_by_state[] = {
62 /*ClocksStateInvalid - should not be used*/
63 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
64 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
65 { .display_clk_khz = 389189, .pixel_clk_khz = 346672 },
66 /*ClocksStateLow*/
67 { .display_clk_khz = 459000, .pixel_clk_khz = 400000 },
68 /*ClocksStateNominal*/
69 { .display_clk_khz = 667000, .pixel_clk_khz = 600000 },
70 /*ClocksStatePerformance*/
71 { .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } };
72
73
74 //TODO: remove use the two broken down functions
dce112_set_clock(struct clk_mgr * clk_mgr_base,int requested_clk_khz)75 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
76 {
77 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
78 struct bp_set_dce_clock_parameters dce_clk_params;
79 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios;
80 struct dc *dc = clk_mgr_base->ctx->dc;
81 struct dmcu *dmcu = dc->res_pool->dmcu;
82 int actual_clock = requested_clk_khz;
83 /* Prepare to program display clock*/
84 memset(&dce_clk_params, 0, sizeof(dce_clk_params));
85
86 /* Make sure requested clock isn't lower than minimum threshold*/
87 if (requested_clk_khz > 0)
88 requested_clk_khz = max(requested_clk_khz,
89 clk_mgr_dce->base.dentist_vco_freq_khz / 62);
90
91 dce_clk_params.target_clock_frequency = requested_clk_khz;
92 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
93 dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
94
95 bp->funcs->set_dce_clock(bp, &dce_clk_params);
96 actual_clock = dce_clk_params.target_clock_frequency;
97
98 /*
99 * from power down, we need mark the clock state as ClocksStateNominal
100 * from HWReset, so when resume we will call pplib voltage regulator.
101 */
102 if (requested_clk_khz == 0)
103 clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
104
105 /*Program DP ref Clock*/
106 /*VBIOS will determine DPREFCLK frequency, so we don't set it*/
107 dce_clk_params.target_clock_frequency = 0;
108 dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
109 if (!ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))
110 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
111 (dce_clk_params.pll_id ==
112 CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
113 else
114 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
115
116 bp->funcs->set_dce_clock(bp, &dce_clk_params);
117
118 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
119 if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
120 if (clk_mgr_dce->dfs_bypass_disp_clk != actual_clock)
121 dmcu->funcs->set_psr_wait_loop(dmcu,
122 actual_clock / 1000 / 7);
123 }
124 }
125
126 clk_mgr_dce->dfs_bypass_disp_clk = actual_clock;
127 return actual_clock;
128 }
129
dce112_set_dispclk(struct clk_mgr_internal * clk_mgr,int requested_clk_khz)130 int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
131 {
132 struct bp_set_dce_clock_parameters dce_clk_params;
133 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
134 struct dc *dc = clk_mgr->base.ctx->dc;
135 struct dmcu *dmcu = dc->res_pool->dmcu;
136 int actual_clock = requested_clk_khz;
137 /* Prepare to program display clock*/
138 memset(&dce_clk_params, 0, sizeof(dce_clk_params));
139
140 /* Make sure requested clock isn't lower than minimum threshold*/
141 if (requested_clk_khz > 0)
142 requested_clk_khz = max(requested_clk_khz,
143 clk_mgr->base.dentist_vco_freq_khz / 62);
144
145 dce_clk_params.target_clock_frequency = requested_clk_khz;
146 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
147 dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK;
148
149 bp->funcs->set_dce_clock(bp, &dce_clk_params);
150 actual_clock = dce_clk_params.target_clock_frequency;
151
152 /*
153 * from power down, we need mark the clock state as ClocksStateNominal
154 * from HWReset, so when resume we will call pplib voltage regulator.
155 */
156 if (requested_clk_khz == 0)
157 clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
158
159
160 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
161 if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
162 if (clk_mgr->dfs_bypass_disp_clk != actual_clock)
163 dmcu->funcs->set_psr_wait_loop(dmcu,
164 actual_clock / 1000 / 7);
165 }
166 }
167
168 clk_mgr->dfs_bypass_disp_clk = actual_clock;
169 return actual_clock;
170
171 }
172
dce112_set_dprefclk(struct clk_mgr_internal * clk_mgr)173 int dce112_set_dprefclk(struct clk_mgr_internal *clk_mgr)
174 {
175 struct bp_set_dce_clock_parameters dce_clk_params;
176 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios;
177
178 memset(&dce_clk_params, 0, sizeof(dce_clk_params));
179
180 /*Program DP ref Clock*/
181 /*VBIOS will determine DPREFCLK frequency, so we don't set it*/
182 dce_clk_params.target_clock_frequency = 0;
183 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS;
184 dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK;
185 if (!ASICREV_IS_VEGA20_P(clk_mgr->base.ctx->asic_id.hw_internal_rev))
186 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK =
187 (dce_clk_params.pll_id ==
188 CLOCK_SOURCE_COMBO_DISPLAY_PLL0);
189 else
190 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false;
191
192 bp->funcs->set_dce_clock(bp, &dce_clk_params);
193
194 /* Returns the dp_refclk that was set */
195 return dce_clk_params.target_clock_frequency;
196 }
197
dce112_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)198 static void dce112_update_clocks(struct clk_mgr *clk_mgr_base,
199 struct dc_state *context,
200 bool safe_to_lower)
201 {
202 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
203 struct dm_pp_power_level_change_request level_change_req;
204 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
205
206 /*TODO: W/A for dal3 linux, investigate why this works */
207 if (!clk_mgr_dce->dfs_bypass_active)
208 patched_disp_clk = patched_disp_clk * 115 / 100;
209
210 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
211 /* get max clock state from PPLIB */
212 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)
213 || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {
214 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))
215 clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
216 }
217
218 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
219 patched_disp_clk = dce112_set_clock(clk_mgr_base, patched_disp_clk);
220 clk_mgr_base->clks.dispclk_khz = patched_disp_clk;
221 }
222 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
223 }
224
225 static struct clk_mgr_funcs dce112_funcs = {
226 .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz,
227 .update_clocks = dce112_update_clocks
228 };
229
dce112_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr)230 void dce112_clk_mgr_construct(
231 struct dc_context *ctx,
232 struct clk_mgr_internal *clk_mgr)
233 {
234 dce_clk_mgr_construct(ctx, clk_mgr);
235
236 memcpy(clk_mgr->max_clks_by_state,
237 dce112_max_clks_by_state,
238 sizeof(dce112_max_clks_by_state));
239
240 clk_mgr->regs = &disp_clk_regs;
241 clk_mgr->clk_mgr_shift = &disp_clk_shift;
242 clk_mgr->clk_mgr_mask = &disp_clk_mask;
243 clk_mgr->base.funcs = &dce112_funcs;
244 }
245