1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #include "dm_services.h"
26
27 #include "link_encoder.h"
28 #include "stream_encoder.h"
29
30 #include "resource.h"
31 #include "include/irq_service_interface.h"
32 #include "../virtual/virtual_stream_encoder.h"
33 #include "dce110/dce110_resource.h"
34 #include "dce110/dce110_timing_generator.h"
35 #include "irq/dce110/irq_service_dce110.h"
36 #include "dce/dce_link_encoder.h"
37 #include "dce/dce_stream_encoder.h"
38
39 #include "dce/dce_mem_input.h"
40 #include "dce/dce_ipp.h"
41 #include "dce/dce_transform.h"
42 #include "dce/dce_opp.h"
43 #include "dce/dce_clocks.h"
44 #include "dce/dce_clock_source.h"
45 #include "dce/dce_audio.h"
46 #include "dce/dce_hwseq.h"
47 #include "dce100/dce100_hw_sequencer.h"
48
49 #include "reg_helper.h"
50
51 #include "dce/dce_10_0_d.h"
52 #include "dce/dce_10_0_sh_mask.h"
53
54 #include "dce/dce_dmcu.h"
55 #include "dce/dce_aux.h"
56 #include "dce/dce_abm.h"
57
58 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
59 #include "gmc/gmc_8_2_d.h"
60 #include "gmc/gmc_8_2_sh_mask.h"
61 #endif
62
63 #include "dce100/dce100_resource.h"
64
65 #ifndef mmDP_DPHY_INTERNAL_CTRL
66 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
67 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
68 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
69 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
70 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
71 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
72 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
73 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
74 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
75 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
76 #endif
77
78 #ifndef mmBIOS_SCRATCH_2
79 #define mmBIOS_SCRATCH_2 0x05CB
80 #define mmBIOS_SCRATCH_6 0x05CF
81 #endif
82
83 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
84 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
85 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
86 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
87 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
88 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
89 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
90 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
91 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
92 #endif
93
94 #ifndef mmDP_DPHY_FAST_TRAINING
95 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
96 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
97 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
98 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
99 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
100 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
101 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
102 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
103 #endif
104
105 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
106 {
107 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
108 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
109 },
110 {
111 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
112 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
113 },
114 {
115 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
116 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
117 },
118 {
119 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
120 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
121 },
122 {
123 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
124 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
125 },
126 {
127 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
128 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
129 }
130 };
131
132 /* set register offset */
133 #define SR(reg_name)\
134 .reg_name = mm ## reg_name
135
136 /* set register offset with instance */
137 #define SRI(reg_name, block, id)\
138 .reg_name = mm ## block ## id ## _ ## reg_name
139
140
141 static const struct dccg_registers disp_clk_regs = {
142 CLK_COMMON_REG_LIST_DCE_BASE()
143 };
144
145 static const struct dccg_shift disp_clk_shift = {
146 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
147 };
148
149 static const struct dccg_mask disp_clk_mask = {
150 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
151 };
152
153 #define ipp_regs(id)\
154 [id] = {\
155 IPP_DCE100_REG_LIST_DCE_BASE(id)\
156 }
157
158 static const struct dce_ipp_registers ipp_regs[] = {
159 ipp_regs(0),
160 ipp_regs(1),
161 ipp_regs(2),
162 ipp_regs(3),
163 ipp_regs(4),
164 ipp_regs(5)
165 };
166
167 static const struct dce_ipp_shift ipp_shift = {
168 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
169 };
170
171 static const struct dce_ipp_mask ipp_mask = {
172 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
173 };
174
175 #define transform_regs(id)\
176 [id] = {\
177 XFM_COMMON_REG_LIST_DCE100(id)\
178 }
179
180 static const struct dce_transform_registers xfm_regs[] = {
181 transform_regs(0),
182 transform_regs(1),
183 transform_regs(2),
184 transform_regs(3),
185 transform_regs(4),
186 transform_regs(5)
187 };
188
189 static const struct dce_transform_shift xfm_shift = {
190 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
191 };
192
193 static const struct dce_transform_mask xfm_mask = {
194 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
195 };
196
197 #define aux_regs(id)\
198 [id] = {\
199 AUX_REG_LIST(id)\
200 }
201
202 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
203 aux_regs(0),
204 aux_regs(1),
205 aux_regs(2),
206 aux_regs(3),
207 aux_regs(4),
208 aux_regs(5)
209 };
210
211 #define hpd_regs(id)\
212 [id] = {\
213 HPD_REG_LIST(id)\
214 }
215
216 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
217 hpd_regs(0),
218 hpd_regs(1),
219 hpd_regs(2),
220 hpd_regs(3),
221 hpd_regs(4),
222 hpd_regs(5)
223 };
224
225 #define link_regs(id)\
226 [id] = {\
227 LE_DCE100_REG_LIST(id)\
228 }
229
230 static const struct dce110_link_enc_registers link_enc_regs[] = {
231 link_regs(0),
232 link_regs(1),
233 link_regs(2),
234 link_regs(3),
235 link_regs(4),
236 link_regs(5),
237 link_regs(6),
238 };
239
240 #define stream_enc_regs(id)\
241 [id] = {\
242 SE_COMMON_REG_LIST_DCE_BASE(id),\
243 .AFMT_CNTL = 0,\
244 }
245
246 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
247 stream_enc_regs(0),
248 stream_enc_regs(1),
249 stream_enc_regs(2),
250 stream_enc_regs(3),
251 stream_enc_regs(4),
252 stream_enc_regs(5),
253 stream_enc_regs(6)
254 };
255
256 static const struct dce_stream_encoder_shift se_shift = {
257 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
258 };
259
260 static const struct dce_stream_encoder_mask se_mask = {
261 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
262 };
263
264 #define opp_regs(id)\
265 [id] = {\
266 OPP_DCE_100_REG_LIST(id),\
267 }
268
269 static const struct dce_opp_registers opp_regs[] = {
270 opp_regs(0),
271 opp_regs(1),
272 opp_regs(2),
273 opp_regs(3),
274 opp_regs(4),
275 opp_regs(5)
276 };
277
278 static const struct dce_opp_shift opp_shift = {
279 OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT)
280 };
281
282 static const struct dce_opp_mask opp_mask = {
283 OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK)
284 };
285 #define aux_engine_regs(id)\
286 [id] = {\
287 AUX_COMMON_REG_LIST(id), \
288 .AUX_RESET_MASK = 0 \
289 }
290
291 static const struct dce110_aux_registers aux_engine_regs[] = {
292 aux_engine_regs(0),
293 aux_engine_regs(1),
294 aux_engine_regs(2),
295 aux_engine_regs(3),
296 aux_engine_regs(4),
297 aux_engine_regs(5)
298 };
299
300 #define audio_regs(id)\
301 [id] = {\
302 AUD_COMMON_REG_LIST(id)\
303 }
304
305 static const struct dce_audio_registers audio_regs[] = {
306 audio_regs(0),
307 audio_regs(1),
308 audio_regs(2),
309 audio_regs(3),
310 audio_regs(4),
311 audio_regs(5),
312 audio_regs(6),
313 };
314
315 static const struct dce_audio_shift audio_shift = {
316 AUD_COMMON_MASK_SH_LIST(__SHIFT)
317 };
318
319 static const struct dce_aduio_mask audio_mask = {
320 AUD_COMMON_MASK_SH_LIST(_MASK)
321 };
322
323 #define clk_src_regs(id)\
324 [id] = {\
325 CS_COMMON_REG_LIST_DCE_100_110(id),\
326 }
327
328 static const struct dce110_clk_src_regs clk_src_regs[] = {
329 clk_src_regs(0),
330 clk_src_regs(1),
331 clk_src_regs(2)
332 };
333
334 static const struct dce110_clk_src_shift cs_shift = {
335 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
336 };
337
338 static const struct dce110_clk_src_mask cs_mask = {
339 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
340 };
341
342 static const struct dce_dmcu_registers dmcu_regs = {
343 DMCU_DCE110_COMMON_REG_LIST()
344 };
345
346 static const struct dce_dmcu_shift dmcu_shift = {
347 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
348 };
349
350 static const struct dce_dmcu_mask dmcu_mask = {
351 DMCU_MASK_SH_LIST_DCE110(_MASK)
352 };
353
354 static const struct dce_abm_registers abm_regs = {
355 ABM_DCE110_COMMON_REG_LIST()
356 };
357
358 static const struct dce_abm_shift abm_shift = {
359 ABM_MASK_SH_LIST_DCE110(__SHIFT)
360 };
361
362 static const struct dce_abm_mask abm_mask = {
363 ABM_MASK_SH_LIST_DCE110(_MASK)
364 };
365
366 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
367
368 static const struct bios_registers bios_regs = {
369 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
370 };
371
372 static const struct resource_caps res_cap = {
373 .num_timing_generator = 6,
374 .num_audio = 6,
375 .num_stream_encoder = 6,
376 .num_pll = 3
377 };
378
379 #define CTX ctx
380 #define REG(reg) mm ## reg
381
382 #ifndef mmCC_DC_HDMI_STRAPS
383 #define mmCC_DC_HDMI_STRAPS 0x1918
384 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
385 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
386 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
387 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
388 #endif
389
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)390 static void read_dce_straps(
391 struct dc_context *ctx,
392 struct resource_straps *straps)
393 {
394 REG_GET_2(CC_DC_HDMI_STRAPS,
395 HDMI_DISABLE, &straps->hdmi_disable,
396 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
397
398 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
399 }
400
create_audio(struct dc_context * ctx,unsigned int inst)401 static struct audio *create_audio(
402 struct dc_context *ctx, unsigned int inst)
403 {
404 return dce_audio_create(ctx, inst,
405 &audio_regs[inst], &audio_shift, &audio_mask);
406 }
407
dce100_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)408 static struct timing_generator *dce100_timing_generator_create(
409 struct dc_context *ctx,
410 uint32_t instance,
411 const struct dce110_timing_generator_offsets *offsets)
412 {
413 struct dce110_timing_generator *tg110 =
414 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
415
416 if (!tg110)
417 return NULL;
418
419 dce110_timing_generator_construct(tg110, ctx, instance, offsets);
420 return &tg110->base;
421 }
422
dce100_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)423 static struct stream_encoder *dce100_stream_encoder_create(
424 enum engine_id eng_id,
425 struct dc_context *ctx)
426 {
427 struct dce110_stream_encoder *enc110 =
428 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
429
430 if (!enc110)
431 return NULL;
432
433 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
434 &stream_enc_regs[eng_id], &se_shift, &se_mask);
435 return &enc110->base;
436 }
437
438 #define SRII(reg_name, block, id)\
439 .reg_name[id] = mm ## block ## id ## _ ## reg_name
440
441 static const struct dce_hwseq_registers hwseq_reg = {
442 HWSEQ_DCE10_REG_LIST()
443 };
444
445 static const struct dce_hwseq_shift hwseq_shift = {
446 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT)
447 };
448
449 static const struct dce_hwseq_mask hwseq_mask = {
450 HWSEQ_DCE10_MASK_SH_LIST(_MASK)
451 };
452
dce100_hwseq_create(struct dc_context * ctx)453 static struct dce_hwseq *dce100_hwseq_create(
454 struct dc_context *ctx)
455 {
456 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
457
458 if (hws) {
459 hws->ctx = ctx;
460 hws->regs = &hwseq_reg;
461 hws->shifts = &hwseq_shift;
462 hws->masks = &hwseq_mask;
463 }
464 return hws;
465 }
466
467 static const struct resource_create_funcs res_create_funcs = {
468 .read_dce_straps = read_dce_straps,
469 .create_audio = create_audio,
470 .create_stream_encoder = dce100_stream_encoder_create,
471 .create_hwseq = dce100_hwseq_create,
472 };
473
474 #define mi_inst_regs(id) { \
475 MI_DCE8_REG_LIST(id), \
476 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
477 }
478 static const struct dce_mem_input_registers mi_regs[] = {
479 mi_inst_regs(0),
480 mi_inst_regs(1),
481 mi_inst_regs(2),
482 mi_inst_regs(3),
483 mi_inst_regs(4),
484 mi_inst_regs(5),
485 };
486
487 static const struct dce_mem_input_shift mi_shifts = {
488 MI_DCE8_MASK_SH_LIST(__SHIFT),
489 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
490 };
491
492 static const struct dce_mem_input_mask mi_masks = {
493 MI_DCE8_MASK_SH_LIST(_MASK),
494 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
495 };
496
dce100_mem_input_create(struct dc_context * ctx,uint32_t inst)497 static struct mem_input *dce100_mem_input_create(
498 struct dc_context *ctx,
499 uint32_t inst)
500 {
501 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
502 GFP_KERNEL);
503
504 if (!dce_mi) {
505 BREAK_TO_DEBUGGER();
506 return NULL;
507 }
508
509 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
510 dce_mi->wa.single_head_rdreq_dmif_limit = 2;
511 return &dce_mi->base;
512 }
513
dce100_transform_destroy(struct transform ** xfm)514 static void dce100_transform_destroy(struct transform **xfm)
515 {
516 kfree(TO_DCE_TRANSFORM(*xfm));
517 *xfm = NULL;
518 }
519
dce100_transform_create(struct dc_context * ctx,uint32_t inst)520 static struct transform *dce100_transform_create(
521 struct dc_context *ctx,
522 uint32_t inst)
523 {
524 struct dce_transform *transform =
525 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
526
527 if (!transform)
528 return NULL;
529
530 dce_transform_construct(transform, ctx, inst,
531 &xfm_regs[inst], &xfm_shift, &xfm_mask);
532 return &transform->base;
533 }
534
dce100_ipp_create(struct dc_context * ctx,uint32_t inst)535 static struct input_pixel_processor *dce100_ipp_create(
536 struct dc_context *ctx, uint32_t inst)
537 {
538 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
539
540 if (!ipp) {
541 BREAK_TO_DEBUGGER();
542 return NULL;
543 }
544
545 dce_ipp_construct(ipp, ctx, inst,
546 &ipp_regs[inst], &ipp_shift, &ipp_mask);
547 return &ipp->base;
548 }
549
550 static const struct encoder_feature_support link_enc_feature = {
551 .max_hdmi_deep_color = COLOR_DEPTH_121212,
552 .max_hdmi_pixel_clock = 300000,
553 .flags.bits.IS_HBR2_CAPABLE = true,
554 .flags.bits.IS_TPS3_CAPABLE = true,
555 .flags.bits.IS_YCBCR_CAPABLE = true
556 };
557
558 static
dce100_link_encoder_create(const struct encoder_init_data * enc_init_data)559 struct link_encoder *dce100_link_encoder_create(
560 const struct encoder_init_data *enc_init_data)
561 {
562 struct dce110_link_encoder *enc110 =
563 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
564
565 if (!enc110)
566 return NULL;
567
568 dce110_link_encoder_construct(enc110,
569 enc_init_data,
570 &link_enc_feature,
571 &link_enc_regs[enc_init_data->transmitter],
572 &link_enc_aux_regs[enc_init_data->channel - 1],
573 &link_enc_hpd_regs[enc_init_data->hpd_source]);
574 return &enc110->base;
575 }
576
577 static
dce100_opp_create(struct dc_context * ctx,uint32_t inst)578 struct output_pixel_processor *dce100_opp_create(
579 struct dc_context *ctx,
580 uint32_t inst)
581 {
582 struct dce110_opp *opp =
583 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
584
585 if (!opp)
586 return NULL;
587
588 dce110_opp_construct(opp,
589 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
590 return &opp->base;
591 }
592
593 static
dce100_aux_engine_create(struct dc_context * ctx,uint32_t inst)594 struct aux_engine *dce100_aux_engine_create(
595 struct dc_context *ctx,
596 uint32_t inst)
597 {
598 struct aux_engine_dce110 *aux_engine =
599 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
600
601 if (!aux_engine)
602 return NULL;
603
604 dce110_aux_engine_construct(aux_engine, ctx, inst,
605 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
606 &aux_engine_regs[inst]);
607
608 return &aux_engine->base;
609 }
610
611 static
dce100_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)612 struct clock_source *dce100_clock_source_create(
613 struct dc_context *ctx,
614 struct dc_bios *bios,
615 enum clock_source_id id,
616 const struct dce110_clk_src_regs *regs,
617 bool dp_clk_src)
618 {
619 struct dce110_clk_src *clk_src =
620 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
621
622 if (!clk_src)
623 return NULL;
624
625 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
626 regs, &cs_shift, &cs_mask)) {
627 clk_src->base.dp_clk_src = dp_clk_src;
628 return &clk_src->base;
629 }
630
631 BREAK_TO_DEBUGGER();
632 return NULL;
633 }
634
635 static
dce100_clock_source_destroy(struct clock_source ** clk_src)636 void dce100_clock_source_destroy(struct clock_source **clk_src)
637 {
638 kfree(TO_DCE110_CLK_SRC(*clk_src));
639 *clk_src = NULL;
640 }
641
destruct(struct dce110_resource_pool * pool)642 static void destruct(struct dce110_resource_pool *pool)
643 {
644 unsigned int i;
645
646 for (i = 0; i < pool->base.pipe_count; i++) {
647 if (pool->base.opps[i] != NULL)
648 dce110_opp_destroy(&pool->base.opps[i]);
649
650 if (pool->base.transforms[i] != NULL)
651 dce100_transform_destroy(&pool->base.transforms[i]);
652
653 if (pool->base.ipps[i] != NULL)
654 dce_ipp_destroy(&pool->base.ipps[i]);
655
656 if (pool->base.mis[i] != NULL) {
657 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
658 pool->base.mis[i] = NULL;
659 }
660
661 if (pool->base.timing_generators[i] != NULL) {
662 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
663 pool->base.timing_generators[i] = NULL;
664 }
665
666 if (pool->base.engines[i] != NULL)
667 dce110_engine_destroy(&pool->base.engines[i]);
668
669 }
670
671 for (i = 0; i < pool->base.stream_enc_count; i++) {
672 if (pool->base.stream_enc[i] != NULL)
673 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
674 }
675
676 for (i = 0; i < pool->base.clk_src_count; i++) {
677 if (pool->base.clock_sources[i] != NULL)
678 dce100_clock_source_destroy(&pool->base.clock_sources[i]);
679 }
680
681 if (pool->base.dp_clock_source != NULL)
682 dce100_clock_source_destroy(&pool->base.dp_clock_source);
683
684 for (i = 0; i < pool->base.audio_count; i++) {
685 if (pool->base.audios[i] != NULL)
686 dce_aud_destroy(&pool->base.audios[i]);
687 }
688
689 if (pool->base.dccg != NULL)
690 dce_dccg_destroy(&pool->base.dccg);
691
692 if (pool->base.abm != NULL)
693 dce_abm_destroy(&pool->base.abm);
694
695 if (pool->base.dmcu != NULL)
696 dce_dmcu_destroy(&pool->base.dmcu);
697
698 if (pool->base.irqs != NULL)
699 dal_irq_service_destroy(&pool->base.irqs);
700 }
701
build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)702 static enum dc_status build_mapped_resource(
703 const struct dc *dc,
704 struct dc_state *context,
705 struct dc_stream_state *stream)
706 {
707 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
708
709 if (!pipe_ctx)
710 return DC_ERROR_UNEXPECTED;
711
712 dce110_resource_build_pipe_hw_param(pipe_ctx);
713
714 resource_build_info_frame(pipe_ctx);
715
716 return DC_OK;
717 }
718
719 static
dce100_validate_bandwidth(struct dc * dc,struct dc_state * context)720 bool dce100_validate_bandwidth(
721 struct dc *dc,
722 struct dc_state *context)
723 {
724 int i;
725 bool at_least_one_pipe = false;
726
727 for (i = 0; i < dc->res_pool->pipe_count; i++) {
728 if (context->res_ctx.pipe_ctx[i].stream)
729 at_least_one_pipe = true;
730 }
731
732 if (at_least_one_pipe) {
733 /* TODO implement when needed but for now hardcode max value*/
734 context->bw.dce.dispclk_khz = 681000;
735 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
736 } else {
737 context->bw.dce.dispclk_khz = 0;
738 context->bw.dce.yclk_khz = 0;
739 }
740
741 return true;
742 }
743
dce100_validate_surface_sets(struct dc_state * context)744 static bool dce100_validate_surface_sets(
745 struct dc_state *context)
746 {
747 int i;
748
749 for (i = 0; i < context->stream_count; i++) {
750 if (context->stream_status[i].plane_count == 0)
751 continue;
752
753 if (context->stream_status[i].plane_count > 1)
754 return false;
755
756 if (context->stream_status[i].plane_states[0]->format
757 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
758 return false;
759 }
760
761 return true;
762 }
763
764 static
dce100_validate_global(struct dc * dc,struct dc_state * context)765 enum dc_status dce100_validate_global(
766 struct dc *dc,
767 struct dc_state *context)
768 {
769 if (!dce100_validate_surface_sets(context))
770 return DC_FAIL_SURFACE_VALIDATE;
771
772 return DC_OK;
773 }
774
dce100_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)775 enum dc_status dce100_add_stream_to_ctx(
776 struct dc *dc,
777 struct dc_state *new_ctx,
778 struct dc_stream_state *dc_stream)
779 {
780 enum dc_status result = DC_ERROR_UNEXPECTED;
781
782 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
783
784 if (result == DC_OK)
785 result = resource_map_clock_resources(dc, new_ctx, dc_stream);
786
787 if (result == DC_OK)
788 result = build_mapped_resource(dc, new_ctx, dc_stream);
789
790 return result;
791 }
792
dce100_destroy_resource_pool(struct resource_pool ** pool)793 static void dce100_destroy_resource_pool(struct resource_pool **pool)
794 {
795 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
796
797 destruct(dce110_pool);
798 kfree(dce110_pool);
799 *pool = NULL;
800 }
801
dce100_validate_plane(const struct dc_plane_state * plane_state,struct dc_caps * caps)802 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
803 {
804
805 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
806 return DC_OK;
807
808 return DC_FAIL_SURFACE_VALIDATE;
809 }
810
811 static const struct resource_funcs dce100_res_pool_funcs = {
812 .destroy = dce100_destroy_resource_pool,
813 .link_enc_create = dce100_link_encoder_create,
814 .validate_bandwidth = dce100_validate_bandwidth,
815 .validate_plane = dce100_validate_plane,
816 .add_stream_to_ctx = dce100_add_stream_to_ctx,
817 .validate_global = dce100_validate_global
818 };
819
construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)820 static bool construct(
821 uint8_t num_virtual_links,
822 struct dc *dc,
823 struct dce110_resource_pool *pool)
824 {
825 unsigned int i;
826 struct dc_context *ctx = dc->ctx;
827 struct dc_firmware_info info;
828 struct dc_bios *bp;
829 struct dm_pp_static_clock_info static_clk_info = {0};
830
831 ctx->dc_bios->regs = &bios_regs;
832
833 pool->base.res_cap = &res_cap;
834 pool->base.funcs = &dce100_res_pool_funcs;
835 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
836
837 bp = ctx->dc_bios;
838
839 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
840 info.external_clock_source_frequency_for_dp != 0) {
841 pool->base.dp_clock_source =
842 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
843
844 pool->base.clock_sources[0] =
845 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
846 pool->base.clock_sources[1] =
847 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
848 pool->base.clock_sources[2] =
849 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
850 pool->base.clk_src_count = 3;
851
852 } else {
853 pool->base.dp_clock_source =
854 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
855
856 pool->base.clock_sources[0] =
857 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
858 pool->base.clock_sources[1] =
859 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
860 pool->base.clk_src_count = 2;
861 }
862
863 if (pool->base.dp_clock_source == NULL) {
864 dm_error("DC: failed to create dp clock source!\n");
865 BREAK_TO_DEBUGGER();
866 goto res_create_fail;
867 }
868
869 for (i = 0; i < pool->base.clk_src_count; i++) {
870 if (pool->base.clock_sources[i] == NULL) {
871 dm_error("DC: failed to create clock sources!\n");
872 BREAK_TO_DEBUGGER();
873 goto res_create_fail;
874 }
875 }
876
877 pool->base.dccg = dce_dccg_create(ctx,
878 &disp_clk_regs,
879 &disp_clk_shift,
880 &disp_clk_mask);
881 if (pool->base.dccg == NULL) {
882 dm_error("DC: failed to create display clock!\n");
883 BREAK_TO_DEBUGGER();
884 goto res_create_fail;
885 }
886
887 pool->base.dmcu = dce_dmcu_create(ctx,
888 &dmcu_regs,
889 &dmcu_shift,
890 &dmcu_mask);
891 if (pool->base.dmcu == NULL) {
892 dm_error("DC: failed to create dmcu!\n");
893 BREAK_TO_DEBUGGER();
894 goto res_create_fail;
895 }
896
897 pool->base.abm = dce_abm_create(ctx,
898 &abm_regs,
899 &abm_shift,
900 &abm_mask);
901 if (pool->base.abm == NULL) {
902 dm_error("DC: failed to create abm!\n");
903 BREAK_TO_DEBUGGER();
904 goto res_create_fail;
905 }
906
907 /* get static clock information for PPLIB or firmware, save
908 * max_clock_state
909 */
910 if (dm_pp_get_static_clocks(ctx, &static_clk_info))
911 pool->base.dccg->max_clks_state =
912 static_clk_info.max_clocks_state;
913 {
914 struct irq_service_init_data init_data;
915 init_data.ctx = dc->ctx;
916 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
917 if (!pool->base.irqs)
918 goto res_create_fail;
919 }
920
921 /*************************************************
922 * Resource + asic cap harcoding *
923 *************************************************/
924 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
925 pool->base.pipe_count = res_cap.num_timing_generator;
926 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
927 dc->caps.max_downscale_ratio = 200;
928 dc->caps.i2c_speed_in_khz = 40;
929 dc->caps.max_cursor_size = 128;
930 dc->caps.dual_link_dvi = true;
931 dc->caps.disable_dp_clk_share = true;
932 for (i = 0; i < pool->base.pipe_count; i++) {
933 pool->base.timing_generators[i] =
934 dce100_timing_generator_create(
935 ctx,
936 i,
937 &dce100_tg_offsets[i]);
938 if (pool->base.timing_generators[i] == NULL) {
939 BREAK_TO_DEBUGGER();
940 dm_error("DC: failed to create tg!\n");
941 goto res_create_fail;
942 }
943
944 pool->base.mis[i] = dce100_mem_input_create(ctx, i);
945 if (pool->base.mis[i] == NULL) {
946 BREAK_TO_DEBUGGER();
947 dm_error(
948 "DC: failed to create memory input!\n");
949 goto res_create_fail;
950 }
951
952 pool->base.ipps[i] = dce100_ipp_create(ctx, i);
953 if (pool->base.ipps[i] == NULL) {
954 BREAK_TO_DEBUGGER();
955 dm_error(
956 "DC: failed to create input pixel processor!\n");
957 goto res_create_fail;
958 }
959
960 pool->base.transforms[i] = dce100_transform_create(ctx, i);
961 if (pool->base.transforms[i] == NULL) {
962 BREAK_TO_DEBUGGER();
963 dm_error(
964 "DC: failed to create transform!\n");
965 goto res_create_fail;
966 }
967
968 pool->base.opps[i] = dce100_opp_create(ctx, i);
969 if (pool->base.opps[i] == NULL) {
970 BREAK_TO_DEBUGGER();
971 dm_error(
972 "DC: failed to create output pixel processor!\n");
973 goto res_create_fail;
974 }
975 pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
976 if (pool->base.engines[i] == NULL) {
977 BREAK_TO_DEBUGGER();
978 dm_error(
979 "DC:failed to create aux engine!!\n");
980 goto res_create_fail;
981 }
982 }
983
984 dc->caps.max_planes = pool->base.pipe_count;
985
986 if (!resource_construct(num_virtual_links, dc, &pool->base,
987 &res_create_funcs))
988 goto res_create_fail;
989
990 /* Create hardware sequencer */
991 dce100_hw_sequencer_construct(dc);
992 return true;
993
994 res_create_fail:
995 destruct(pool);
996
997 return false;
998 }
999
dce100_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1000 struct resource_pool *dce100_create_resource_pool(
1001 uint8_t num_virtual_links,
1002 struct dc *dc)
1003 {
1004 struct dce110_resource_pool *pool =
1005 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1006
1007 if (!pool)
1008 return NULL;
1009
1010 if (construct(num_virtual_links, dc, pool))
1011 return &pool->base;
1012
1013 kfree(pool);
1014 BREAK_TO_DEBUGGER();
1015 return NULL;
1016 }
1017
1018