1 /* $NetBSD: amdgpu_irq_service_dcn20.c,v 1.2 2021/12/18 23:45:06 riastradh Exp $ */
2
3 /*
4 * Copyright 2018 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_irq_service_dcn20.c,v 1.2 2021/12/18 23:45:06 riastradh Exp $");
30
31 #include <linux/slab.h>
32
33 #include "dm_services.h"
34
35 #include "include/logger_interface.h"
36
37 #include "../dce110/irq_service_dce110.h"
38
39 #include "dcn/dcn_2_0_0_offset.h"
40 #include "dcn/dcn_2_0_0_sh_mask.h"
41 #include "navi10_ip_offset.h"
42
43
44 #include "irq_service_dcn20.h"
45
46 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
47
to_dal_irq_source_dcn20(struct irq_service * irq_service,uint32_t src_id,uint32_t ext_id)48 enum dc_irq_source to_dal_irq_source_dcn20(
49 struct irq_service *irq_service,
50 uint32_t src_id,
51 uint32_t ext_id)
52 {
53 switch (src_id) {
54 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
55 return DC_IRQ_SOURCE_VBLANK1;
56 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
57 return DC_IRQ_SOURCE_VBLANK2;
58 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
59 return DC_IRQ_SOURCE_VBLANK3;
60 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
61 return DC_IRQ_SOURCE_VBLANK4;
62 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
63 return DC_IRQ_SOURCE_VBLANK5;
64 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
65 return DC_IRQ_SOURCE_VBLANK6;
66 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
67 return DC_IRQ_SOURCE_PFLIP1;
68 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
69 return DC_IRQ_SOURCE_PFLIP2;
70 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
71 return DC_IRQ_SOURCE_PFLIP3;
72 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
73 return DC_IRQ_SOURCE_PFLIP4;
74 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
75 return DC_IRQ_SOURCE_PFLIP5;
76 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
77 return DC_IRQ_SOURCE_PFLIP6;
78 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
79 return DC_IRQ_SOURCE_VUPDATE1;
80 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
81 return DC_IRQ_SOURCE_VUPDATE2;
82 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
83 return DC_IRQ_SOURCE_VUPDATE3;
84 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
85 return DC_IRQ_SOURCE_VUPDATE4;
86 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
87 return DC_IRQ_SOURCE_VUPDATE5;
88 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
89 return DC_IRQ_SOURCE_VUPDATE6;
90
91 case DCN_1_0__SRCID__DC_HPD1_INT:
92 /* generic src_id for all HPD and HPDRX interrupts */
93 switch (ext_id) {
94 case DCN_1_0__CTXID__DC_HPD1_INT:
95 return DC_IRQ_SOURCE_HPD1;
96 case DCN_1_0__CTXID__DC_HPD2_INT:
97 return DC_IRQ_SOURCE_HPD2;
98 case DCN_1_0__CTXID__DC_HPD3_INT:
99 return DC_IRQ_SOURCE_HPD3;
100 case DCN_1_0__CTXID__DC_HPD4_INT:
101 return DC_IRQ_SOURCE_HPD4;
102 case DCN_1_0__CTXID__DC_HPD5_INT:
103 return DC_IRQ_SOURCE_HPD5;
104 case DCN_1_0__CTXID__DC_HPD6_INT:
105 return DC_IRQ_SOURCE_HPD6;
106 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
107 return DC_IRQ_SOURCE_HPD1RX;
108 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
109 return DC_IRQ_SOURCE_HPD2RX;
110 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
111 return DC_IRQ_SOURCE_HPD3RX;
112 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
113 return DC_IRQ_SOURCE_HPD4RX;
114 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
115 return DC_IRQ_SOURCE_HPD5RX;
116 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
117 return DC_IRQ_SOURCE_HPD6RX;
118 default:
119 return DC_IRQ_SOURCE_INVALID;
120 }
121 break;
122
123 default:
124 return DC_IRQ_SOURCE_INVALID;
125 }
126 }
127
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)128 static bool hpd_ack(
129 struct irq_service *irq_service,
130 const struct irq_source_info *info)
131 {
132 uint32_t addr = info->status_reg;
133 uint32_t value = dm_read_reg(irq_service->ctx, addr);
134 uint32_t current_status =
135 get_reg_field_value(
136 value,
137 HPD0_DC_HPD_INT_STATUS,
138 DC_HPD_SENSE_DELAYED);
139
140 dal_irq_service_ack_generic(irq_service, info);
141
142 value = dm_read_reg(irq_service->ctx, info->enable_reg);
143
144 set_reg_field_value(
145 value,
146 current_status ? 0 : 1,
147 HPD0_DC_HPD_INT_CONTROL,
148 DC_HPD_INT_POLARITY);
149
150 dm_write_reg(irq_service->ctx, info->enable_reg, value);
151
152 return true;
153 }
154
155 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
156 .set = NULL,
157 .ack = hpd_ack
158 };
159
160 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
161 .set = NULL,
162 .ack = NULL
163 };
164
165 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
166 .set = NULL,
167 .ack = NULL
168 };
169
170 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
171 .set = NULL,
172 .ack = NULL
173 };
174
175 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
176 .set = NULL,
177 .ack = NULL
178 };
179
180 #undef BASE_INNER
181 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
182
183 /* compile time expand base address. */
184 #define BASE(seg) \
185 BASE_INNER(seg)
186
187
188 #define SRI(reg_name, block, id)\
189 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
190 mm ## block ## id ## _ ## reg_name
191
192
193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
194 .enable_reg = SRI(reg1, block, reg_num),\
195 .enable_mask = \
196 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
197 .enable_value = {\
198 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
200 },\
201 .ack_reg = SRI(reg2, block, reg_num),\
202 .ack_mask = \
203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
204 .ack_value = \
205 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
206
207
208
209 #define hpd_int_entry(reg_num)\
210 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
211 IRQ_REG_ENTRY(HPD, reg_num,\
212 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
213 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
214 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
215 .funcs = &hpd_irq_info_funcs\
216 }
217
218 #define hpd_rx_int_entry(reg_num)\
219 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
220 IRQ_REG_ENTRY(HPD, reg_num,\
221 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
222 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
223 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
224 .funcs = &hpd_rx_irq_info_funcs\
225 }
226 #define pflip_int_entry(reg_num)\
227 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
228 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
229 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
230 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
231 .funcs = &pflip_irq_info_funcs\
232 }
233
234 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
235 * of DCE's DC_IRQ_SOURCE_VUPDATEx.
236 */
237 #define vupdate_no_lock_int_entry(reg_num)\
238 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
239 IRQ_REG_ENTRY(OTG, reg_num,\
240 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
241 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
242 .funcs = &vupdate_no_lock_irq_info_funcs\
243 }
244
245 #define vblank_int_entry(reg_num)\
246 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
247 IRQ_REG_ENTRY(OTG, reg_num,\
248 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
249 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
250 .funcs = &vblank_irq_info_funcs\
251 }
252
253 #define dummy_irq_entry() \
254 {\
255 .funcs = &dummy_irq_info_funcs\
256 }
257
258 #define i2c_int_entry(reg_num) \
259 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
260
261 #define dp_sink_int_entry(reg_num) \
262 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
263
264 #define gpio_pad_int_entry(reg_num) \
265 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
266
267 #define dc_underflow_int_entry(reg_num) \
268 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
269
270 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
271 .set = dal_irq_service_dummy_set,
272 .ack = dal_irq_service_dummy_ack
273 };
274
275 static const struct irq_source_info
276 irq_source_info_dcn20[DAL_IRQ_SOURCES_NUMBER] = {
277 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
278 hpd_int_entry(0),
279 hpd_int_entry(1),
280 hpd_int_entry(2),
281 hpd_int_entry(3),
282 hpd_int_entry(4),
283 hpd_int_entry(5),
284 hpd_rx_int_entry(0),
285 hpd_rx_int_entry(1),
286 hpd_rx_int_entry(2),
287 hpd_rx_int_entry(3),
288 hpd_rx_int_entry(4),
289 hpd_rx_int_entry(5),
290 i2c_int_entry(1),
291 i2c_int_entry(2),
292 i2c_int_entry(3),
293 i2c_int_entry(4),
294 i2c_int_entry(5),
295 i2c_int_entry(6),
296 dp_sink_int_entry(1),
297 dp_sink_int_entry(2),
298 dp_sink_int_entry(3),
299 dp_sink_int_entry(4),
300 dp_sink_int_entry(5),
301 dp_sink_int_entry(6),
302 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
303 pflip_int_entry(0),
304 pflip_int_entry(1),
305 pflip_int_entry(2),
306 pflip_int_entry(3),
307 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
308 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
309 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
310 gpio_pad_int_entry(0),
311 gpio_pad_int_entry(1),
312 gpio_pad_int_entry(2),
313 gpio_pad_int_entry(3),
314 gpio_pad_int_entry(4),
315 gpio_pad_int_entry(5),
316 gpio_pad_int_entry(6),
317 gpio_pad_int_entry(7),
318 gpio_pad_int_entry(8),
319 gpio_pad_int_entry(9),
320 gpio_pad_int_entry(10),
321 gpio_pad_int_entry(11),
322 gpio_pad_int_entry(12),
323 gpio_pad_int_entry(13),
324 gpio_pad_int_entry(14),
325 gpio_pad_int_entry(15),
326 gpio_pad_int_entry(16),
327 gpio_pad_int_entry(17),
328 gpio_pad_int_entry(18),
329 gpio_pad_int_entry(19),
330 gpio_pad_int_entry(20),
331 gpio_pad_int_entry(21),
332 gpio_pad_int_entry(22),
333 gpio_pad_int_entry(23),
334 gpio_pad_int_entry(24),
335 gpio_pad_int_entry(25),
336 gpio_pad_int_entry(26),
337 gpio_pad_int_entry(27),
338 gpio_pad_int_entry(28),
339 gpio_pad_int_entry(29),
340 gpio_pad_int_entry(30),
341 dc_underflow_int_entry(1),
342 dc_underflow_int_entry(2),
343 dc_underflow_int_entry(3),
344 dc_underflow_int_entry(4),
345 dc_underflow_int_entry(5),
346 dc_underflow_int_entry(6),
347 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
348 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
349 vupdate_no_lock_int_entry(0),
350 vupdate_no_lock_int_entry(1),
351 vupdate_no_lock_int_entry(2),
352 vupdate_no_lock_int_entry(3),
353 vupdate_no_lock_int_entry(4),
354 vupdate_no_lock_int_entry(5),
355 vblank_int_entry(0),
356 vblank_int_entry(1),
357 vblank_int_entry(2),
358 vblank_int_entry(3),
359 vblank_int_entry(4),
360 vblank_int_entry(5),
361 };
362
363 static const struct irq_service_funcs irq_service_funcs_dcn20 = {
364 .to_dal_irq_source = to_dal_irq_source_dcn20
365 };
366
dcn20_irq_construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)367 static void dcn20_irq_construct(
368 struct irq_service *irq_service,
369 struct irq_service_init_data *init_data)
370 {
371 dal_irq_service_construct(irq_service, init_data);
372
373 irq_service->info = irq_source_info_dcn20;
374 irq_service->funcs = &irq_service_funcs_dcn20;
375 }
376
dal_irq_service_dcn20_create(struct irq_service_init_data * init_data)377 struct irq_service *dal_irq_service_dcn20_create(
378 struct irq_service_init_data *init_data)
379 {
380 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
381 GFP_KERNEL);
382
383 if (!irq_service)
384 return NULL;
385
386 dcn20_irq_construct(irq_service, init_data);
387 return irq_service;
388 }
389