1 /* $NetBSD: amdgpu_hw_factory_dce80.c,v 1.2 2021/12/18 23:45:05 riastradh Exp $ */
2
3 /*
4 * Copyright 2012-15 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_hw_factory_dce80.c,v 1.2 2021/12/18 23:45:05 riastradh Exp $");
30
31 #include "dm_services.h"
32 #include "include/gpio_types.h"
33 #include "../hw_factory.h"
34
35 #include "hw_factory_dce80.h"
36
37 #include "../hw_gpio.h"
38 #include "../hw_ddc.h"
39 #include "../hw_hpd.h"
40 #include "../hw_generic.h"
41
42 #include "dce/dce_8_0_d.h"
43 #include "dce/dce_8_0_sh_mask.h"
44
45
46 #define REG(reg_name)\
47 mm ## reg_name
48
49 #include "reg_helper.h"
50 #include "../hpd_regs.h"
51
52 #define HPD_REG_LIST_DCE8(id) \
53 HPD_GPIO_REG_LIST(id), \
54 .int_status = mmDC_HPD ## id ## _INT_STATUS,\
55 .toggle_filt_cntl = mmDC_HPD ## id ## _TOGGLE_FILT_CNTL
56
57 #define HPD_MASK_SH_LIST_DCE8(mask_sh) \
58 .DC_HPD_SENSE_DELAYED = DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED ## mask_sh,\
59 .DC_HPD_SENSE = DC_HPD1_INT_STATUS__DC_HPD1_SENSE ## mask_sh,\
60 .DC_HPD_CONNECT_INT_DELAY = DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY ## mask_sh,\
61 .DC_HPD_DISCONNECT_INT_DELAY = DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY ## mask_sh
62
63 #define hpd_regs(id) \
64 {\
65 HPD_REG_LIST_DCE8(id)\
66 }
67
68 static const struct hpd_registers hpd_regs[] = {
69 hpd_regs(1),
70 hpd_regs(2),
71 hpd_regs(3),
72 hpd_regs(4),
73 hpd_regs(5),
74 hpd_regs(6)
75 };
76
77 static const struct hpd_sh_mask hpd_shift = {
78 HPD_MASK_SH_LIST_DCE8(__SHIFT)
79 };
80
81 static const struct hpd_sh_mask hpd_mask = {
82 HPD_MASK_SH_LIST_DCE8(_MASK)
83 };
84
85 #include "../ddc_regs.h"
86
87 /* set field name */
88 #define SF_DDC(reg_name, field_name, post_fix)\
89 .field_name = reg_name ## __ ## field_name ## post_fix
90
91 static const struct ddc_registers ddc_data_regs[] = {
92 ddc_data_regs(1),
93 ddc_data_regs(2),
94 ddc_data_regs(3),
95 ddc_data_regs(4),
96 ddc_data_regs(5),
97 ddc_data_regs(6),
98 ddc_vga_data_regs,
99 ddc_i2c_data_regs
100 };
101
102 static const struct ddc_registers ddc_clk_regs[] = {
103 ddc_clk_regs(1),
104 ddc_clk_regs(2),
105 ddc_clk_regs(3),
106 ddc_clk_regs(4),
107 ddc_clk_regs(5),
108 ddc_clk_regs(6),
109 ddc_vga_clk_regs,
110 ddc_i2c_clk_regs
111 };
112
113 static const struct ddc_sh_mask ddc_shift = {
114 DDC_MASK_SH_LIST(__SHIFT)
115 };
116
117 static const struct ddc_sh_mask ddc_mask = {
118 DDC_MASK_SH_LIST(_MASK)
119 };
120
define_ddc_registers(struct hw_gpio_pin * pin,uint32_t en)121 static void define_ddc_registers(
122 struct hw_gpio_pin *pin,
123 uint32_t en)
124 {
125 struct hw_ddc *ddc = HW_DDC_FROM_BASE(pin);
126
127 switch (pin->id) {
128 case GPIO_ID_DDC_DATA:
129 ddc->regs = &ddc_data_regs[en];
130 ddc->base.regs = &ddc_data_regs[en].gpio;
131 break;
132 case GPIO_ID_DDC_CLOCK:
133 ddc->regs = &ddc_clk_regs[en];
134 ddc->base.regs = &ddc_clk_regs[en].gpio;
135 break;
136 default:
137 ASSERT_CRITICAL(false);
138 return;
139 }
140
141 ddc->shifts = &ddc_shift;
142 ddc->masks = &ddc_mask;
143
144 }
145
define_hpd_registers(struct hw_gpio_pin * pin,uint32_t en)146 static void define_hpd_registers(struct hw_gpio_pin *pin, uint32_t en)
147 {
148 struct hw_hpd *hpd = HW_HPD_FROM_BASE(pin);
149
150 hpd->regs = &hpd_regs[en];
151 hpd->shifts = &hpd_shift;
152 hpd->masks = &hpd_mask;
153 hpd->base.regs = &hpd_regs[en].gpio;
154 }
155
156 static const struct hw_factory_funcs funcs = {
157 .init_ddc_data = dal_hw_ddc_init,
158 .init_generic = NULL,
159 .init_hpd = dal_hw_hpd_init,
160 .get_ddc_pin = dal_hw_ddc_get_pin,
161 .get_hpd_pin = dal_hw_hpd_get_pin,
162 .get_generic_pin = NULL,
163 .define_hpd_registers = define_hpd_registers,
164 .define_ddc_registers = define_ddc_registers
165 };
166
dal_hw_factory_dce80_init(struct hw_factory * factory)167 void dal_hw_factory_dce80_init(
168 struct hw_factory *factory)
169 {
170 factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
171 factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
172 factory->number_of_pins[GPIO_ID_GENERIC] = 7;
173 factory->number_of_pins[GPIO_ID_HPD] = 6;
174 factory->number_of_pins[GPIO_ID_GPIO_PAD] = 31;
175 factory->number_of_pins[GPIO_ID_VIP_PAD] = 0;
176 factory->number_of_pins[GPIO_ID_SYNC] = 2;
177 factory->number_of_pins[GPIO_ID_GSL] = 4;
178
179 factory->funcs = &funcs;
180 }
181