1 /* $NetBSD: amdgpu_command_table_helper2.c,v 1.2 2021/12/18 23:45:00 riastradh Exp $ */
2
3 /*
4 * Copyright 2012-15 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_command_table_helper2.c,v 1.2 2021/12/18 23:45:00 riastradh Exp $");
30
31 #include "dm_services.h"
32
33 #include "ObjectID.h"
34 #include "atomfirmware.h"
35
36 #include "include/bios_parser_types.h"
37
38 #include "command_table_helper2.h"
39
dal_bios_parser_init_cmd_tbl_helper2(const struct command_table_helper ** h,enum dce_version dce)40 bool dal_bios_parser_init_cmd_tbl_helper2(
41 const struct command_table_helper **h,
42 enum dce_version dce)
43 {
44 switch (dce) {
45 case DCE_VERSION_8_0:
46 case DCE_VERSION_8_1:
47 case DCE_VERSION_8_3:
48 *h = dal_cmd_tbl_helper_dce80_get_table();
49 return true;
50
51 case DCE_VERSION_10_0:
52 *h = dal_cmd_tbl_helper_dce110_get_table();
53 return true;
54
55 case DCE_VERSION_11_0:
56 *h = dal_cmd_tbl_helper_dce110_get_table();
57 return true;
58
59 case DCE_VERSION_11_2:
60 case DCE_VERSION_11_22:
61 *h = dal_cmd_tbl_helper_dce112_get_table2();
62 return true;
63 #if defined(CONFIG_DRM_AMD_DC_DCN)
64 case DCN_VERSION_1_0:
65 case DCN_VERSION_1_01:
66 *h = dal_cmd_tbl_helper_dce112_get_table2();
67 return true;
68 #endif
69
70 case DCN_VERSION_2_0:
71 *h = dal_cmd_tbl_helper_dce112_get_table2();
72 return true;
73 case DCN_VERSION_2_1:
74 *h = dal_cmd_tbl_helper_dce112_get_table2();
75 return true;
76 case DCE_VERSION_12_0:
77 case DCE_VERSION_12_1:
78 *h = dal_cmd_tbl_helper_dce112_get_table2();
79 return true;
80
81 default:
82 /* Unsupported DCE */
83 BREAK_TO_DEBUGGER();
84 return false;
85 }
86 }
87
88 /* real implementations */
89
dal_cmd_table_helper_controller_id_to_atom2(enum controller_id id,uint8_t * atom_id)90 bool dal_cmd_table_helper_controller_id_to_atom2(
91 enum controller_id id,
92 uint8_t *atom_id)
93 {
94 if (atom_id == NULL) {
95 BREAK_TO_DEBUGGER();
96 return false;
97 }
98
99 switch (id) {
100 case CONTROLLER_ID_D0:
101 *atom_id = ATOM_CRTC1;
102 return true;
103 case CONTROLLER_ID_D1:
104 *atom_id = ATOM_CRTC2;
105 return true;
106 case CONTROLLER_ID_D2:
107 *atom_id = ATOM_CRTC3;
108 return true;
109 case CONTROLLER_ID_D3:
110 *atom_id = ATOM_CRTC4;
111 return true;
112 case CONTROLLER_ID_D4:
113 *atom_id = ATOM_CRTC5;
114 return true;
115 case CONTROLLER_ID_D5:
116 *atom_id = ATOM_CRTC6;
117 return true;
118 /* TODO :case CONTROLLER_ID_UNDERLAY0:
119 *atom_id = ATOM_UNDERLAY_PIPE0;
120 return true;
121 */
122 case CONTROLLER_ID_UNDEFINED:
123 *atom_id = ATOM_CRTC_INVALID;
124 return true;
125 default:
126 /* Wrong controller id */
127 BREAK_TO_DEBUGGER();
128 return false;
129 }
130 }
131
132 /**
133 * translate_transmitter_bp_to_atom
134 *
135 * @brief
136 * Translate the Transmitter to the corresponding ATOM BIOS value
137 *
138 * @param
139 * input transmitter
140 * output digitalTransmitter
141 * // =00: Digital Transmitter1 ( UNIPHY linkAB )
142 * // =01: Digital Transmitter2 ( UNIPHY linkCD )
143 * // =02: Digital Transmitter3 ( UNIPHY linkEF )
144 */
dal_cmd_table_helper_transmitter_bp_to_atom2(enum transmitter t)145 uint8_t dal_cmd_table_helper_transmitter_bp_to_atom2(
146 enum transmitter t)
147 {
148 switch (t) {
149 case TRANSMITTER_UNIPHY_A:
150 case TRANSMITTER_UNIPHY_B:
151 case TRANSMITTER_TRAVIS_LCD:
152 return 0;
153 case TRANSMITTER_UNIPHY_C:
154 case TRANSMITTER_UNIPHY_D:
155 return 1;
156 case TRANSMITTER_UNIPHY_E:
157 case TRANSMITTER_UNIPHY_F:
158 return 2;
159 default:
160 /* Invalid Transmitter Type! */
161 BREAK_TO_DEBUGGER();
162 return 0;
163 }
164 }
165
dal_cmd_table_helper_encoder_mode_bp_to_atom2(enum signal_type s,bool enable_dp_audio)166 uint32_t dal_cmd_table_helper_encoder_mode_bp_to_atom2(
167 enum signal_type s,
168 bool enable_dp_audio)
169 {
170 switch (s) {
171 case SIGNAL_TYPE_DVI_SINGLE_LINK:
172 case SIGNAL_TYPE_DVI_DUAL_LINK:
173 return ATOM_ENCODER_MODE_DVI;
174 case SIGNAL_TYPE_HDMI_TYPE_A:
175 return ATOM_ENCODER_MODE_HDMI;
176 case SIGNAL_TYPE_LVDS:
177 return ATOM_ENCODER_MODE_LVDS;
178 case SIGNAL_TYPE_EDP:
179 case SIGNAL_TYPE_DISPLAY_PORT_MST:
180 case SIGNAL_TYPE_DISPLAY_PORT:
181 case SIGNAL_TYPE_VIRTUAL:
182 if (enable_dp_audio)
183 return ATOM_ENCODER_MODE_DP_AUDIO;
184 else
185 return ATOM_ENCODER_MODE_DP;
186 case SIGNAL_TYPE_RGB:
187 return ATOM_ENCODER_MODE_CRT;
188 default:
189 return ATOM_ENCODER_MODE_CRT;
190 }
191 }
192
dal_cmd_table_helper_clock_source_id_to_ref_clk_src2(enum clock_source_id id,uint32_t * ref_clk_src_id)193 bool dal_cmd_table_helper_clock_source_id_to_ref_clk_src2(
194 enum clock_source_id id,
195 uint32_t *ref_clk_src_id)
196 {
197 if (ref_clk_src_id == NULL) {
198 BREAK_TO_DEBUGGER();
199 return false;
200 }
201
202 switch (id) {
203 case CLOCK_SOURCE_ID_PLL1:
204 *ref_clk_src_id = ENCODER_REFCLK_SRC_P1PLL;
205 return true;
206 case CLOCK_SOURCE_ID_PLL2:
207 *ref_clk_src_id = ENCODER_REFCLK_SRC_P2PLL;
208 return true;
209 /*TODO:case CLOCK_SOURCE_ID_DCPLL:
210 *ref_clk_src_id = ENCODER_REFCLK_SRC_DCPLL;
211 return true;
212 */
213 case CLOCK_SOURCE_ID_EXTERNAL:
214 *ref_clk_src_id = ENCODER_REFCLK_SRC_EXTCLK;
215 return true;
216 case CLOCK_SOURCE_ID_UNDEFINED:
217 *ref_clk_src_id = ENCODER_REFCLK_SRC_INVALID;
218 return true;
219 default:
220 /* Unsupported clock source id */
221 BREAK_TO_DEBUGGER();
222 return false;
223 }
224 }
225
dal_cmd_table_helper_encoder_id_to_atom2(enum encoder_id id)226 uint8_t dal_cmd_table_helper_encoder_id_to_atom2(
227 enum encoder_id id)
228 {
229 switch (id) {
230 case ENCODER_ID_INTERNAL_LVDS:
231 return ENCODER_OBJECT_ID_INTERNAL_LVDS;
232 case ENCODER_ID_INTERNAL_TMDS1:
233 return ENCODER_OBJECT_ID_INTERNAL_TMDS1;
234 case ENCODER_ID_INTERNAL_TMDS2:
235 return ENCODER_OBJECT_ID_INTERNAL_TMDS2;
236 case ENCODER_ID_INTERNAL_DAC1:
237 return ENCODER_OBJECT_ID_INTERNAL_DAC1;
238 case ENCODER_ID_INTERNAL_DAC2:
239 return ENCODER_OBJECT_ID_INTERNAL_DAC2;
240 case ENCODER_ID_INTERNAL_LVTM1:
241 return ENCODER_OBJECT_ID_INTERNAL_LVTM1;
242 case ENCODER_ID_INTERNAL_HDMI:
243 return ENCODER_OBJECT_ID_HDMI_INTERNAL;
244 case ENCODER_ID_EXTERNAL_TRAVIS:
245 return ENCODER_OBJECT_ID_TRAVIS;
246 case ENCODER_ID_EXTERNAL_NUTMEG:
247 return ENCODER_OBJECT_ID_NUTMEG;
248 case ENCODER_ID_INTERNAL_KLDSCP_TMDS1:
249 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
250 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
251 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
252 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
253 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
254 case ENCODER_ID_EXTERNAL_MVPU_FPGA:
255 return ENCODER_OBJECT_ID_MVPU_FPGA;
256 case ENCODER_ID_INTERNAL_DDI:
257 return ENCODER_OBJECT_ID_INTERNAL_DDI;
258 case ENCODER_ID_INTERNAL_UNIPHY:
259 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY;
260 case ENCODER_ID_INTERNAL_KLDSCP_LVTMA:
261 return ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA;
262 case ENCODER_ID_INTERNAL_UNIPHY1:
263 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY1;
264 case ENCODER_ID_INTERNAL_UNIPHY2:
265 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY2;
266 case ENCODER_ID_INTERNAL_UNIPHY3:
267 return ENCODER_OBJECT_ID_INTERNAL_UNIPHY3;
268 case ENCODER_ID_INTERNAL_WIRELESS:
269 return ENCODER_OBJECT_ID_INTERNAL_VCE;
270 case ENCODER_ID_INTERNAL_VIRTUAL:
271 return ENCODER_OBJECT_ID_NONE;
272 case ENCODER_ID_UNKNOWN:
273 return ENCODER_OBJECT_ID_NONE;
274 default:
275 /* Invalid encoder id */
276 BREAK_TO_DEBUGGER();
277 return ENCODER_OBJECT_ID_NONE;
278 }
279 }
280