1 //===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCVMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MCTargetDesc/RISCVBaseInfo.h"
14 #include "MCTargetDesc/RISCVFixupKinds.h"
15 #include "MCTargetDesc/RISCVMCExpr.h"
16 #include "MCTargetDesc/RISCVMCTargetDesc.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCInstBuilder.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/Support/Casting.h"
28 #include "llvm/Support/EndianStream.h"
29 #include "llvm/Support/raw_ostream.h"
30
31 using namespace llvm;
32
33 #define DEBUG_TYPE "mccodeemitter"
34
35 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
36 STATISTIC(MCNumFixups, "Number of MC fixups created");
37
38 namespace {
39 class RISCVMCCodeEmitter : public MCCodeEmitter {
40 RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete;
41 void operator=(const RISCVMCCodeEmitter &) = delete;
42 MCContext &Ctx;
43 MCInstrInfo const &MCII;
44
45 public:
RISCVMCCodeEmitter(MCContext & ctx,MCInstrInfo const & MCII)46 RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
47 : Ctx(ctx), MCII(MCII) {}
48
~RISCVMCCodeEmitter()49 ~RISCVMCCodeEmitter() override {}
50
51 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
52 SmallVectorImpl<MCFixup> &Fixups,
53 const MCSubtargetInfo &STI) const override;
54
55 void expandFunctionCall(const MCInst &MI, raw_ostream &OS,
56 SmallVectorImpl<MCFixup> &Fixups,
57 const MCSubtargetInfo &STI) const;
58
59 void expandAddTPRel(const MCInst &MI, raw_ostream &OS,
60 SmallVectorImpl<MCFixup> &Fixups,
61 const MCSubtargetInfo &STI) const;
62
63 /// TableGen'erated function for getting the binary encoding for an
64 /// instruction.
65 uint64_t getBinaryCodeForInstr(const MCInst &MI,
66 SmallVectorImpl<MCFixup> &Fixups,
67 const MCSubtargetInfo &STI) const;
68
69 /// Return binary encoding of operand. If the machine operand requires
70 /// relocation, record the relocation and return zero.
71 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
72 SmallVectorImpl<MCFixup> &Fixups,
73 const MCSubtargetInfo &STI) const;
74
75 unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
76 SmallVectorImpl<MCFixup> &Fixups,
77 const MCSubtargetInfo &STI) const;
78
79 unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
80 SmallVectorImpl<MCFixup> &Fixups,
81 const MCSubtargetInfo &STI) const;
82
83 unsigned getVMaskReg(const MCInst &MI, unsigned OpNo,
84 SmallVectorImpl<MCFixup> &Fixups,
85 const MCSubtargetInfo &STI) const;
86
87 private:
88 FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const;
89 void
90 verifyInstructionPredicates(const MCInst &MI,
91 const FeatureBitset &AvailableFeatures) const;
92 };
93 } // end anonymous namespace
94
createRISCVMCCodeEmitter(const MCInstrInfo & MCII,const MCRegisterInfo & MRI,MCContext & Ctx)95 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
96 const MCRegisterInfo &MRI,
97 MCContext &Ctx) {
98 return new RISCVMCCodeEmitter(Ctx, MCII);
99 }
100
101 // Expand PseudoCALL(Reg), PseudoTAIL and PseudoJump to AUIPC and JALR with
102 // relocation types. We expand those pseudo-instructions while encoding them,
103 // meaning AUIPC and JALR won't go through RISCV MC to MC compressed
104 // instruction transformation. This is acceptable because AUIPC has no 16-bit
105 // form and C_JALR has no immediate operand field. We let linker relaxation
106 // deal with it. When linker relaxation is enabled, AUIPC and JALR have a
107 // chance to relax to JAL.
108 // If the C extension is enabled, JAL has a chance relax to C_JAL.
expandFunctionCall(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const109 void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
110 SmallVectorImpl<MCFixup> &Fixups,
111 const MCSubtargetInfo &STI) const {
112 MCInst TmpInst;
113 MCOperand Func;
114 MCRegister Ra;
115 if (MI.getOpcode() == RISCV::PseudoTAIL) {
116 Func = MI.getOperand(0);
117 Ra = RISCV::X6;
118 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) {
119 Func = MI.getOperand(1);
120 Ra = MI.getOperand(0).getReg();
121 } else if (MI.getOpcode() == RISCV::PseudoCALL) {
122 Func = MI.getOperand(0);
123 Ra = RISCV::X1;
124 } else if (MI.getOpcode() == RISCV::PseudoJump) {
125 Func = MI.getOperand(1);
126 Ra = MI.getOperand(0).getReg();
127 }
128 uint32_t Binary;
129
130 assert(Func.isExpr() && "Expected expression");
131
132 const MCExpr *CallExpr = Func.getExpr();
133
134 // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
135 TmpInst = MCInstBuilder(RISCV::AUIPC)
136 .addReg(Ra)
137 .addOperand(MCOperand::createExpr(CallExpr));
138 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
139 support::endian::write(OS, Binary, support::little);
140
141 if (MI.getOpcode() == RISCV::PseudoTAIL ||
142 MI.getOpcode() == RISCV::PseudoJump)
143 // Emit JALR X0, Ra, 0
144 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
145 else
146 // Emit JALR Ra, Ra, 0
147 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
148 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
149 support::endian::write(OS, Binary, support::little);
150 }
151
152 // Expand PseudoAddTPRel to a simple ADD with the correct relocation.
expandAddTPRel(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const153 void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS,
154 SmallVectorImpl<MCFixup> &Fixups,
155 const MCSubtargetInfo &STI) const {
156 MCOperand DestReg = MI.getOperand(0);
157 MCOperand SrcReg = MI.getOperand(1);
158 MCOperand TPReg = MI.getOperand(2);
159 assert(TPReg.isReg() && TPReg.getReg() == RISCV::X4 &&
160 "Expected thread pointer as second input to TP-relative add");
161
162 MCOperand SrcSymbol = MI.getOperand(3);
163 assert(SrcSymbol.isExpr() &&
164 "Expected expression as third input to TP-relative add");
165
166 const RISCVMCExpr *Expr = dyn_cast<RISCVMCExpr>(SrcSymbol.getExpr());
167 assert(Expr && Expr->getKind() == RISCVMCExpr::VK_RISCV_TPREL_ADD &&
168 "Expected tprel_add relocation on TP-relative symbol");
169
170 // Emit the correct tprel_add relocation for the symbol.
171 Fixups.push_back(MCFixup::create(
172 0, Expr, MCFixupKind(RISCV::fixup_riscv_tprel_add), MI.getLoc()));
173
174 // Emit fixup_riscv_relax for tprel_add where the relax feature is enabled.
175 if (STI.getFeatureBits()[RISCV::FeatureRelax]) {
176 const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
177 Fixups.push_back(MCFixup::create(
178 0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax), MI.getLoc()));
179 }
180
181 // Emit a normal ADD instruction with the given operands.
182 MCInst TmpInst = MCInstBuilder(RISCV::ADD)
183 .addOperand(DestReg)
184 .addOperand(SrcReg)
185 .addOperand(TPReg);
186 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
187 support::endian::write(OS, Binary, support::little);
188 }
189
encodeInstruction(const MCInst & MI,raw_ostream & OS,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const190 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
191 SmallVectorImpl<MCFixup> &Fixups,
192 const MCSubtargetInfo &STI) const {
193 verifyInstructionPredicates(MI,
194 computeAvailableFeatures(STI.getFeatureBits()));
195
196 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
197 // Get byte count of instruction.
198 unsigned Size = Desc.getSize();
199
200 // RISCVInstrInfo::getInstSizeInBytes hard-codes the number of expanded
201 // instructions for each pseudo, and must be updated when adding new pseudos
202 // or changing existing ones.
203 if (MI.getOpcode() == RISCV::PseudoCALLReg ||
204 MI.getOpcode() == RISCV::PseudoCALL ||
205 MI.getOpcode() == RISCV::PseudoTAIL ||
206 MI.getOpcode() == RISCV::PseudoJump) {
207 expandFunctionCall(MI, OS, Fixups, STI);
208 MCNumEmitted += 2;
209 return;
210 }
211
212 if (MI.getOpcode() == RISCV::PseudoAddTPRel) {
213 expandAddTPRel(MI, OS, Fixups, STI);
214 MCNumEmitted += 1;
215 return;
216 }
217
218 switch (Size) {
219 default:
220 llvm_unreachable("Unhandled encodeInstruction length!");
221 case 2: {
222 uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
223 support::endian::write<uint16_t>(OS, Bits, support::little);
224 break;
225 }
226 case 4: {
227 uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
228 support::endian::write(OS, Bits, support::little);
229 break;
230 }
231 }
232
233 ++MCNumEmitted; // Keep track of the # of mi's emitted.
234 }
235
236 unsigned
getMachineOpValue(const MCInst & MI,const MCOperand & MO,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const237 RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
238 SmallVectorImpl<MCFixup> &Fixups,
239 const MCSubtargetInfo &STI) const {
240
241 if (MO.isReg())
242 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
243
244 if (MO.isImm())
245 return static_cast<unsigned>(MO.getImm());
246
247 llvm_unreachable("Unhandled expression!");
248 return 0;
249 }
250
251 unsigned
getImmOpValueAsr1(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const252 RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
253 SmallVectorImpl<MCFixup> &Fixups,
254 const MCSubtargetInfo &STI) const {
255 const MCOperand &MO = MI.getOperand(OpNo);
256
257 if (MO.isImm()) {
258 unsigned Res = MO.getImm();
259 assert((Res & 1) == 0 && "LSB is non-zero");
260 return Res >> 1;
261 }
262
263 return getImmOpValue(MI, OpNo, Fixups, STI);
264 }
265
getImmOpValue(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const266 unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
267 SmallVectorImpl<MCFixup> &Fixups,
268 const MCSubtargetInfo &STI) const {
269 bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax];
270 const MCOperand &MO = MI.getOperand(OpNo);
271
272 MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
273 unsigned MIFrm = RISCVII::getFormat(Desc.TSFlags);
274
275 // If the destination is an immediate, there is nothing to do.
276 if (MO.isImm())
277 return MO.getImm();
278
279 assert(MO.isExpr() &&
280 "getImmOpValue expects only expressions or immediates");
281 const MCExpr *Expr = MO.getExpr();
282 MCExpr::ExprKind Kind = Expr->getKind();
283 RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid;
284 bool RelaxCandidate = false;
285 if (Kind == MCExpr::Target) {
286 const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
287
288 switch (RVExpr->getKind()) {
289 case RISCVMCExpr::VK_RISCV_None:
290 case RISCVMCExpr::VK_RISCV_Invalid:
291 case RISCVMCExpr::VK_RISCV_32_PCREL:
292 llvm_unreachable("Unhandled fixup kind!");
293 case RISCVMCExpr::VK_RISCV_TPREL_ADD:
294 // tprel_add is only used to indicate that a relocation should be emitted
295 // for an add instruction used in TP-relative addressing. It should not be
296 // expanded as if representing an actual instruction operand and so to
297 // encounter it here is an error.
298 llvm_unreachable(
299 "VK_RISCV_TPREL_ADD should not represent an instruction operand");
300 case RISCVMCExpr::VK_RISCV_LO:
301 if (MIFrm == RISCVII::InstFormatI)
302 FixupKind = RISCV::fixup_riscv_lo12_i;
303 else if (MIFrm == RISCVII::InstFormatS)
304 FixupKind = RISCV::fixup_riscv_lo12_s;
305 else
306 llvm_unreachable("VK_RISCV_LO used with unexpected instruction format");
307 RelaxCandidate = true;
308 break;
309 case RISCVMCExpr::VK_RISCV_HI:
310 FixupKind = RISCV::fixup_riscv_hi20;
311 RelaxCandidate = true;
312 break;
313 case RISCVMCExpr::VK_RISCV_PCREL_LO:
314 if (MIFrm == RISCVII::InstFormatI)
315 FixupKind = RISCV::fixup_riscv_pcrel_lo12_i;
316 else if (MIFrm == RISCVII::InstFormatS)
317 FixupKind = RISCV::fixup_riscv_pcrel_lo12_s;
318 else
319 llvm_unreachable(
320 "VK_RISCV_PCREL_LO used with unexpected instruction format");
321 RelaxCandidate = true;
322 break;
323 case RISCVMCExpr::VK_RISCV_PCREL_HI:
324 FixupKind = RISCV::fixup_riscv_pcrel_hi20;
325 RelaxCandidate = true;
326 break;
327 case RISCVMCExpr::VK_RISCV_GOT_HI:
328 FixupKind = RISCV::fixup_riscv_got_hi20;
329 break;
330 case RISCVMCExpr::VK_RISCV_TPREL_LO:
331 if (MIFrm == RISCVII::InstFormatI)
332 FixupKind = RISCV::fixup_riscv_tprel_lo12_i;
333 else if (MIFrm == RISCVII::InstFormatS)
334 FixupKind = RISCV::fixup_riscv_tprel_lo12_s;
335 else
336 llvm_unreachable(
337 "VK_RISCV_TPREL_LO used with unexpected instruction format");
338 RelaxCandidate = true;
339 break;
340 case RISCVMCExpr::VK_RISCV_TPREL_HI:
341 FixupKind = RISCV::fixup_riscv_tprel_hi20;
342 RelaxCandidate = true;
343 break;
344 case RISCVMCExpr::VK_RISCV_TLS_GOT_HI:
345 FixupKind = RISCV::fixup_riscv_tls_got_hi20;
346 break;
347 case RISCVMCExpr::VK_RISCV_TLS_GD_HI:
348 FixupKind = RISCV::fixup_riscv_tls_gd_hi20;
349 break;
350 case RISCVMCExpr::VK_RISCV_CALL:
351 FixupKind = RISCV::fixup_riscv_call;
352 RelaxCandidate = true;
353 break;
354 case RISCVMCExpr::VK_RISCV_CALL_PLT:
355 FixupKind = RISCV::fixup_riscv_call_plt;
356 RelaxCandidate = true;
357 break;
358 }
359 } else if (Kind == MCExpr::SymbolRef &&
360 cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) {
361 if (Desc.getOpcode() == RISCV::JAL) {
362 FixupKind = RISCV::fixup_riscv_jal;
363 } else if (MIFrm == RISCVII::InstFormatB) {
364 FixupKind = RISCV::fixup_riscv_branch;
365 } else if (MIFrm == RISCVII::InstFormatCJ) {
366 FixupKind = RISCV::fixup_riscv_rvc_jump;
367 } else if (MIFrm == RISCVII::InstFormatCB) {
368 FixupKind = RISCV::fixup_riscv_rvc_branch;
369 }
370 }
371
372 assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
373
374 Fixups.push_back(
375 MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
376 ++MCNumFixups;
377
378 // Ensure an R_RISCV_RELAX relocation will be emitted if linker relaxation is
379 // enabled and the current fixup will result in a relocation that may be
380 // relaxed.
381 if (EnableRelax && RelaxCandidate) {
382 const MCConstantExpr *Dummy = MCConstantExpr::create(0, Ctx);
383 Fixups.push_back(
384 MCFixup::create(0, Dummy, MCFixupKind(RISCV::fixup_riscv_relax),
385 MI.getLoc()));
386 ++MCNumFixups;
387 }
388
389 return 0;
390 }
391
getVMaskReg(const MCInst & MI,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI) const392 unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo,
393 SmallVectorImpl<MCFixup> &Fixups,
394 const MCSubtargetInfo &STI) const {
395 MCOperand MO = MI.getOperand(OpNo);
396 assert(MO.isReg() && "Expected a register.");
397
398 switch (MO.getReg()) {
399 default:
400 llvm_unreachable("Invalid mask register.");
401 case RISCV::V0:
402 return 0;
403 case RISCV::NoRegister:
404 return 1;
405 }
406 }
407
408 #define ENABLE_INSTR_PREDICATE_VERIFIER
409 #include "RISCVGenMCCodeEmitter.inc"
410