1 //===-- AVRExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a pass that expands pseudo instructions into target
10 // instructions. This pass should be run after register allocation but before
11 // the post-regalloc scheduling pass.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "AVR.h"
16 #include "AVRInstrInfo.h"
17 #include "AVRTargetMachine.h"
18 #include "MCTargetDesc/AVRMCTargetDesc.h"
19
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/CodeGen/TargetRegisterInfo.h"
25
26 using namespace llvm;
27
28 #define AVR_EXPAND_PSEUDO_NAME "AVR pseudo instruction expansion pass"
29
30 namespace {
31
32 /// Expands "placeholder" instructions marked as pseudo into
33 /// actual AVR instructions.
34 class AVRExpandPseudo : public MachineFunctionPass {
35 public:
36 static char ID;
37
AVRExpandPseudo()38 AVRExpandPseudo() : MachineFunctionPass(ID) {
39 initializeAVRExpandPseudoPass(*PassRegistry::getPassRegistry());
40 }
41
42 bool runOnMachineFunction(MachineFunction &MF) override;
43
getPassName() const44 StringRef getPassName() const override { return AVR_EXPAND_PSEUDO_NAME; }
45
46 private:
47 typedef MachineBasicBlock Block;
48 typedef Block::iterator BlockIt;
49
50 const AVRRegisterInfo *TRI;
51 const TargetInstrInfo *TII;
52
53 /// The register to be used for temporary storage.
54 const Register SCRATCH_REGISTER = AVR::R0;
55 /// The register that will always contain zero.
56 const Register ZERO_REGISTER = AVR::R1;
57 /// The IO address of the status register.
58 const unsigned SREG_ADDR = 0x3f;
59
60 bool expandMBB(Block &MBB);
61 bool expandMI(Block &MBB, BlockIt MBBI);
62 template <unsigned OP> bool expand(Block &MBB, BlockIt MBBI);
63
buildMI(Block & MBB,BlockIt MBBI,unsigned Opcode)64 MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode) {
65 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode));
66 }
67
buildMI(Block & MBB,BlockIt MBBI,unsigned Opcode,Register DstReg)68 MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode,
69 Register DstReg) {
70 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg);
71 }
72
getRegInfo(Block & MBB)73 MachineRegisterInfo &getRegInfo(Block &MBB) { return MBB.getParent()->getRegInfo(); }
74
75 bool expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI);
76 bool expandLogic(unsigned Op, Block &MBB, BlockIt MBBI);
77 bool expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI);
78 bool isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const;
79
80 template<typename Func>
81 bool expandAtomic(Block &MBB, BlockIt MBBI, Func f);
82
83 template<typename Func>
84 bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI, Func f);
85
86 bool expandAtomicBinaryOp(unsigned Opcode, Block &MBB, BlockIt MBBI);
87
88 bool expandAtomicArithmeticOp(unsigned MemOpcode,
89 unsigned ArithOpcode,
90 Block &MBB,
91 BlockIt MBBI);
92
93 /// Scavenges a free GPR8 register for use.
94 Register scavengeGPR8(MachineInstr &MI);
95 };
96
97 char AVRExpandPseudo::ID = 0;
98
expandMBB(MachineBasicBlock & MBB)99 bool AVRExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
100 bool Modified = false;
101
102 BlockIt MBBI = MBB.begin(), E = MBB.end();
103 while (MBBI != E) {
104 BlockIt NMBBI = std::next(MBBI);
105 Modified |= expandMI(MBB, MBBI);
106 MBBI = NMBBI;
107 }
108
109 return Modified;
110 }
111
runOnMachineFunction(MachineFunction & MF)112 bool AVRExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
113 bool Modified = false;
114
115 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
116 TRI = STI.getRegisterInfo();
117 TII = STI.getInstrInfo();
118
119 // We need to track liveness in order to use register scavenging.
120 MF.getProperties().set(MachineFunctionProperties::Property::TracksLiveness);
121
122 for (Block &MBB : MF) {
123 bool ContinueExpanding = true;
124 unsigned ExpandCount = 0;
125
126 // Continue expanding the block until all pseudos are expanded.
127 do {
128 assert(ExpandCount < 10 && "pseudo expand limit reached");
129
130 bool BlockModified = expandMBB(MBB);
131 Modified |= BlockModified;
132 ExpandCount++;
133
134 ContinueExpanding = BlockModified;
135 } while (ContinueExpanding);
136 }
137
138 return Modified;
139 }
140
141 bool AVRExpandPseudo::
expandArith(unsigned OpLo,unsigned OpHi,Block & MBB,BlockIt MBBI)142 expandArith(unsigned OpLo, unsigned OpHi, Block &MBB, BlockIt MBBI) {
143 MachineInstr &MI = *MBBI;
144 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
145 Register DstReg = MI.getOperand(0).getReg();
146 Register SrcReg = MI.getOperand(2).getReg();
147 bool DstIsDead = MI.getOperand(0).isDead();
148 bool DstIsKill = MI.getOperand(1).isKill();
149 bool SrcIsKill = MI.getOperand(2).isKill();
150 bool ImpIsDead = MI.getOperand(3).isDead();
151 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
152 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
153
154 buildMI(MBB, MBBI, OpLo)
155 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
156 .addReg(DstLoReg, getKillRegState(DstIsKill))
157 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
158
159 auto MIBHI = buildMI(MBB, MBBI, OpHi)
160 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
161 .addReg(DstHiReg, getKillRegState(DstIsKill))
162 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
163
164 if (ImpIsDead)
165 MIBHI->getOperand(3).setIsDead();
166
167 // SREG is always implicitly killed
168 MIBHI->getOperand(4).setIsKill();
169
170 MI.eraseFromParent();
171 return true;
172 }
173
174 bool AVRExpandPseudo::
expandLogic(unsigned Op,Block & MBB,BlockIt MBBI)175 expandLogic(unsigned Op, Block &MBB, BlockIt MBBI) {
176 MachineInstr &MI = *MBBI;
177 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
178 Register DstReg = MI.getOperand(0).getReg();
179 Register SrcReg = MI.getOperand(2).getReg();
180 bool DstIsDead = MI.getOperand(0).isDead();
181 bool DstIsKill = MI.getOperand(1).isKill();
182 bool SrcIsKill = MI.getOperand(2).isKill();
183 bool ImpIsDead = MI.getOperand(3).isDead();
184 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
185 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
186
187 auto MIBLO = buildMI(MBB, MBBI, Op)
188 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
189 .addReg(DstLoReg, getKillRegState(DstIsKill))
190 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
191
192 // SREG is always implicitly dead
193 MIBLO->getOperand(3).setIsDead();
194
195 auto MIBHI = buildMI(MBB, MBBI, Op)
196 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
197 .addReg(DstHiReg, getKillRegState(DstIsKill))
198 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
199
200 if (ImpIsDead)
201 MIBHI->getOperand(3).setIsDead();
202
203 MI.eraseFromParent();
204 return true;
205 }
206
207 bool AVRExpandPseudo::
isLogicImmOpRedundant(unsigned Op,unsigned ImmVal) const208 isLogicImmOpRedundant(unsigned Op, unsigned ImmVal) const {
209
210 // ANDI Rd, 0xff is redundant.
211 if (Op == AVR::ANDIRdK && ImmVal == 0xff)
212 return true;
213
214 // ORI Rd, 0x0 is redundant.
215 if (Op == AVR::ORIRdK && ImmVal == 0x0)
216 return true;
217
218 return false;
219 }
220
221 bool AVRExpandPseudo::
expandLogicImm(unsigned Op,Block & MBB,BlockIt MBBI)222 expandLogicImm(unsigned Op, Block &MBB, BlockIt MBBI) {
223 MachineInstr &MI = *MBBI;
224 Register DstLoReg, DstHiReg;
225 Register DstReg = MI.getOperand(0).getReg();
226 bool DstIsDead = MI.getOperand(0).isDead();
227 bool SrcIsKill = MI.getOperand(1).isKill();
228 bool ImpIsDead = MI.getOperand(3).isDead();
229 unsigned Imm = MI.getOperand(2).getImm();
230 unsigned Lo8 = Imm & 0xff;
231 unsigned Hi8 = (Imm >> 8) & 0xff;
232 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
233
234 if (!isLogicImmOpRedundant(Op, Lo8)) {
235 auto MIBLO = buildMI(MBB, MBBI, Op)
236 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
237 .addReg(DstLoReg, getKillRegState(SrcIsKill))
238 .addImm(Lo8);
239
240 // SREG is always implicitly dead
241 MIBLO->getOperand(3).setIsDead();
242 }
243
244 if (!isLogicImmOpRedundant(Op, Hi8)) {
245 auto MIBHI = buildMI(MBB, MBBI, Op)
246 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
247 .addReg(DstHiReg, getKillRegState(SrcIsKill))
248 .addImm(Hi8);
249
250 if (ImpIsDead)
251 MIBHI->getOperand(3).setIsDead();
252 }
253
254 MI.eraseFromParent();
255 return true;
256 }
257
258 template <>
expand(Block & MBB,BlockIt MBBI)259 bool AVRExpandPseudo::expand<AVR::ADDWRdRr>(Block &MBB, BlockIt MBBI) {
260 return expandArith(AVR::ADDRdRr, AVR::ADCRdRr, MBB, MBBI);
261 }
262
263 template <>
expand(Block & MBB,BlockIt MBBI)264 bool AVRExpandPseudo::expand<AVR::ADCWRdRr>(Block &MBB, BlockIt MBBI) {
265 return expandArith(AVR::ADCRdRr, AVR::ADCRdRr, MBB, MBBI);
266 }
267
268 template <>
expand(Block & MBB,BlockIt MBBI)269 bool AVRExpandPseudo::expand<AVR::SUBWRdRr>(Block &MBB, BlockIt MBBI) {
270 return expandArith(AVR::SUBRdRr, AVR::SBCRdRr, MBB, MBBI);
271 }
272
273 template <>
expand(Block & MBB,BlockIt MBBI)274 bool AVRExpandPseudo::expand<AVR::SUBIWRdK>(Block &MBB, BlockIt MBBI) {
275 MachineInstr &MI = *MBBI;
276 Register DstLoReg, DstHiReg;
277 Register DstReg = MI.getOperand(0).getReg();
278 bool DstIsDead = MI.getOperand(0).isDead();
279 bool SrcIsKill = MI.getOperand(1).isKill();
280 bool ImpIsDead = MI.getOperand(3).isDead();
281 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
282
283 auto MIBLO = buildMI(MBB, MBBI, AVR::SUBIRdK)
284 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
285 .addReg(DstLoReg, getKillRegState(SrcIsKill));
286
287 auto MIBHI = buildMI(MBB, MBBI, AVR::SBCIRdK)
288 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
289 .addReg(DstHiReg, getKillRegState(SrcIsKill));
290
291 switch (MI.getOperand(2).getType()) {
292 case MachineOperand::MO_GlobalAddress: {
293 const GlobalValue *GV = MI.getOperand(2).getGlobal();
294 int64_t Offs = MI.getOperand(2).getOffset();
295 unsigned TF = MI.getOperand(2).getTargetFlags();
296 MIBLO.addGlobalAddress(GV, Offs, TF | AVRII::MO_NEG | AVRII::MO_LO);
297 MIBHI.addGlobalAddress(GV, Offs, TF | AVRII::MO_NEG | AVRII::MO_HI);
298 break;
299 }
300 case MachineOperand::MO_Immediate: {
301 unsigned Imm = MI.getOperand(2).getImm();
302 MIBLO.addImm(Imm & 0xff);
303 MIBHI.addImm((Imm >> 8) & 0xff);
304 break;
305 }
306 default:
307 llvm_unreachable("Unknown operand type!");
308 }
309
310 if (ImpIsDead)
311 MIBHI->getOperand(3).setIsDead();
312
313 // SREG is always implicitly killed
314 MIBHI->getOperand(4).setIsKill();
315
316 MI.eraseFromParent();
317 return true;
318 }
319
320 template <>
expand(Block & MBB,BlockIt MBBI)321 bool AVRExpandPseudo::expand<AVR::SBCWRdRr>(Block &MBB, BlockIt MBBI) {
322 return expandArith(AVR::SBCRdRr, AVR::SBCRdRr, MBB, MBBI);
323 }
324
325 template <>
expand(Block & MBB,BlockIt MBBI)326 bool AVRExpandPseudo::expand<AVR::SBCIWRdK>(Block &MBB, BlockIt MBBI) {
327 MachineInstr &MI = *MBBI;
328 Register DstLoReg, DstHiReg;
329 Register DstReg = MI.getOperand(0).getReg();
330 bool DstIsDead = MI.getOperand(0).isDead();
331 bool SrcIsKill = MI.getOperand(1).isKill();
332 bool ImpIsDead = MI.getOperand(3).isDead();
333 unsigned Imm = MI.getOperand(2).getImm();
334 unsigned Lo8 = Imm & 0xff;
335 unsigned Hi8 = (Imm >> 8) & 0xff;
336 unsigned OpLo = AVR::SBCIRdK;
337 unsigned OpHi = AVR::SBCIRdK;
338 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
339
340 auto MIBLO = buildMI(MBB, MBBI, OpLo)
341 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
342 .addReg(DstLoReg, getKillRegState(SrcIsKill))
343 .addImm(Lo8);
344
345 // SREG is always implicitly killed
346 MIBLO->getOperand(4).setIsKill();
347
348 auto MIBHI = buildMI(MBB, MBBI, OpHi)
349 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
350 .addReg(DstHiReg, getKillRegState(SrcIsKill))
351 .addImm(Hi8);
352
353 if (ImpIsDead)
354 MIBHI->getOperand(3).setIsDead();
355
356 // SREG is always implicitly killed
357 MIBHI->getOperand(4).setIsKill();
358
359 MI.eraseFromParent();
360 return true;
361 }
362
363 template <>
expand(Block & MBB,BlockIt MBBI)364 bool AVRExpandPseudo::expand<AVR::ANDWRdRr>(Block &MBB, BlockIt MBBI) {
365 return expandLogic(AVR::ANDRdRr, MBB, MBBI);
366 }
367
368 template <>
expand(Block & MBB,BlockIt MBBI)369 bool AVRExpandPseudo::expand<AVR::ANDIWRdK>(Block &MBB, BlockIt MBBI) {
370 return expandLogicImm(AVR::ANDIRdK, MBB, MBBI);
371 }
372
373 template <>
expand(Block & MBB,BlockIt MBBI)374 bool AVRExpandPseudo::expand<AVR::ORWRdRr>(Block &MBB, BlockIt MBBI) {
375 return expandLogic(AVR::ORRdRr, MBB, MBBI);
376 }
377
378 template <>
expand(Block & MBB,BlockIt MBBI)379 bool AVRExpandPseudo::expand<AVR::ORIWRdK>(Block &MBB, BlockIt MBBI) {
380 return expandLogicImm(AVR::ORIRdK, MBB, MBBI);
381 }
382
383 template <>
expand(Block & MBB,BlockIt MBBI)384 bool AVRExpandPseudo::expand<AVR::EORWRdRr>(Block &MBB, BlockIt MBBI) {
385 return expandLogic(AVR::EORRdRr, MBB, MBBI);
386 }
387
388 template <>
expand(Block & MBB,BlockIt MBBI)389 bool AVRExpandPseudo::expand<AVR::COMWRd>(Block &MBB, BlockIt MBBI) {
390 MachineInstr &MI = *MBBI;
391 Register DstLoReg, DstHiReg;
392 Register DstReg = MI.getOperand(0).getReg();
393 bool DstIsDead = MI.getOperand(0).isDead();
394 bool DstIsKill = MI.getOperand(1).isKill();
395 bool ImpIsDead = MI.getOperand(2).isDead();
396 unsigned OpLo = AVR::COMRd;
397 unsigned OpHi = AVR::COMRd;
398 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
399
400 auto MIBLO = buildMI(MBB, MBBI, OpLo)
401 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
402 .addReg(DstLoReg, getKillRegState(DstIsKill));
403
404 // SREG is always implicitly dead
405 MIBLO->getOperand(2).setIsDead();
406
407 auto MIBHI = buildMI(MBB, MBBI, OpHi)
408 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
409 .addReg(DstHiReg, getKillRegState(DstIsKill));
410
411 if (ImpIsDead)
412 MIBHI->getOperand(2).setIsDead();
413
414 MI.eraseFromParent();
415 return true;
416 }
417
418 template <>
expand(Block & MBB,BlockIt MBBI)419 bool AVRExpandPseudo::expand<AVR::NEGWRd>(Block &MBB, BlockIt MBBI) {
420 MachineInstr &MI = *MBBI;
421 Register DstLoReg, DstHiReg;
422 Register DstReg = MI.getOperand(0).getReg();
423 bool DstIsDead = MI.getOperand(0).isDead();
424 bool DstIsKill = MI.getOperand(1).isKill();
425 bool ImpIsDead = MI.getOperand(2).isDead();
426 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
427
428 // Do NEG on the upper byte.
429 auto MIBHI =
430 buildMI(MBB, MBBI, AVR::NEGRd)
431 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
432 .addReg(DstHiReg, getKillRegState(DstIsKill));
433 // SREG is always implicitly dead
434 MIBHI->getOperand(2).setIsDead();
435
436 // Do NEG on the lower byte.
437 buildMI(MBB, MBBI, AVR::NEGRd)
438 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
439 .addReg(DstLoReg, getKillRegState(DstIsKill));
440
441 // Do an extra SBC.
442 auto MISBCI =
443 buildMI(MBB, MBBI, AVR::SBCRdRr)
444 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
445 .addReg(DstHiReg, getKillRegState(DstIsKill))
446 .addReg(ZERO_REGISTER);
447 if (ImpIsDead)
448 MISBCI->getOperand(3).setIsDead();
449 // SREG is always implicitly killed
450 MISBCI->getOperand(4).setIsKill();
451
452 MI.eraseFromParent();
453 return true;
454 }
455
456 template <>
expand(Block & MBB,BlockIt MBBI)457 bool AVRExpandPseudo::expand<AVR::CPWRdRr>(Block &MBB, BlockIt MBBI) {
458 MachineInstr &MI = *MBBI;
459 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
460 Register DstReg = MI.getOperand(0).getReg();
461 Register SrcReg = MI.getOperand(1).getReg();
462 bool DstIsKill = MI.getOperand(0).isKill();
463 bool SrcIsKill = MI.getOperand(1).isKill();
464 bool ImpIsDead = MI.getOperand(2).isDead();
465 unsigned OpLo = AVR::CPRdRr;
466 unsigned OpHi = AVR::CPCRdRr;
467 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
468 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
469
470 // Low part
471 buildMI(MBB, MBBI, OpLo)
472 .addReg(DstLoReg, getKillRegState(DstIsKill))
473 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
474
475 auto MIBHI = buildMI(MBB, MBBI, OpHi)
476 .addReg(DstHiReg, getKillRegState(DstIsKill))
477 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
478
479 if (ImpIsDead)
480 MIBHI->getOperand(2).setIsDead();
481
482 // SREG is always implicitly killed
483 MIBHI->getOperand(3).setIsKill();
484
485 MI.eraseFromParent();
486 return true;
487 }
488
489 template <>
expand(Block & MBB,BlockIt MBBI)490 bool AVRExpandPseudo::expand<AVR::CPCWRdRr>(Block &MBB, BlockIt MBBI) {
491 MachineInstr &MI = *MBBI;
492 Register SrcLoReg, SrcHiReg, DstLoReg, DstHiReg;
493 Register DstReg = MI.getOperand(0).getReg();
494 Register SrcReg = MI.getOperand(1).getReg();
495 bool DstIsKill = MI.getOperand(0).isKill();
496 bool SrcIsKill = MI.getOperand(1).isKill();
497 bool ImpIsDead = MI.getOperand(2).isDead();
498 unsigned OpLo = AVR::CPCRdRr;
499 unsigned OpHi = AVR::CPCRdRr;
500 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
501 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
502
503 auto MIBLO = buildMI(MBB, MBBI, OpLo)
504 .addReg(DstLoReg, getKillRegState(DstIsKill))
505 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
506
507 // SREG is always implicitly killed
508 MIBLO->getOperand(3).setIsKill();
509
510 auto MIBHI = buildMI(MBB, MBBI, OpHi)
511 .addReg(DstHiReg, getKillRegState(DstIsKill))
512 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
513
514 if (ImpIsDead)
515 MIBHI->getOperand(2).setIsDead();
516
517 // SREG is always implicitly killed
518 MIBHI->getOperand(3).setIsKill();
519
520 MI.eraseFromParent();
521 return true;
522 }
523
524 template <>
expand(Block & MBB,BlockIt MBBI)525 bool AVRExpandPseudo::expand<AVR::LDIWRdK>(Block &MBB, BlockIt MBBI) {
526 MachineInstr &MI = *MBBI;
527 Register DstLoReg, DstHiReg;
528 Register DstReg = MI.getOperand(0).getReg();
529 bool DstIsDead = MI.getOperand(0).isDead();
530 unsigned OpLo = AVR::LDIRdK;
531 unsigned OpHi = AVR::LDIRdK;
532 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
533
534 auto MIBLO = buildMI(MBB, MBBI, OpLo)
535 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
536
537 auto MIBHI = buildMI(MBB, MBBI, OpHi)
538 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
539
540 switch (MI.getOperand(1).getType()) {
541 case MachineOperand::MO_GlobalAddress: {
542 const GlobalValue *GV = MI.getOperand(1).getGlobal();
543 int64_t Offs = MI.getOperand(1).getOffset();
544 unsigned TF = MI.getOperand(1).getTargetFlags();
545
546 MIBLO.addGlobalAddress(GV, Offs, TF | AVRII::MO_LO);
547 MIBHI.addGlobalAddress(GV, Offs, TF | AVRII::MO_HI);
548 break;
549 }
550 case MachineOperand::MO_BlockAddress: {
551 const BlockAddress *BA = MI.getOperand(1).getBlockAddress();
552 unsigned TF = MI.getOperand(1).getTargetFlags();
553
554 MIBLO.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_LO));
555 MIBHI.add(MachineOperand::CreateBA(BA, TF | AVRII::MO_HI));
556 break;
557 }
558 case MachineOperand::MO_Immediate: {
559 unsigned Imm = MI.getOperand(1).getImm();
560
561 MIBLO.addImm(Imm & 0xff);
562 MIBHI.addImm((Imm >> 8) & 0xff);
563 break;
564 }
565 default:
566 llvm_unreachable("Unknown operand type!");
567 }
568
569 MI.eraseFromParent();
570 return true;
571 }
572
573 template <>
expand(Block & MBB,BlockIt MBBI)574 bool AVRExpandPseudo::expand<AVR::LDSWRdK>(Block &MBB, BlockIt MBBI) {
575 MachineInstr &MI = *MBBI;
576 Register DstLoReg, DstHiReg;
577 Register DstReg = MI.getOperand(0).getReg();
578 bool DstIsDead = MI.getOperand(0).isDead();
579 unsigned OpLo = AVR::LDSRdK;
580 unsigned OpHi = AVR::LDSRdK;
581 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
582
583 auto MIBLO = buildMI(MBB, MBBI, OpLo)
584 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
585
586 auto MIBHI = buildMI(MBB, MBBI, OpHi)
587 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
588
589 switch (MI.getOperand(1).getType()) {
590 case MachineOperand::MO_GlobalAddress: {
591 const GlobalValue *GV = MI.getOperand(1).getGlobal();
592 int64_t Offs = MI.getOperand(1).getOffset();
593 unsigned TF = MI.getOperand(1).getTargetFlags();
594
595 MIBLO.addGlobalAddress(GV, Offs, TF);
596 MIBHI.addGlobalAddress(GV, Offs + 1, TF);
597 break;
598 }
599 case MachineOperand::MO_Immediate: {
600 unsigned Imm = MI.getOperand(1).getImm();
601
602 MIBLO.addImm(Imm);
603 MIBHI.addImm(Imm + 1);
604 break;
605 }
606 default:
607 llvm_unreachable("Unknown operand type!");
608 }
609
610 MIBLO.setMemRefs(MI.memoperands());
611 MIBHI.setMemRefs(MI.memoperands());
612
613 MI.eraseFromParent();
614 return true;
615 }
616
617 template <>
expand(Block & MBB,BlockIt MBBI)618 bool AVRExpandPseudo::expand<AVR::LDWRdPtr>(Block &MBB, BlockIt MBBI) {
619 MachineInstr &MI = *MBBI;
620 Register DstLoReg, DstHiReg;
621 Register DstReg = MI.getOperand(0).getReg();
622 Register TmpReg = 0; // 0 for no temporary register
623 Register SrcReg = MI.getOperand(1).getReg();
624 bool SrcIsKill = MI.getOperand(1).isKill();
625 unsigned OpLo = AVR::LDRdPtr;
626 unsigned OpHi = AVR::LDDRdPtrQ;
627 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
628
629 // Use a temporary register if src and dst registers are the same.
630 if (DstReg == SrcReg)
631 TmpReg = scavengeGPR8(MI);
632
633 Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
634 Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
635
636 // Load low byte.
637 auto MIBLO = buildMI(MBB, MBBI, OpLo)
638 .addReg(CurDstLoReg, RegState::Define)
639 .addReg(SrcReg);
640
641 // Push low byte onto stack if necessary.
642 if (TmpReg)
643 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
644
645 // Load high byte.
646 auto MIBHI = buildMI(MBB, MBBI, OpHi)
647 .addReg(CurDstHiReg, RegState::Define)
648 .addReg(SrcReg, getKillRegState(SrcIsKill))
649 .addImm(1);
650
651 if (TmpReg) {
652 // Move the high byte into the final destination.
653 buildMI(MBB, MBBI, AVR::MOVRdRr, DstHiReg).addReg(TmpReg);
654
655 // Move the low byte from the scratch space into the final destination.
656 buildMI(MBB, MBBI, AVR::POPRd, DstLoReg);
657 }
658
659 MIBLO.setMemRefs(MI.memoperands());
660 MIBHI.setMemRefs(MI.memoperands());
661
662 MI.eraseFromParent();
663 return true;
664 }
665
666 template <>
expand(Block & MBB,BlockIt MBBI)667 bool AVRExpandPseudo::expand<AVR::LDWRdPtrPi>(Block &MBB, BlockIt MBBI) {
668 MachineInstr &MI = *MBBI;
669 Register DstLoReg, DstHiReg;
670 Register DstReg = MI.getOperand(0).getReg();
671 Register SrcReg = MI.getOperand(1).getReg();
672 bool DstIsDead = MI.getOperand(0).isDead();
673 bool SrcIsDead = MI.getOperand(1).isKill();
674 unsigned OpLo = AVR::LDRdPtrPi;
675 unsigned OpHi = AVR::LDRdPtrPi;
676 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
677
678 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
679
680 auto MIBLO = buildMI(MBB, MBBI, OpLo)
681 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
682 .addReg(SrcReg, RegState::Define)
683 .addReg(SrcReg, RegState::Kill);
684
685 auto MIBHI = buildMI(MBB, MBBI, OpHi)
686 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
687 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
688 .addReg(SrcReg, RegState::Kill);
689
690 MIBLO.setMemRefs(MI.memoperands());
691 MIBHI.setMemRefs(MI.memoperands());
692
693 MI.eraseFromParent();
694 return true;
695 }
696
697 template <>
expand(Block & MBB,BlockIt MBBI)698 bool AVRExpandPseudo::expand<AVR::LDWRdPtrPd>(Block &MBB, BlockIt MBBI) {
699 MachineInstr &MI = *MBBI;
700 Register DstLoReg, DstHiReg;
701 Register DstReg = MI.getOperand(0).getReg();
702 Register SrcReg = MI.getOperand(1).getReg();
703 bool DstIsDead = MI.getOperand(0).isDead();
704 bool SrcIsDead = MI.getOperand(1).isKill();
705 unsigned OpLo = AVR::LDRdPtrPd;
706 unsigned OpHi = AVR::LDRdPtrPd;
707 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
708
709 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
710
711 auto MIBHI = buildMI(MBB, MBBI, OpHi)
712 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
713 .addReg(SrcReg, RegState::Define)
714 .addReg(SrcReg, RegState::Kill);
715
716 auto MIBLO = buildMI(MBB, MBBI, OpLo)
717 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
718 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
719 .addReg(SrcReg, RegState::Kill);
720
721 MIBLO.setMemRefs(MI.memoperands());
722 MIBHI.setMemRefs(MI.memoperands());
723
724 MI.eraseFromParent();
725 return true;
726 }
727
728 template <>
expand(Block & MBB,BlockIt MBBI)729 bool AVRExpandPseudo::expand<AVR::LDDWRdPtrQ>(Block &MBB, BlockIt MBBI) {
730 MachineInstr &MI = *MBBI;
731 Register DstLoReg, DstHiReg;
732 Register DstReg = MI.getOperand(0).getReg();
733 Register TmpReg = 0; // 0 for no temporary register
734 Register SrcReg = MI.getOperand(1).getReg();
735 unsigned Imm = MI.getOperand(2).getImm();
736 bool SrcIsKill = MI.getOperand(1).isKill();
737 unsigned OpLo = AVR::LDDRdPtrQ;
738 unsigned OpHi = AVR::LDDRdPtrQ;
739 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
740
741 // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
742 // allowed for the instruction, 62 is the limit here.
743 assert(Imm <= 62 && "Offset is out of range");
744
745 // Use a temporary register if src and dst registers are the same.
746 if (DstReg == SrcReg)
747 TmpReg = scavengeGPR8(MI);
748
749 Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
750 Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
751
752 // Load low byte.
753 auto MIBLO = buildMI(MBB, MBBI, OpLo)
754 .addReg(CurDstLoReg, RegState::Define)
755 .addReg(SrcReg)
756 .addImm(Imm);
757
758 // Push low byte onto stack if necessary.
759 if (TmpReg)
760 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
761
762 // Load high byte.
763 auto MIBHI = buildMI(MBB, MBBI, OpHi)
764 .addReg(CurDstHiReg, RegState::Define)
765 .addReg(SrcReg, getKillRegState(SrcIsKill))
766 .addImm(Imm + 1);
767
768 if (TmpReg) {
769 // Move the high byte into the final destination.
770 buildMI(MBB, MBBI, AVR::MOVRdRr, DstHiReg).addReg(TmpReg);
771
772 // Move the low byte from the scratch space into the final destination.
773 buildMI(MBB, MBBI, AVR::POPRd, DstLoReg);
774 }
775
776 MIBLO.setMemRefs(MI.memoperands());
777 MIBHI.setMemRefs(MI.memoperands());
778
779 MI.eraseFromParent();
780 return true;
781 }
782
783 template <>
expand(Block & MBB,BlockIt MBBI)784 bool AVRExpandPseudo::expand<AVR::LPMWRdZ>(Block &MBB, BlockIt MBBI) {
785 MachineInstr &MI = *MBBI;
786 Register DstLoReg, DstHiReg;
787 Register DstReg = MI.getOperand(0).getReg();
788 Register TmpReg = 0; // 0 for no temporary register
789 Register SrcReg = MI.getOperand(1).getReg();
790 bool SrcIsKill = MI.getOperand(1).isKill();
791 unsigned OpLo = AVR::LPMRdZPi;
792 unsigned OpHi = AVR::LPMRdZ;
793 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
794
795 // Use a temporary register if src and dst registers are the same.
796 if (DstReg == SrcReg)
797 TmpReg = scavengeGPR8(MI);
798
799 Register CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg;
800 Register CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg;
801
802 // Load low byte.
803 auto MIBLO = buildMI(MBB, MBBI, OpLo)
804 .addReg(CurDstLoReg, RegState::Define)
805 .addReg(SrcReg);
806
807 // Push low byte onto stack if necessary.
808 if (TmpReg)
809 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
810
811 // Load high byte.
812 auto MIBHI = buildMI(MBB, MBBI, OpHi)
813 .addReg(CurDstHiReg, RegState::Define)
814 .addReg(SrcReg, getKillRegState(SrcIsKill));
815
816 if (TmpReg) {
817 // Move the high byte into the final destination.
818 buildMI(MBB, MBBI, AVR::MOVRdRr, DstHiReg).addReg(TmpReg);
819
820 // Move the low byte from the scratch space into the final destination.
821 buildMI(MBB, MBBI, AVR::POPRd, DstLoReg);
822 }
823
824 MIBLO.setMemRefs(MI.memoperands());
825 MIBHI.setMemRefs(MI.memoperands());
826
827 MI.eraseFromParent();
828 return true;
829 }
830
831 template <>
expand(Block & MBB,BlockIt MBBI)832 bool AVRExpandPseudo::expand<AVR::LPMWRdZPi>(Block &MBB, BlockIt MBBI) {
833 llvm_unreachable("wide LPMPi is unimplemented");
834 }
835
836 template<typename Func>
expandAtomic(Block & MBB,BlockIt MBBI,Func f)837 bool AVRExpandPseudo::expandAtomic(Block &MBB, BlockIt MBBI, Func f) {
838 // Remove the pseudo instruction.
839 MachineInstr &MI = *MBBI;
840
841 // Store the SREG.
842 buildMI(MBB, MBBI, AVR::INRdA)
843 .addReg(SCRATCH_REGISTER, RegState::Define)
844 .addImm(SREG_ADDR);
845
846 // Disable exceptions.
847 buildMI(MBB, MBBI, AVR::BCLRs).addImm(7); // CLI
848
849 f(MI);
850
851 // Restore the status reg.
852 buildMI(MBB, MBBI, AVR::OUTARr)
853 .addImm(SREG_ADDR)
854 .addReg(SCRATCH_REGISTER);
855
856 MI.eraseFromParent();
857 return true;
858 }
859
860 template<typename Func>
expandAtomicBinaryOp(unsigned Opcode,Block & MBB,BlockIt MBBI,Func f)861 bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode,
862 Block &MBB,
863 BlockIt MBBI,
864 Func f) {
865 return expandAtomic(MBB, MBBI, [&](MachineInstr &MI) {
866 auto Op1 = MI.getOperand(0);
867 auto Op2 = MI.getOperand(1);
868
869 MachineInstr &NewInst =
870 *buildMI(MBB, MBBI, Opcode).add(Op1).add(Op2).getInstr();
871 f(NewInst);
872 });
873 }
874
expandAtomicBinaryOp(unsigned Opcode,Block & MBB,BlockIt MBBI)875 bool AVRExpandPseudo::expandAtomicBinaryOp(unsigned Opcode,
876 Block &MBB,
877 BlockIt MBBI) {
878 return expandAtomicBinaryOp(Opcode, MBB, MBBI, [](MachineInstr &MI) {});
879 }
880
expandAtomicArithmeticOp(unsigned Width,unsigned ArithOpcode,Block & MBB,BlockIt MBBI)881 bool AVRExpandPseudo::expandAtomicArithmeticOp(unsigned Width,
882 unsigned ArithOpcode,
883 Block &MBB,
884 BlockIt MBBI) {
885 return expandAtomic(MBB, MBBI, [&](MachineInstr &MI) {
886 auto Op1 = MI.getOperand(0);
887 auto Op2 = MI.getOperand(1);
888
889 unsigned LoadOpcode = (Width == 8) ? AVR::LDRdPtr : AVR::LDWRdPtr;
890 unsigned StoreOpcode = (Width == 8) ? AVR::STPtrRr : AVR::STWPtrRr;
891
892 // Create the load
893 buildMI(MBB, MBBI, LoadOpcode).add(Op1).add(Op2);
894
895 // Create the arithmetic op
896 buildMI(MBB, MBBI, ArithOpcode).add(Op1).add(Op1).add(Op2);
897
898 // Create the store
899 buildMI(MBB, MBBI, StoreOpcode).add(Op2).add(Op1);
900 });
901 }
902
scavengeGPR8(MachineInstr & MI)903 Register AVRExpandPseudo::scavengeGPR8(MachineInstr &MI) {
904 MachineBasicBlock &MBB = *MI.getParent();
905 RegScavenger RS;
906
907 RS.enterBasicBlock(MBB);
908 RS.forward(MI);
909
910 BitVector Candidates =
911 TRI->getAllocatableSet
912 (*MBB.getParent(), &AVR::GPR8RegClass);
913
914 // Exclude all the registers being used by the instruction.
915 for (MachineOperand &MO : MI.operands()) {
916 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
917 !Register::isVirtualRegister(MO.getReg()))
918 Candidates.reset(MO.getReg());
919 }
920
921 BitVector Available = RS.getRegsAvailable(&AVR::GPR8RegClass);
922 Available &= Candidates;
923
924 signed Reg = Available.find_first();
925 assert(Reg != -1 && "ran out of registers");
926 return Reg;
927 }
928
929 template<>
expand(Block & MBB,BlockIt MBBI)930 bool AVRExpandPseudo::expand<AVR::AtomicLoad8>(Block &MBB, BlockIt MBBI) {
931 return expandAtomicBinaryOp(AVR::LDRdPtr, MBB, MBBI);
932 }
933
934 template<>
expand(Block & MBB,BlockIt MBBI)935 bool AVRExpandPseudo::expand<AVR::AtomicLoad16>(Block &MBB, BlockIt MBBI) {
936 return expandAtomicBinaryOp(AVR::LDWRdPtr, MBB, MBBI);
937 }
938
939 template<>
expand(Block & MBB,BlockIt MBBI)940 bool AVRExpandPseudo::expand<AVR::AtomicStore8>(Block &MBB, BlockIt MBBI) {
941 return expandAtomicBinaryOp(AVR::STPtrRr, MBB, MBBI);
942 }
943
944 template<>
expand(Block & MBB,BlockIt MBBI)945 bool AVRExpandPseudo::expand<AVR::AtomicStore16>(Block &MBB, BlockIt MBBI) {
946 return expandAtomicBinaryOp(AVR::STWPtrRr, MBB, MBBI);
947 }
948
949 template<>
expand(Block & MBB,BlockIt MBBI)950 bool AVRExpandPseudo::expand<AVR::AtomicLoadAdd8>(Block &MBB, BlockIt MBBI) {
951 return expandAtomicArithmeticOp(8, AVR::ADDRdRr, MBB, MBBI);
952 }
953
954 template<>
expand(Block & MBB,BlockIt MBBI)955 bool AVRExpandPseudo::expand<AVR::AtomicLoadAdd16>(Block &MBB, BlockIt MBBI) {
956 return expandAtomicArithmeticOp(16, AVR::ADDWRdRr, MBB, MBBI);
957 }
958
959 template<>
expand(Block & MBB,BlockIt MBBI)960 bool AVRExpandPseudo::expand<AVR::AtomicLoadSub8>(Block &MBB, BlockIt MBBI) {
961 return expandAtomicArithmeticOp(8, AVR::SUBRdRr, MBB, MBBI);
962 }
963
964 template<>
expand(Block & MBB,BlockIt MBBI)965 bool AVRExpandPseudo::expand<AVR::AtomicLoadSub16>(Block &MBB, BlockIt MBBI) {
966 return expandAtomicArithmeticOp(16, AVR::SUBWRdRr, MBB, MBBI);
967 }
968
969 template<>
expand(Block & MBB,BlockIt MBBI)970 bool AVRExpandPseudo::expand<AVR::AtomicLoadAnd8>(Block &MBB, BlockIt MBBI) {
971 return expandAtomicArithmeticOp(8, AVR::ANDRdRr, MBB, MBBI);
972 }
973
974 template<>
expand(Block & MBB,BlockIt MBBI)975 bool AVRExpandPseudo::expand<AVR::AtomicLoadAnd16>(Block &MBB, BlockIt MBBI) {
976 return expandAtomicArithmeticOp(16, AVR::ANDWRdRr, MBB, MBBI);
977 }
978
979 template<>
expand(Block & MBB,BlockIt MBBI)980 bool AVRExpandPseudo::expand<AVR::AtomicLoadOr8>(Block &MBB, BlockIt MBBI) {
981 return expandAtomicArithmeticOp(8, AVR::ORRdRr, MBB, MBBI);
982 }
983
984 template<>
expand(Block & MBB,BlockIt MBBI)985 bool AVRExpandPseudo::expand<AVR::AtomicLoadOr16>(Block &MBB, BlockIt MBBI) {
986 return expandAtomicArithmeticOp(16, AVR::ORWRdRr, MBB, MBBI);
987 }
988
989 template<>
expand(Block & MBB,BlockIt MBBI)990 bool AVRExpandPseudo::expand<AVR::AtomicLoadXor8>(Block &MBB, BlockIt MBBI) {
991 return expandAtomicArithmeticOp(8, AVR::EORRdRr, MBB, MBBI);
992 }
993
994 template<>
expand(Block & MBB,BlockIt MBBI)995 bool AVRExpandPseudo::expand<AVR::AtomicLoadXor16>(Block &MBB, BlockIt MBBI) {
996 return expandAtomicArithmeticOp(16, AVR::EORWRdRr, MBB, MBBI);
997 }
998
999 template<>
expand(Block & MBB,BlockIt MBBI)1000 bool AVRExpandPseudo::expand<AVR::AtomicFence>(Block &MBB, BlockIt MBBI) {
1001 // On AVR, there is only one core and so atomic fences do nothing.
1002 MBBI->eraseFromParent();
1003 return true;
1004 }
1005
1006 template <>
expand(Block & MBB,BlockIt MBBI)1007 bool AVRExpandPseudo::expand<AVR::STSWKRr>(Block &MBB, BlockIt MBBI) {
1008 MachineInstr &MI = *MBBI;
1009 Register SrcLoReg, SrcHiReg;
1010 Register SrcReg = MI.getOperand(1).getReg();
1011 bool SrcIsKill = MI.getOperand(1).isKill();
1012 unsigned OpLo = AVR::STSKRr;
1013 unsigned OpHi = AVR::STSKRr;
1014 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1015
1016 // Write the high byte first in case this address belongs to a special
1017 // I/O address with a special temporary register.
1018 auto MIBHI = buildMI(MBB, MBBI, OpHi);
1019 auto MIBLO = buildMI(MBB, MBBI, OpLo);
1020
1021 switch (MI.getOperand(0).getType()) {
1022 case MachineOperand::MO_GlobalAddress: {
1023 const GlobalValue *GV = MI.getOperand(0).getGlobal();
1024 int64_t Offs = MI.getOperand(0).getOffset();
1025 unsigned TF = MI.getOperand(0).getTargetFlags();
1026
1027 MIBLO.addGlobalAddress(GV, Offs, TF);
1028 MIBHI.addGlobalAddress(GV, Offs + 1, TF);
1029 break;
1030 }
1031 case MachineOperand::MO_Immediate: {
1032 unsigned Imm = MI.getOperand(0).getImm();
1033
1034 MIBLO.addImm(Imm);
1035 MIBHI.addImm(Imm + 1);
1036 break;
1037 }
1038 default:
1039 llvm_unreachable("Unknown operand type!");
1040 }
1041
1042 MIBLO.addReg(SrcLoReg, getKillRegState(SrcIsKill));
1043 MIBHI.addReg(SrcHiReg, getKillRegState(SrcIsKill));
1044
1045 MIBLO.setMemRefs(MI.memoperands());
1046 MIBHI.setMemRefs(MI.memoperands());
1047
1048 MI.eraseFromParent();
1049 return true;
1050 }
1051
1052 template <>
expand(Block & MBB,BlockIt MBBI)1053 bool AVRExpandPseudo::expand<AVR::STWPtrRr>(Block &MBB, BlockIt MBBI) {
1054 MachineInstr &MI = *MBBI;
1055 Register SrcLoReg, SrcHiReg;
1056 Register DstReg = MI.getOperand(0).getReg();
1057 Register SrcReg = MI.getOperand(1).getReg();
1058 bool DstIsUndef = MI.getOperand(0).isUndef();
1059 bool SrcIsKill = MI.getOperand(1).isKill();
1060 unsigned OpLo = AVR::STPtrRr;
1061 unsigned OpHi = AVR::STDPtrQRr;
1062 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1063
1064 //:TODO: need to reverse this order like inw and stsw?
1065 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1066 .addReg(DstReg, getUndefRegState(DstIsUndef))
1067 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1068
1069 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1070 .addReg(DstReg, getUndefRegState(DstIsUndef))
1071 .addImm(1)
1072 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1073
1074 MIBLO.setMemRefs(MI.memoperands());
1075 MIBHI.setMemRefs(MI.memoperands());
1076
1077 MI.eraseFromParent();
1078 return true;
1079 }
1080
1081 template <>
expand(Block & MBB,BlockIt MBBI)1082 bool AVRExpandPseudo::expand<AVR::STWPtrPiRr>(Block &MBB, BlockIt MBBI) {
1083 MachineInstr &MI = *MBBI;
1084 Register SrcLoReg, SrcHiReg;
1085 Register DstReg = MI.getOperand(0).getReg();
1086 Register SrcReg = MI.getOperand(2).getReg();
1087 unsigned Imm = MI.getOperand(3).getImm();
1088 bool DstIsDead = MI.getOperand(0).isDead();
1089 bool SrcIsKill = MI.getOperand(2).isKill();
1090 unsigned OpLo = AVR::STPtrPiRr;
1091 unsigned OpHi = AVR::STPtrPiRr;
1092 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1093
1094 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
1095
1096 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1097 .addReg(DstReg, RegState::Define)
1098 .addReg(DstReg, RegState::Kill)
1099 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1100 .addImm(Imm);
1101
1102 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1103 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1104 .addReg(DstReg, RegState::Kill)
1105 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1106 .addImm(Imm);
1107
1108 MIBLO.setMemRefs(MI.memoperands());
1109 MIBHI.setMemRefs(MI.memoperands());
1110
1111 MI.eraseFromParent();
1112 return true;
1113 }
1114
1115 template <>
expand(Block & MBB,BlockIt MBBI)1116 bool AVRExpandPseudo::expand<AVR::STWPtrPdRr>(Block &MBB, BlockIt MBBI) {
1117 MachineInstr &MI = *MBBI;
1118 Register SrcLoReg, SrcHiReg;
1119 Register DstReg = MI.getOperand(0).getReg();
1120 Register SrcReg = MI.getOperand(2).getReg();
1121 unsigned Imm = MI.getOperand(3).getImm();
1122 bool DstIsDead = MI.getOperand(0).isDead();
1123 bool SrcIsKill = MI.getOperand(2).isKill();
1124 unsigned OpLo = AVR::STPtrPdRr;
1125 unsigned OpHi = AVR::STPtrPdRr;
1126 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1127
1128 assert(DstReg != SrcReg && "SrcReg and DstReg cannot be the same");
1129
1130 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1131 .addReg(DstReg, RegState::Define)
1132 .addReg(DstReg, RegState::Kill)
1133 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1134 .addImm(Imm);
1135
1136 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1137 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1138 .addReg(DstReg, RegState::Kill)
1139 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1140 .addImm(Imm);
1141
1142 MIBLO.setMemRefs(MI.memoperands());
1143 MIBHI.setMemRefs(MI.memoperands());
1144
1145 MI.eraseFromParent();
1146 return true;
1147 }
1148
1149 template <>
expand(Block & MBB,BlockIt MBBI)1150 bool AVRExpandPseudo::expand<AVR::STDWPtrQRr>(Block &MBB, BlockIt MBBI) {
1151 MachineInstr &MI = *MBBI;
1152 Register SrcLoReg, SrcHiReg;
1153 Register DstReg = MI.getOperand(0).getReg();
1154 Register SrcReg = MI.getOperand(2).getReg();
1155 unsigned Imm = MI.getOperand(1).getImm();
1156 bool DstIsKill = MI.getOperand(0).isKill();
1157 bool SrcIsKill = MI.getOperand(2).isKill();
1158 unsigned OpLo = AVR::STDPtrQRr;
1159 unsigned OpHi = AVR::STDPtrQRr;
1160 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1161
1162 // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
1163 // allowed for the instruction, 62 is the limit here.
1164 assert(Imm <= 62 && "Offset is out of range");
1165
1166 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1167 .addReg(DstReg)
1168 .addImm(Imm)
1169 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1170
1171 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1172 .addReg(DstReg, getKillRegState(DstIsKill))
1173 .addImm(Imm + 1)
1174 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1175
1176 MIBLO.setMemRefs(MI.memoperands());
1177 MIBHI.setMemRefs(MI.memoperands());
1178
1179 MI.eraseFromParent();
1180 return true;
1181 }
1182
1183 template <>
expand(Block & MBB,BlockIt MBBI)1184 bool AVRExpandPseudo::expand<AVR::INWRdA>(Block &MBB, BlockIt MBBI) {
1185 MachineInstr &MI = *MBBI;
1186 Register DstLoReg, DstHiReg;
1187 unsigned Imm = MI.getOperand(1).getImm();
1188 Register DstReg = MI.getOperand(0).getReg();
1189 bool DstIsDead = MI.getOperand(0).isDead();
1190 unsigned OpLo = AVR::INRdA;
1191 unsigned OpHi = AVR::INRdA;
1192 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1193
1194 // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
1195 // allowed for the instruction, 62 is the limit here.
1196 assert(Imm <= 62 && "Address is out of range");
1197
1198 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1199 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1200 .addImm(Imm);
1201
1202 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1203 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1204 .addImm(Imm + 1);
1205
1206 MIBLO.setMemRefs(MI.memoperands());
1207 MIBHI.setMemRefs(MI.memoperands());
1208
1209 MI.eraseFromParent();
1210 return true;
1211 }
1212
1213 template <>
expand(Block & MBB,BlockIt MBBI)1214 bool AVRExpandPseudo::expand<AVR::OUTWARr>(Block &MBB, BlockIt MBBI) {
1215 MachineInstr &MI = *MBBI;
1216 Register SrcLoReg, SrcHiReg;
1217 unsigned Imm = MI.getOperand(0).getImm();
1218 Register SrcReg = MI.getOperand(1).getReg();
1219 bool SrcIsKill = MI.getOperand(1).isKill();
1220 unsigned OpLo = AVR::OUTARr;
1221 unsigned OpHi = AVR::OUTARr;
1222 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1223
1224 // Since we add 1 to the Imm value for the high byte below, and 63 is the highest Imm value
1225 // allowed for the instruction, 62 is the limit here.
1226 assert(Imm <= 62 && "Address is out of range");
1227
1228 // 16 bit I/O writes need the high byte first
1229 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1230 .addImm(Imm + 1)
1231 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1232
1233 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1234 .addImm(Imm)
1235 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1236
1237 MIBLO.setMemRefs(MI.memoperands());
1238 MIBHI.setMemRefs(MI.memoperands());
1239
1240 MI.eraseFromParent();
1241 return true;
1242 }
1243
1244 template <>
expand(Block & MBB,BlockIt MBBI)1245 bool AVRExpandPseudo::expand<AVR::PUSHWRr>(Block &MBB, BlockIt MBBI) {
1246 MachineInstr &MI = *MBBI;
1247 Register SrcLoReg, SrcHiReg;
1248 Register SrcReg = MI.getOperand(0).getReg();
1249 bool SrcIsKill = MI.getOperand(0).isKill();
1250 unsigned Flags = MI.getFlags();
1251 unsigned OpLo = AVR::PUSHRr;
1252 unsigned OpHi = AVR::PUSHRr;
1253 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
1254
1255 // Low part
1256 buildMI(MBB, MBBI, OpLo)
1257 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1258 .setMIFlags(Flags);
1259
1260 // High part
1261 buildMI(MBB, MBBI, OpHi)
1262 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1263 .setMIFlags(Flags);
1264
1265 MI.eraseFromParent();
1266 return true;
1267 }
1268
1269 template <>
expand(Block & MBB,BlockIt MBBI)1270 bool AVRExpandPseudo::expand<AVR::POPWRd>(Block &MBB, BlockIt MBBI) {
1271 MachineInstr &MI = *MBBI;
1272 Register DstLoReg, DstHiReg;
1273 Register DstReg = MI.getOperand(0).getReg();
1274 unsigned Flags = MI.getFlags();
1275 unsigned OpLo = AVR::POPRd;
1276 unsigned OpHi = AVR::POPRd;
1277 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1278
1279 buildMI(MBB, MBBI, OpHi, DstHiReg).setMIFlags(Flags); // High
1280 buildMI(MBB, MBBI, OpLo, DstLoReg).setMIFlags(Flags); // Low
1281
1282 MI.eraseFromParent();
1283 return true;
1284 }
1285
1286 template <>
expand(Block & MBB,BlockIt MBBI)1287 bool AVRExpandPseudo::expand<AVR::ROLBRd>(Block &MBB, BlockIt MBBI) {
1288 // In AVR, the rotate instructions behave quite unintuitively. They rotate
1289 // bits through the carry bit in SREG, effectively rotating over 9 bits,
1290 // instead of 8. This is useful when we are dealing with numbers over
1291 // multiple registers, but when we actually need to rotate stuff, we have
1292 // to explicitly add the carry bit.
1293
1294 MachineInstr &MI = *MBBI;
1295 unsigned OpShift, OpCarry;
1296 Register DstReg = MI.getOperand(0).getReg();
1297 bool DstIsDead = MI.getOperand(0).isDead();
1298 OpShift = AVR::ADDRdRr;
1299 OpCarry = AVR::ADCRdRr;
1300
1301 // add r16, r16
1302 // adc r16, r1
1303
1304 // Shift part
1305 buildMI(MBB, MBBI, OpShift)
1306 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1307 .addReg(DstReg)
1308 .addReg(DstReg);
1309
1310 // Add the carry bit
1311 auto MIB = buildMI(MBB, MBBI, OpCarry)
1312 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1313 .addReg(DstReg)
1314 .addReg(ZERO_REGISTER);
1315
1316 // SREG is always implicitly killed
1317 MIB->getOperand(2).setIsKill();
1318
1319 MI.eraseFromParent();
1320 return true;
1321 }
1322
1323 template <>
expand(Block & MBB,BlockIt MBBI)1324 bool AVRExpandPseudo::expand<AVR::RORBRd>(Block &MBB, BlockIt MBBI) {
1325 // In AVR, the rotate instructions behave quite unintuitively. They rotate
1326 // bits through the carry bit in SREG, effectively rotating over 9 bits,
1327 // instead of 8. This is useful when we are dealing with numbers over
1328 // multiple registers, but when we actually need to rotate stuff, we have
1329 // to explicitly add the carry bit.
1330
1331 MachineInstr &MI = *MBBI;
1332 unsigned OpShiftOut, OpLoad, OpShiftIn, OpAdd;
1333 Register DstReg = MI.getOperand(0).getReg();
1334 bool DstIsDead = MI.getOperand(0).isDead();
1335 OpShiftOut = AVR::LSRRd;
1336 OpLoad = AVR::LDIRdK;
1337 OpShiftIn = AVR::RORRd;
1338 OpAdd = AVR::ORRdRr;
1339
1340 // lsr r16
1341 // ldi r0, 0
1342 // ror r0
1343 // or r16, r17
1344
1345 // Shift out
1346 buildMI(MBB, MBBI, OpShiftOut)
1347 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1348 .addReg(DstReg);
1349
1350 // Put 0 in temporary register
1351 buildMI(MBB, MBBI, OpLoad)
1352 .addReg(SCRATCH_REGISTER, RegState::Define | getDeadRegState(true))
1353 .addImm(0x00);
1354
1355 // Shift in
1356 buildMI(MBB, MBBI, OpShiftIn)
1357 .addReg(SCRATCH_REGISTER, RegState::Define | getDeadRegState(true))
1358 .addReg(SCRATCH_REGISTER);
1359
1360 // Add the results together using an or-instruction
1361 auto MIB = buildMI(MBB, MBBI, OpAdd)
1362 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1363 .addReg(DstReg)
1364 .addReg(SCRATCH_REGISTER);
1365
1366 // SREG is always implicitly killed
1367 MIB->getOperand(2).setIsKill();
1368
1369 MI.eraseFromParent();
1370 return true;
1371 }
1372
1373 template <>
expand(Block & MBB,BlockIt MBBI)1374 bool AVRExpandPseudo::expand<AVR::LSLWRd>(Block &MBB, BlockIt MBBI) {
1375 MachineInstr &MI = *MBBI;
1376 Register DstLoReg, DstHiReg;
1377 Register DstReg = MI.getOperand(0).getReg();
1378 bool DstIsDead = MI.getOperand(0).isDead();
1379 bool DstIsKill = MI.getOperand(1).isKill();
1380 bool ImpIsDead = MI.getOperand(2).isDead();
1381 unsigned OpLo = AVR::ADDRdRr; // ADD Rd, Rd <==> LSL Rd
1382 unsigned OpHi = AVR::ADCRdRr; // ADC Rd, Rd <==> ROL Rd
1383 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1384
1385 // Low part
1386 buildMI(MBB, MBBI, OpLo)
1387 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1388 .addReg(DstLoReg)
1389 .addReg(DstLoReg, getKillRegState(DstIsKill));
1390
1391 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1392 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1393 .addReg(DstHiReg)
1394 .addReg(DstHiReg, getKillRegState(DstIsKill));
1395
1396 if (ImpIsDead)
1397 MIBHI->getOperand(3).setIsDead();
1398
1399 // SREG is always implicitly killed
1400 MIBHI->getOperand(4).setIsKill();
1401
1402 MI.eraseFromParent();
1403 return true;
1404 }
1405
1406 template <>
expand(Block & MBB,BlockIt MBBI)1407 bool AVRExpandPseudo::expand<AVR::LSLW4Rd>(Block &MBB, BlockIt MBBI) {
1408 MachineInstr &MI = *MBBI;
1409 Register DstLoReg, DstHiReg;
1410 Register DstReg = MI.getOperand(0).getReg();
1411 bool DstIsDead = MI.getOperand(0).isDead();
1412 bool DstIsKill = MI.getOperand(1).isKill();
1413 bool ImpIsDead = MI.getOperand(2).isDead();
1414 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1415
1416 // swap Rh
1417 // swap Rl
1418 buildMI(MBB, MBBI, AVR::SWAPRd)
1419 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1420 .addReg(DstHiReg, getKillRegState(DstIsKill));
1421 buildMI(MBB, MBBI, AVR::SWAPRd)
1422 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1423 .addReg(DstLoReg, getKillRegState(DstIsKill));
1424
1425 // andi Rh, 0xf0
1426 auto MI0 =
1427 buildMI(MBB, MBBI, AVR::ANDIRdK)
1428 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1429 .addReg(DstHiReg, getKillRegState(DstIsKill))
1430 .addImm(0xf0);
1431 // SREG is implicitly dead.
1432 MI0->getOperand(3).setIsDead();
1433
1434 // eor Rh, Rl
1435 auto MI1 =
1436 buildMI(MBB, MBBI, AVR::EORRdRr)
1437 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1438 .addReg(DstHiReg, getKillRegState(DstIsKill))
1439 .addReg(DstLoReg);
1440 // SREG is implicitly dead.
1441 MI1->getOperand(3).setIsDead();
1442
1443 // andi Rl, 0xf0
1444 auto MI2 =
1445 buildMI(MBB, MBBI, AVR::ANDIRdK)
1446 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1447 .addReg(DstLoReg, getKillRegState(DstIsKill))
1448 .addImm(0xf0);
1449 // SREG is implicitly dead.
1450 MI2->getOperand(3).setIsDead();
1451
1452 // eor Rh, Rl
1453 auto MI3 =
1454 buildMI(MBB, MBBI, AVR::EORRdRr)
1455 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1456 .addReg(DstHiReg, getKillRegState(DstIsKill))
1457 .addReg(DstLoReg);
1458 if (ImpIsDead)
1459 MI3->getOperand(3).setIsDead();
1460
1461 MI.eraseFromParent();
1462 return true;
1463 }
1464
1465 template <>
expand(Block & MBB,BlockIt MBBI)1466 bool AVRExpandPseudo::expand<AVR::LSLW8Rd>(Block &MBB, BlockIt MBBI) {
1467 MachineInstr &MI = *MBBI;
1468 Register DstLoReg, DstHiReg;
1469 Register DstReg = MI.getOperand(0).getReg();
1470 bool DstIsDead = MI.getOperand(0).isDead();
1471 bool DstIsKill = MI.getOperand(1).isKill();
1472 bool ImpIsDead = MI.getOperand(2).isDead();
1473 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1474
1475 // mov Rh, Rl
1476 buildMI(MBB, MBBI, AVR::MOVRdRr)
1477 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1478 .addReg(DstLoReg);
1479
1480 // clr Rl
1481 auto MIBLO =
1482 buildMI(MBB, MBBI, AVR::EORRdRr)
1483 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1484 .addReg(DstLoReg, getKillRegState(DstIsKill))
1485 .addReg(DstLoReg, getKillRegState(DstIsKill));
1486 if (ImpIsDead)
1487 MIBLO->getOperand(3).setIsDead();
1488
1489 MI.eraseFromParent();
1490 return true;
1491 }
1492
1493 template <>
expand(Block & MBB,BlockIt MBBI)1494 bool AVRExpandPseudo::expand<AVR::LSLW12Rd>(Block &MBB, BlockIt MBBI) {
1495 MachineInstr &MI = *MBBI;
1496 Register DstLoReg, DstHiReg;
1497 Register DstReg = MI.getOperand(0).getReg();
1498 bool DstIsDead = MI.getOperand(0).isDead();
1499 bool DstIsKill = MI.getOperand(1).isKill();
1500 bool ImpIsDead = MI.getOperand(2).isDead();
1501 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1502
1503 // mov Rh, Rl
1504 buildMI(MBB, MBBI, AVR::MOVRdRr)
1505 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1506 .addReg(DstLoReg);
1507
1508 // swap Rh
1509 buildMI(MBB, MBBI, AVR::SWAPRd)
1510 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1511 .addReg(DstHiReg, getKillRegState(DstIsKill));
1512
1513 // andi Rh, 0xf0
1514 auto MI0 =
1515 buildMI(MBB, MBBI, AVR::ANDIRdK)
1516 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1517 .addReg(DstHiReg, getKillRegState(DstIsKill))
1518 .addImm(0xf0);
1519 // SREG is implicitly dead.
1520 MI0->getOperand(3).setIsDead();
1521
1522 // clr Rl
1523 auto MI1 =
1524 buildMI(MBB, MBBI, AVR::EORRdRr)
1525 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1526 .addReg(DstLoReg, getKillRegState(DstIsKill))
1527 .addReg(DstLoReg, getKillRegState(DstIsKill));
1528 if (ImpIsDead)
1529 MI1->getOperand(3).setIsDead();
1530
1531 MI.eraseFromParent();
1532 return true;
1533 }
1534
1535 template <>
expand(Block & MBB,BlockIt MBBI)1536 bool AVRExpandPseudo::expand<AVR::LSRWRd>(Block &MBB, BlockIt MBBI) {
1537 MachineInstr &MI = *MBBI;
1538 Register DstLoReg, DstHiReg;
1539 Register DstReg = MI.getOperand(0).getReg();
1540 bool DstIsDead = MI.getOperand(0).isDead();
1541 bool DstIsKill = MI.getOperand(1).isKill();
1542 bool ImpIsDead = MI.getOperand(2).isDead();
1543 unsigned OpLo = AVR::RORRd;
1544 unsigned OpHi = AVR::LSRRd;
1545 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1546
1547 // High part
1548 buildMI(MBB, MBBI, OpHi)
1549 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1550 .addReg(DstHiReg, getKillRegState(DstIsKill));
1551
1552 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1553 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1554 .addReg(DstLoReg, getKillRegState(DstIsKill));
1555
1556 if (ImpIsDead)
1557 MIBLO->getOperand(2).setIsDead();
1558
1559 // SREG is always implicitly killed
1560 MIBLO->getOperand(3).setIsKill();
1561
1562 MI.eraseFromParent();
1563 return true;
1564 }
1565
1566 template <>
expand(Block & MBB,BlockIt MBBI)1567 bool AVRExpandPseudo::expand<AVR::LSRW4Rd>(Block &MBB, BlockIt MBBI) {
1568 MachineInstr &MI = *MBBI;
1569 Register DstLoReg, DstHiReg;
1570 Register DstReg = MI.getOperand(0).getReg();
1571 bool DstIsDead = MI.getOperand(0).isDead();
1572 bool DstIsKill = MI.getOperand(1).isKill();
1573 bool ImpIsDead = MI.getOperand(2).isDead();
1574 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1575
1576 // swap Rh
1577 // swap Rl
1578 buildMI(MBB, MBBI, AVR::SWAPRd)
1579 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1580 .addReg(DstHiReg, getKillRegState(DstIsKill));
1581 buildMI(MBB, MBBI, AVR::SWAPRd)
1582 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1583 .addReg(DstLoReg, getKillRegState(DstIsKill));
1584
1585 // andi Rl, 0xf
1586 auto MI0 =
1587 buildMI(MBB, MBBI, AVR::ANDIRdK)
1588 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1589 .addReg(DstLoReg, getKillRegState(DstIsKill))
1590 .addImm(0xf);
1591 // SREG is implicitly dead.
1592 MI0->getOperand(3).setIsDead();
1593
1594 // eor Rl, Rh
1595 auto MI1 =
1596 buildMI(MBB, MBBI, AVR::EORRdRr)
1597 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1598 .addReg(DstLoReg, getKillRegState(DstIsKill))
1599 .addReg(DstHiReg);
1600 // SREG is implicitly dead.
1601 MI1->getOperand(3).setIsDead();
1602
1603 // andi Rh, 0xf
1604 auto MI2 =
1605 buildMI(MBB, MBBI, AVR::ANDIRdK)
1606 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1607 .addReg(DstHiReg, getKillRegState(DstIsKill))
1608 .addImm(0xf);
1609 // SREG is implicitly dead.
1610 MI2->getOperand(3).setIsDead();
1611
1612 // eor Rl, Rh
1613 auto MI3 =
1614 buildMI(MBB, MBBI, AVR::EORRdRr)
1615 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1616 .addReg(DstLoReg, getKillRegState(DstIsKill))
1617 .addReg(DstHiReg);
1618 if (ImpIsDead)
1619 MI3->getOperand(3).setIsDead();
1620
1621 MI.eraseFromParent();
1622 return true;
1623 }
1624
1625 template <>
expand(Block & MBB,BlockIt MBBI)1626 bool AVRExpandPseudo::expand<AVR::LSRW8Rd>(Block &MBB, BlockIt MBBI) {
1627 MachineInstr &MI = *MBBI;
1628 Register DstLoReg, DstHiReg;
1629 Register DstReg = MI.getOperand(0).getReg();
1630 bool DstIsDead = MI.getOperand(0).isDead();
1631 bool DstIsKill = MI.getOperand(1).isKill();
1632 bool ImpIsDead = MI.getOperand(2).isDead();
1633 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1634
1635 // Move upper byte to lower byte.
1636 buildMI(MBB, MBBI, AVR::MOVRdRr)
1637 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1638 .addReg(DstHiReg);
1639
1640 // Clear upper byte.
1641 auto MIBHI =
1642 buildMI(MBB, MBBI, AVR::EORRdRr)
1643 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1644 .addReg(DstHiReg, getKillRegState(DstIsKill))
1645 .addReg(DstHiReg, getKillRegState(DstIsKill));
1646 if (ImpIsDead)
1647 MIBHI->getOperand(3).setIsDead();
1648
1649 MI.eraseFromParent();
1650 return true;
1651 }
1652
1653 template <>
expand(Block & MBB,BlockIt MBBI)1654 bool AVRExpandPseudo::expand<AVR::LSRW12Rd>(Block &MBB, BlockIt MBBI) {
1655 MachineInstr &MI = *MBBI;
1656 Register DstLoReg, DstHiReg;
1657 Register DstReg = MI.getOperand(0).getReg();
1658 bool DstIsDead = MI.getOperand(0).isDead();
1659 bool DstIsKill = MI.getOperand(1).isKill();
1660 bool ImpIsDead = MI.getOperand(2).isDead();
1661 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1662
1663 // Move upper byte to lower byte.
1664 buildMI(MBB, MBBI, AVR::MOVRdRr)
1665 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1666 .addReg(DstHiReg);
1667
1668 // swap Rl
1669 buildMI(MBB, MBBI, AVR::SWAPRd)
1670 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1671 .addReg(DstLoReg, getKillRegState(DstIsKill));
1672
1673 // andi Rl, 0xf
1674 auto MI0 =
1675 buildMI(MBB, MBBI, AVR::ANDIRdK)
1676 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1677 .addReg(DstLoReg, getKillRegState(DstIsKill))
1678 .addImm(0xf);
1679 // SREG is implicitly dead.
1680 MI0->getOperand(3).setIsDead();
1681
1682 // Clear upper byte.
1683 auto MIBHI =
1684 buildMI(MBB, MBBI, AVR::EORRdRr)
1685 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1686 .addReg(DstHiReg, getKillRegState(DstIsKill))
1687 .addReg(DstHiReg, getKillRegState(DstIsKill));
1688 if (ImpIsDead)
1689 MIBHI->getOperand(3).setIsDead();
1690
1691 MI.eraseFromParent();
1692 return true;
1693 }
1694
1695 template <>
expand(Block & MBB,BlockIt MBBI)1696 bool AVRExpandPseudo::expand<AVR::RORWRd>(Block &MBB, BlockIt MBBI) {
1697 llvm_unreachable("RORW unimplemented");
1698 return false;
1699 }
1700
1701 template <>
expand(Block & MBB,BlockIt MBBI)1702 bool AVRExpandPseudo::expand<AVR::ROLWRd>(Block &MBB, BlockIt MBBI) {
1703 llvm_unreachable("ROLW unimplemented");
1704 return false;
1705 }
1706
1707 template <>
expand(Block & MBB,BlockIt MBBI)1708 bool AVRExpandPseudo::expand<AVR::ASRWRd>(Block &MBB, BlockIt MBBI) {
1709 MachineInstr &MI = *MBBI;
1710 Register DstLoReg, DstHiReg;
1711 Register DstReg = MI.getOperand(0).getReg();
1712 bool DstIsDead = MI.getOperand(0).isDead();
1713 bool DstIsKill = MI.getOperand(1).isKill();
1714 bool ImpIsDead = MI.getOperand(2).isDead();
1715 unsigned OpLo = AVR::RORRd;
1716 unsigned OpHi = AVR::ASRRd;
1717 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1718
1719 // High part
1720 buildMI(MBB, MBBI, OpHi)
1721 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1722 .addReg(DstHiReg, getKillRegState(DstIsKill));
1723
1724 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1725 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1726 .addReg(DstLoReg, getKillRegState(DstIsKill));
1727
1728 if (ImpIsDead)
1729 MIBLO->getOperand(2).setIsDead();
1730
1731 // SREG is always implicitly killed
1732 MIBLO->getOperand(3).setIsKill();
1733
1734 MI.eraseFromParent();
1735 return true;
1736 }
1737
1738 template <>
expand(Block & MBB,BlockIt MBBI)1739 bool AVRExpandPseudo::expand<AVR::ASRW8Rd>(Block &MBB, BlockIt MBBI) {
1740 MachineInstr &MI = *MBBI;
1741 Register DstLoReg, DstHiReg;
1742 Register DstReg = MI.getOperand(0).getReg();
1743 bool DstIsDead = MI.getOperand(0).isDead();
1744 bool DstIsKill = MI.getOperand(1).isKill();
1745 bool ImpIsDead = MI.getOperand(2).isDead();
1746 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1747
1748 // Move upper byte to lower byte.
1749 buildMI(MBB, MBBI, AVR::MOVRdRr)
1750 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1751 .addReg(DstHiReg);
1752
1753 // Move the sign bit to the C flag.
1754 buildMI(MBB, MBBI, AVR::ADDRdRr)
1755 .addReg(DstHiReg, RegState::Define, getDeadRegState(DstIsDead))
1756 .addReg(DstHiReg, getKillRegState(DstIsKill) | getDeadRegState(DstIsDead))
1757 .addReg(DstHiReg, getKillRegState(DstIsKill));
1758
1759 // Set upper byte to 0 or -1.
1760 auto MIBHI =
1761 buildMI(MBB, MBBI, AVR::SBCRdRr)
1762 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1763 .addReg(DstHiReg, getKillRegState(DstIsKill))
1764 .addReg(DstHiReg, getKillRegState(DstIsKill));
1765 if (ImpIsDead)
1766 MIBHI->getOperand(3).setIsDead();
1767
1768 MI.eraseFromParent();
1769 return true;
1770 }
1771
1772 template <>
expand(Block & MBB,BlockIt MBBI)1773 bool AVRExpandPseudo::expand<AVR::LSLB7Rd>(Block &MBB, BlockIt MBBI) {
1774 MachineInstr &MI = *MBBI;
1775 Register DstReg = MI.getOperand(0).getReg();
1776 bool DstIsDead = MI.getOperand(0).isDead();
1777 bool DstIsKill = MI.getOperand(1).isKill();
1778 bool ImpIsDead = MI.getOperand(2).isDead();
1779
1780 // ror r24
1781 // clr r24
1782 // ror r24
1783
1784 buildMI(MBB, MBBI, AVR::RORRd)
1785 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1786 .addReg(DstReg, getKillRegState(DstIsKill))
1787 ->getOperand(3).setIsUndef(true);
1788
1789 buildMI(MBB, MBBI, AVR::EORRdRr)
1790 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1791 .addReg(DstReg, getKillRegState(DstIsKill))
1792 .addReg(DstReg, getKillRegState(DstIsKill));
1793
1794 auto MIRRC =
1795 buildMI(MBB, MBBI, AVR::RORRd)
1796 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1797 .addReg(DstReg, getKillRegState(DstIsKill));
1798
1799 if (ImpIsDead)
1800 MIRRC->getOperand(2).setIsDead();
1801
1802 // SREG is always implicitly killed
1803 MIRRC->getOperand(3).setIsKill();
1804
1805 MI.eraseFromParent();
1806 return true;
1807 }
1808
1809 template <>
expand(Block & MBB,BlockIt MBBI)1810 bool AVRExpandPseudo::expand<AVR::LSRB7Rd>(Block &MBB, BlockIt MBBI) {
1811 MachineInstr &MI = *MBBI;
1812 Register DstReg = MI.getOperand(0).getReg();
1813 bool DstIsDead = MI.getOperand(0).isDead();
1814 bool DstIsKill = MI.getOperand(1).isKill();
1815 bool ImpIsDead = MI.getOperand(2).isDead();
1816
1817 // rol r24
1818 // clr r24
1819 // rol r24
1820
1821 buildMI(MBB, MBBI, AVR::ADCRdRr)
1822 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1823 .addReg(DstReg, getKillRegState(DstIsKill))
1824 .addReg(DstReg, getKillRegState(DstIsKill))
1825 ->getOperand(4).setIsUndef(true);
1826
1827 buildMI(MBB, MBBI, AVR::EORRdRr)
1828 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1829 .addReg(DstReg, getKillRegState(DstIsKill))
1830 .addReg(DstReg, getKillRegState(DstIsKill));
1831
1832 auto MIRRC =
1833 buildMI(MBB, MBBI, AVR::ADCRdRr)
1834 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1835 .addReg(DstReg, getKillRegState(DstIsKill))
1836 .addReg(DstReg, getKillRegState(DstIsKill));
1837
1838 if (ImpIsDead)
1839 MIRRC->getOperand(3).setIsDead();
1840
1841 // SREG is always implicitly killed
1842 MIRRC->getOperand(4).setIsKill();
1843
1844 MI.eraseFromParent();
1845 return true;
1846 }
1847
1848 template <>
expand(Block & MBB,BlockIt MBBI)1849 bool AVRExpandPseudo::expand<AVR::ASRB7Rd>(Block &MBB, BlockIt MBBI) {
1850 MachineInstr &MI = *MBBI;
1851 Register DstReg = MI.getOperand(0).getReg();
1852 bool DstIsDead = MI.getOperand(0).isDead();
1853 bool DstIsKill = MI.getOperand(1).isKill();
1854 bool ImpIsDead = MI.getOperand(2).isDead();
1855
1856 // lsl r24
1857 // sbc r24, r24
1858
1859 buildMI(MBB, MBBI, AVR::ADDRdRr)
1860 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1861 .addReg(DstReg, getKillRegState(DstIsKill))
1862 .addReg(DstReg, getKillRegState(DstIsKill));
1863
1864 auto MIRRC = buildMI(MBB, MBBI, AVR::SBCRdRr)
1865 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1866 .addReg(DstReg, getKillRegState(DstIsKill))
1867 .addReg(DstReg, getKillRegState(DstIsKill));
1868
1869 if (ImpIsDead)
1870 MIRRC->getOperand(3).setIsDead();
1871
1872 // SREG is always implicitly killed
1873 MIRRC->getOperand(4).setIsKill();
1874
1875 MI.eraseFromParent();
1876 return true;
1877 }
1878
expand(Block & MBB,BlockIt MBBI)1879 template <> bool AVRExpandPseudo::expand<AVR::SEXT>(Block &MBB, BlockIt MBBI) {
1880 MachineInstr &MI = *MBBI;
1881 Register DstLoReg, DstHiReg;
1882 // sext R17:R16, R17
1883 // mov r16, r17
1884 // lsl r17
1885 // sbc r17, r17
1886 // sext R17:R16, R13
1887 // mov r16, r13
1888 // mov r17, r13
1889 // lsl r17
1890 // sbc r17, r17
1891 // sext R17:R16, R16
1892 // mov r17, r16
1893 // lsl r17
1894 // sbc r17, r17
1895 Register DstReg = MI.getOperand(0).getReg();
1896 Register SrcReg = MI.getOperand(1).getReg();
1897 bool DstIsDead = MI.getOperand(0).isDead();
1898 bool SrcIsKill = MI.getOperand(1).isKill();
1899 bool ImpIsDead = MI.getOperand(2).isDead();
1900 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1901
1902 if (SrcReg != DstLoReg) {
1903 auto MOV = buildMI(MBB, MBBI, AVR::MOVRdRr)
1904 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1905 .addReg(SrcReg);
1906
1907 if (SrcReg == DstHiReg) {
1908 MOV->getOperand(1).setIsKill();
1909 }
1910 }
1911
1912 if (SrcReg != DstHiReg) {
1913 buildMI(MBB, MBBI, AVR::MOVRdRr)
1914 .addReg(DstHiReg, RegState::Define)
1915 .addReg(SrcReg, getKillRegState(SrcIsKill));
1916 }
1917
1918 buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rr
1919 .addReg(DstHiReg, RegState::Define)
1920 .addReg(DstHiReg)
1921 .addReg(DstHiReg, RegState::Kill);
1922
1923 auto SBC = buildMI(MBB, MBBI, AVR::SBCRdRr)
1924 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1925 .addReg(DstHiReg, RegState::Kill)
1926 .addReg(DstHiReg, RegState::Kill);
1927
1928 if (ImpIsDead)
1929 SBC->getOperand(3).setIsDead();
1930
1931 // SREG is always implicitly killed
1932 SBC->getOperand(4).setIsKill();
1933
1934 MI.eraseFromParent();
1935 return true;
1936 }
1937
expand(Block & MBB,BlockIt MBBI)1938 template <> bool AVRExpandPseudo::expand<AVR::ZEXT>(Block &MBB, BlockIt MBBI) {
1939 MachineInstr &MI = *MBBI;
1940 Register DstLoReg, DstHiReg;
1941 // zext R25:R24, R20
1942 // mov R24, R20
1943 // eor R25, R25
1944 // zext R25:R24, R24
1945 // eor R25, R25
1946 // zext R25:R24, R25
1947 // mov R24, R25
1948 // eor R25, R25
1949 Register DstReg = MI.getOperand(0).getReg();
1950 Register SrcReg = MI.getOperand(1).getReg();
1951 bool DstIsDead = MI.getOperand(0).isDead();
1952 bool SrcIsKill = MI.getOperand(1).isKill();
1953 bool ImpIsDead = MI.getOperand(2).isDead();
1954 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1955
1956 if (SrcReg != DstLoReg) {
1957 buildMI(MBB, MBBI, AVR::MOVRdRr)
1958 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1959 .addReg(SrcReg, getKillRegState(SrcIsKill));
1960 }
1961
1962 auto EOR = buildMI(MBB, MBBI, AVR::EORRdRr)
1963 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1964 .addReg(DstHiReg, RegState::Kill | RegState::Undef)
1965 .addReg(DstHiReg, RegState::Kill | RegState::Undef);
1966
1967 if (ImpIsDead)
1968 EOR->getOperand(3).setIsDead();
1969
1970 MI.eraseFromParent();
1971 return true;
1972 }
1973
1974 template <>
expand(Block & MBB,BlockIt MBBI)1975 bool AVRExpandPseudo::expand<AVR::SPREAD>(Block &MBB, BlockIt MBBI) {
1976 MachineInstr &MI = *MBBI;
1977 Register DstLoReg, DstHiReg;
1978 Register DstReg = MI.getOperand(0).getReg();
1979 bool DstIsDead = MI.getOperand(0).isDead();
1980 unsigned Flags = MI.getFlags();
1981 unsigned OpLo = AVR::INRdA;
1982 unsigned OpHi = AVR::INRdA;
1983 TRI->splitReg(DstReg, DstLoReg, DstHiReg);
1984
1985 // Low part
1986 buildMI(MBB, MBBI, OpLo)
1987 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1988 .addImm(0x3d)
1989 .setMIFlags(Flags);
1990
1991 // High part
1992 buildMI(MBB, MBBI, OpHi)
1993 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1994 .addImm(0x3e)
1995 .setMIFlags(Flags);
1996
1997 MI.eraseFromParent();
1998 return true;
1999 }
2000
2001 template <>
expand(Block & MBB,BlockIt MBBI)2002 bool AVRExpandPseudo::expand<AVR::SPWRITE>(Block &MBB, BlockIt MBBI) {
2003 MachineInstr &MI = *MBBI;
2004 Register SrcLoReg, SrcHiReg;
2005 Register SrcReg = MI.getOperand(1).getReg();
2006 bool SrcIsKill = MI.getOperand(1).isKill();
2007 unsigned Flags = MI.getFlags();
2008 TRI->splitReg(SrcReg, SrcLoReg, SrcHiReg);
2009
2010 buildMI(MBB, MBBI, AVR::INRdA)
2011 .addReg(AVR::R0, RegState::Define)
2012 .addImm(SREG_ADDR)
2013 .setMIFlags(Flags);
2014
2015 buildMI(MBB, MBBI, AVR::BCLRs).addImm(0x07).setMIFlags(Flags);
2016
2017 buildMI(MBB, MBBI, AVR::OUTARr)
2018 .addImm(0x3e)
2019 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
2020 .setMIFlags(Flags);
2021
2022 buildMI(MBB, MBBI, AVR::OUTARr)
2023 .addImm(SREG_ADDR)
2024 .addReg(AVR::R0, RegState::Kill)
2025 .setMIFlags(Flags);
2026
2027 buildMI(MBB, MBBI, AVR::OUTARr)
2028 .addImm(0x3d)
2029 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
2030 .setMIFlags(Flags);
2031
2032 MI.eraseFromParent();
2033 return true;
2034 }
2035
expandMI(Block & MBB,BlockIt MBBI)2036 bool AVRExpandPseudo::expandMI(Block &MBB, BlockIt MBBI) {
2037 MachineInstr &MI = *MBBI;
2038 int Opcode = MBBI->getOpcode();
2039
2040 #define EXPAND(Op) \
2041 case Op: \
2042 return expand<Op>(MBB, MI)
2043
2044 switch (Opcode) {
2045 EXPAND(AVR::ADDWRdRr);
2046 EXPAND(AVR::ADCWRdRr);
2047 EXPAND(AVR::SUBWRdRr);
2048 EXPAND(AVR::SUBIWRdK);
2049 EXPAND(AVR::SBCWRdRr);
2050 EXPAND(AVR::SBCIWRdK);
2051 EXPAND(AVR::ANDWRdRr);
2052 EXPAND(AVR::ANDIWRdK);
2053 EXPAND(AVR::ORWRdRr);
2054 EXPAND(AVR::ORIWRdK);
2055 EXPAND(AVR::EORWRdRr);
2056 EXPAND(AVR::COMWRd);
2057 EXPAND(AVR::NEGWRd);
2058 EXPAND(AVR::CPWRdRr);
2059 EXPAND(AVR::CPCWRdRr);
2060 EXPAND(AVR::LDIWRdK);
2061 EXPAND(AVR::LDSWRdK);
2062 EXPAND(AVR::LDWRdPtr);
2063 EXPAND(AVR::LDWRdPtrPi);
2064 EXPAND(AVR::LDWRdPtrPd);
2065 case AVR::LDDWRdYQ: //:FIXME: remove this once PR13375 gets fixed
2066 EXPAND(AVR::LDDWRdPtrQ);
2067 EXPAND(AVR::LPMWRdZ);
2068 EXPAND(AVR::LPMWRdZPi);
2069 EXPAND(AVR::AtomicLoad8);
2070 EXPAND(AVR::AtomicLoad16);
2071 EXPAND(AVR::AtomicStore8);
2072 EXPAND(AVR::AtomicStore16);
2073 EXPAND(AVR::AtomicLoadAdd8);
2074 EXPAND(AVR::AtomicLoadAdd16);
2075 EXPAND(AVR::AtomicLoadSub8);
2076 EXPAND(AVR::AtomicLoadSub16);
2077 EXPAND(AVR::AtomicLoadAnd8);
2078 EXPAND(AVR::AtomicLoadAnd16);
2079 EXPAND(AVR::AtomicLoadOr8);
2080 EXPAND(AVR::AtomicLoadOr16);
2081 EXPAND(AVR::AtomicLoadXor8);
2082 EXPAND(AVR::AtomicLoadXor16);
2083 EXPAND(AVR::AtomicFence);
2084 EXPAND(AVR::STSWKRr);
2085 EXPAND(AVR::STWPtrRr);
2086 EXPAND(AVR::STWPtrPiRr);
2087 EXPAND(AVR::STWPtrPdRr);
2088 EXPAND(AVR::STDWPtrQRr);
2089 EXPAND(AVR::INWRdA);
2090 EXPAND(AVR::OUTWARr);
2091 EXPAND(AVR::PUSHWRr);
2092 EXPAND(AVR::POPWRd);
2093 EXPAND(AVR::ROLBRd);
2094 EXPAND(AVR::RORBRd);
2095 EXPAND(AVR::LSLWRd);
2096 EXPAND(AVR::LSLW4Rd);
2097 EXPAND(AVR::LSLW8Rd);
2098 EXPAND(AVR::LSLW12Rd);
2099 EXPAND(AVR::LSRWRd);
2100 EXPAND(AVR::LSRW4Rd);
2101 EXPAND(AVR::LSRW8Rd);
2102 EXPAND(AVR::LSRW12Rd);
2103 EXPAND(AVR::RORWRd);
2104 EXPAND(AVR::ROLWRd);
2105 EXPAND(AVR::ASRWRd);
2106 EXPAND(AVR::ASRW8Rd);
2107 EXPAND(AVR::LSLB7Rd);
2108 EXPAND(AVR::LSRB7Rd);
2109 EXPAND(AVR::ASRB7Rd);
2110 EXPAND(AVR::SEXT);
2111 EXPAND(AVR::ZEXT);
2112 EXPAND(AVR::SPREAD);
2113 EXPAND(AVR::SPWRITE);
2114 }
2115 #undef EXPAND
2116 return false;
2117 }
2118
2119 } // end of anonymous namespace
2120
2121 INITIALIZE_PASS(AVRExpandPseudo, "avr-expand-pseudo",
2122 AVR_EXPAND_PSEUDO_NAME, false, false)
2123 namespace llvm {
2124
createAVRExpandPseudoPass()2125 FunctionPass *createAVRExpandPseudoPass() { return new AVRExpandPseudo(); }
2126
2127 } // end of namespace llvm
2128