1 /* $NetBSD: coram.c,v 1.20 2021/08/07 16:19:14 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: coram.c,v 1.20 2021/08/07 16:19:14 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/device.h>
35 #include <sys/kmem.h>
36 #include <sys/mutex.h>
37 #include <sys/module.h>
38 #include <sys/bus.h>
39
40 #include <dev/dtv/dtvif.h>
41
42 #include <dev/pci/cx23885reg.h>
43 #include <dev/pci/coramvar.h>
44
45 #include <dev/pci/pcivar.h>
46 #include <dev/pci/pcireg.h>
47 #include <dev/pci/pcidevs.h>
48 #include <dev/i2c/i2cvar.h>
49 #include <dev/i2c/at24cxxvar.h>
50
51 #include <dev/i2c/cx24227var.h>
52 #include <dev/i2c/mt2131var.h>
53
54 /* #define CORAM_DEBUG */
55 /* #define CORAM_ATTACH_I2C */
56
57 static const struct coram_board coram_boards[] = {
58 { PCI_VENDOR_HAUPPAUGE, 0x7911, "Hauppauge HVR-1250" },
59 };
60
61 static int coram_match(device_t, cfdata_t, void *);
62 static void coram_attach(device_t, device_t, void *);
63 static int coram_detach(device_t, int);
64 static int coram_rescan(device_t, const char *, const int *);
65 static void coram_childdet(device_t, device_t);
66 static bool coram_resume(device_t, const pmf_qual_t *);
67 static int coram_intr(void *);
68 static const struct coram_board * coram_board_lookup(uint16_t, uint16_t);
69
70 static int coram_iic_exec(void *, i2c_op_t, i2c_addr_t,
71 const void *, size_t, void *, size_t, int);
72 static int coram_iic_read(struct coram_iic_softc *, i2c_op_t, i2c_addr_t,
73 const void *, size_t, void *, size_t, int);
74 static int coram_iic_write(struct coram_iic_softc *, i2c_op_t, i2c_addr_t,
75 const void *, size_t, void *, size_t, int);
76
77 static void coram_dtv_get_devinfo(void *, struct dvb_frontend_info *);
78 static int coram_dtv_open(void *, int);
79 static void coram_dtv_close(void *);
80 static int coram_dtv_set_tuner(void *, const struct dvb_frontend_parameters *);
81 static fe_status_t coram_dtv_get_status(void *);
82 static uint16_t coram_dtv_get_signal_strength(void *);
83 static uint16_t coram_dtv_get_snr(void *);
84 static int coram_dtv_start_transfer(void *, void (*)(void *, const struct dtv_payload *), void *);
85 static int coram_dtv_stop_transfer(void *);
86
87 static int coram_mpeg_attach(struct coram_softc *);
88 static int coram_mpeg_detach(struct coram_softc *, int);
89 static int coram_mpeg_reset(struct coram_softc *);
90 static void * coram_mpeg_malloc(struct coram_softc *, size_t);
91 static int coram_allocmem(struct coram_softc *, size_t, size_t, struct coram_dma *);
92 static void coram_mpeg_free(struct coram_softc *, void *);
93 static int coram_mpeg_halt(struct coram_softc *);
94 static int coram_freemem(struct coram_softc *, struct coram_dma *);
95 static int coram_mpeg_trigger(struct coram_softc *, void *);
96 static int coram_risc_buffer(struct coram_softc *, uint32_t, uint32_t);
97 static int coram_risc_field(struct coram_softc *, uint32_t *, uint32_t);
98 static int coram_sram_ch_setup(struct coram_softc *, struct coram_sram_ch *, uint32_t);
99 static int coram_mpeg_intr(struct coram_softc *);
100
101 CFATTACH_DECL2_NEW(coram, sizeof(struct coram_softc),
102 coram_match, coram_attach, coram_detach, NULL,
103 coram_rescan, coram_childdet);
104
105 #define CORAM_SRAM_CH6 0
106
107 #define CORAM_TS_PKTSIZE (188 * 8)
108
109 static struct coram_sram_ch coram_sram_chs[] = {
110 [CORAM_SRAM_CH6] = {
111 .csc_cmds= 0x10140,
112 .csc_iq = 0x10500,
113 .csc_iqsz = 0x40,
114 .csc_cdt = 0x10600,
115 .csc_cdtsz = 0x10,
116 .csc_fifo = 0x6000,
117 .csc_fifosz = 0x1000,
118 .csc_risc = 0x10800,
119 .csc_riscsz = 0x800,
120 .csc_ptr1 = DMA5_PTR1,
121 .csc_ptr2 = DMA5_PTR2,
122 .csc_cnt1 = DMA5_CNT1,
123 .csc_cnt2 = DMA5_CNT2,
124 },
125 };
126
127 static const struct dtv_hw_if coram_dtv_if = {
128 .get_devinfo = coram_dtv_get_devinfo,
129 .open = coram_dtv_open,
130 .close = coram_dtv_close,
131 .set_tuner = coram_dtv_set_tuner,
132 .get_status = coram_dtv_get_status,
133 .get_signal_strength = coram_dtv_get_signal_strength,
134 .get_snr = coram_dtv_get_snr,
135 .start_transfer = coram_dtv_start_transfer,
136 .stop_transfer = coram_dtv_stop_transfer,
137 };
138
139 static int
coram_match(device_t parent,cfdata_t match,void * v)140 coram_match(device_t parent, cfdata_t match, void *v)
141 {
142 const struct pci_attach_args *pa = v;
143 pcireg_t subid;
144
145 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_CONEXANT)
146 return 0;
147 if (PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_CONEXANT_CX23885)
148 return 0;
149
150 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
151 if (coram_board_lookup(PCI_VENDOR(subid), PCI_PRODUCT(subid)) == NULL)
152 return 0;
153
154 return 1;
155 }
156
157 static void
coram_attach(device_t parent,device_t self,void * aux)158 coram_attach(device_t parent, device_t self, void *aux)
159 {
160 struct coram_softc *sc = device_private(self);
161 const struct pci_attach_args *pa = aux;
162 pci_intr_handle_t ih;
163 pcireg_t reg;
164 const char *intrstr;
165 struct coram_iic_softc *cic;
166 uint32_t value;
167 int i;
168 #ifdef CORAM_ATTACH_I2C
169 struct i2cbus_attach_args iba;
170 #endif
171 char intrbuf[PCI_INTRSTR_LEN];
172
173 sc->sc_dev = self;
174
175 pci_aprint_devinfo(pa, NULL);
176
177 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
178 sc->sc_board = coram_board_lookup(PCI_VENDOR(reg), PCI_PRODUCT(reg));
179 KASSERT(sc->sc_board != NULL);
180
181 if (pci_mapreg_map(pa, CX23885_MMBASE, PCI_MAPREG_TYPE_MEM, 0,
182 &sc->sc_memt, &sc->sc_memh, NULL, &sc->sc_mems)) {
183 aprint_error_dev(self, "couldn't map memory space\n");
184 return;
185 }
186
187 sc->sc_dmat = pa->pa_dmat;
188 sc->sc_pc = pa->pa_pc;
189
190 if (pci_intr_map(pa, &ih)) {
191 aprint_error_dev(self, "couldn't map interrupt\n");
192 return;
193 }
194 intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf));
195 sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_VM, coram_intr,
196 self, device_xname(self));
197 if (sc->sc_ih == NULL) {
198 aprint_error_dev(self, "couldn't establish interrupt");
199 if (intrstr != NULL)
200 aprint_error(" at %s", intrstr);
201 aprint_error("\n");
202 return;
203 }
204 aprint_normal_dev(self, "interrupting at %s\n", intrstr);
205
206 /* set master */
207 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
208 reg |= PCI_COMMAND_MASTER_ENABLE;
209 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, reg);
210
211 /* I2C */
212 for(i = 0; i < I2C_NUM; i++) {
213 cic = &sc->sc_iic[i];
214
215 cic->cic_sc = sc;
216 if (bus_space_subregion(sc->sc_memt, sc->sc_memh,
217 I2C_BASE + (I2C_SIZE * i), I2C_SIZE, &cic->cic_regh))
218 panic("failed to subregion i2c");
219
220 iic_tag_init(&cic->cic_i2c);
221 cic->cic_i2c.ic_cookie = cic;
222 cic->cic_i2c.ic_exec = coram_iic_exec;
223
224 #ifdef CORAM_ATTACH_I2C
225 /* attach iic(4) */
226 memset(&iba, 0, sizeof(iba));
227 iba.iba_tag = &cic->cic_i2c;
228 cic->cic_i2cdev = config_found(self, &iba, iicbus_print,
229 CFARGS(.iattr = "i2cbus"));
230 #endif
231 }
232
233 /* HVR1250 GPIO */
234 value = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x110010);
235 #if 1
236 value &= ~0x00010001;
237 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value);
238 delay(5000);
239 #endif
240 value |= 0x00010001;
241 bus_space_write_4(sc->sc_memt, sc->sc_memh, 0x110010, value);
242
243 #if 0
244 int i;
245 uint8_t foo[256];
246 uint8_t bar;
247 bar = 0;
248 // seeprom_bootstrap_read(&sc->sc_i2c, 0x50, 0, 256, foo, 256);
249
250 iic_acquire_bus(&sc->sc_i2c, 0);
251 iic_exec(&sc->sc_i2c, I2C_OP_READ_WITH_STOP, 0x50, &bar, 1, foo, 256,
252 0);
253 iic_release_bus(&sc->sc_i2c, 0);
254
255 printf("\n");
256 for ( i = 0; i < 256; i++) {
257 if ( (i % 8) == 0 )
258 printf("%02x: ", i);
259
260 printf("%02x", foo[i]);
261
262 if ( (i % 8) == 7 )
263 printf("\n");
264 else
265 printf(" ");
266 }
267 printf("\n");
268 #endif
269
270 sc->sc_demod = cx24227_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x19);
271 if (sc->sc_demod == NULL)
272 aprint_error_dev(self, "couldn't open cx24227\n");
273 sc->sc_tuner = mt2131_open(sc->sc_dev, &sc->sc_iic[0].cic_i2c, 0x61);
274 if (sc->sc_tuner == NULL)
275 aprint_error_dev(self, "couldn't open mt2131\n");
276
277 coram_mpeg_attach(sc);
278
279 if (!pmf_device_register(self, NULL, coram_resume))
280 aprint_error_dev(self, "couldn't establish power handler\n");
281
282 return;
283 }
284
285 static int
coram_detach(device_t self,int flags)286 coram_detach(device_t self, int flags)
287 {
288 struct coram_softc *sc = device_private(self);
289 struct coram_iic_softc *cic;
290 unsigned int i;
291 int error;
292
293 error = coram_mpeg_detach(sc, flags);
294 if (error)
295 return error;
296
297 if (sc->sc_tuner)
298 mt2131_close(sc->sc_tuner);
299 if (sc->sc_demod)
300 cx24227_close(sc->sc_demod);
301 for (i = 0; i < I2C_NUM; i++) {
302 cic = &sc->sc_iic[i];
303 if (cic->cic_i2cdev)
304 config_detach(cic->cic_i2cdev, flags);
305 iic_tag_fini(&cic->cic_i2c);
306 }
307 pmf_device_deregister(self);
308
309 if (sc->sc_mems)
310 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mems);
311 if (sc->sc_ih)
312 pci_intr_disestablish(sc->sc_pc, sc->sc_ih);
313
314 return 0;
315 }
316
317 static int
coram_rescan(device_t self,const char * ifattr,const int * locs)318 coram_rescan(device_t self, const char *ifattr, const int *locs)
319 {
320 struct coram_softc *sc = device_private(self);
321 struct dtv_attach_args daa;
322
323 daa.hw = &coram_dtv_if;
324 daa.priv = sc;
325
326 if (ifattr_match(ifattr, "dtvbus") && sc->sc_dtvdev == NULL)
327 sc->sc_dtvdev = config_found(sc->sc_dev, &daa, dtv_print,
328 CFARGS(.iattr = "dtvbus"));
329
330 return 0;
331 }
332
333 static void
coram_childdet(device_t self,device_t child)334 coram_childdet(device_t self, device_t child)
335 {
336 struct coram_softc *sc = device_private(self);
337 struct coram_iic_softc *cic;
338 unsigned int i;
339
340 if (sc->sc_dtvdev == child)
341 sc->sc_dtvdev = NULL;
342
343 for (i = 0; i < I2C_NUM; i++) {
344 cic = &sc->sc_iic[i];
345 if (cic->cic_i2cdev == child)
346 cic->cic_i2cdev = NULL;
347 }
348 }
349
350 static int
coram_intr(void * v)351 coram_intr(void *v)
352 {
353 device_t self = v;
354 struct coram_softc *sc;
355 uint32_t val;
356
357 sc = device_private(self);
358
359 val = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSTAT );
360 if (val == 0)
361 return 0; /* not ours */
362
363 /* vid c */
364 if (val & __BIT(2))
365 coram_mpeg_intr(sc);
366
367 if (val & ~__BIT(2))
368 printf("%s %08x\n", __func__, val);
369
370 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, val);
371
372 return 1;
373 }
374
375 static const struct coram_board *
coram_board_lookup(uint16_t vendor,uint16_t product)376 coram_board_lookup(uint16_t vendor, uint16_t product)
377 {
378 unsigned int i;
379
380 for (i = 0; i < __arraycount(coram_boards); i++) {
381 if (coram_boards[i].vendor == vendor &&
382 coram_boards[i].product == product) {
383 return &coram_boards[i];
384 }
385 }
386
387 return NULL;
388 }
389
390 #define CXDTV_TS_RISCI2 (1 << 4)
391 #define CXDTV_TS_RISCI1 (1 << 0)
392
393 #define CXDTV_TS_RISCI (CXDTV_TS_RISCI1|CXDTV_TS_RISCI2)
394
395 static int
coram_mpeg_intr(struct coram_softc * sc)396 coram_mpeg_intr(struct coram_softc *sc)
397 {
398 struct dtv_payload payload;
399 uint32_t s, m, v;
400 int i;
401
402 s = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT);
403 m = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK);
404
405 if ((s & m) == 0)
406 return 0;
407
408 if ( (s & ~CXDTV_TS_RISCI) != 0 ) {
409 printf("%s: unexpected TS IS %08x\n",
410 device_xname(sc->sc_dev), s);
411
412 printf("cmds:\n");
413 for(i = 0; i < 20; i++)
414 {
415 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, 0x10140 +(i*4));
416 printf("%06x %08x\n", 0x10140+(i*4), v);
417 }
418 }
419
420 if (sc->sc_dtvsubmitcb == NULL)
421 goto done;
422
423 if ((s & CXDTV_TS_RISCI1) == CXDTV_TS_RISCI1) {
424 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map,
425 0, CORAM_TS_PKTSIZE,
426 BUS_DMASYNC_POSTREAD);
427 payload.data = KERNADDR(sc->sc_dma);
428 payload.size = CORAM_TS_PKTSIZE;
429 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload);
430 }
431
432 if ((s & CXDTV_TS_RISCI2) == CXDTV_TS_RISCI2) {
433 bus_dmamap_sync(sc->sc_dmat, sc->sc_dma->map,
434 CORAM_TS_PKTSIZE, CORAM_TS_PKTSIZE,
435 BUS_DMASYNC_POSTREAD);
436 payload.data = (char *)(KERNADDR(sc->sc_dma)) + (uintptr_t)CORAM_TS_PKTSIZE;
437 payload.size = CORAM_TS_PKTSIZE;
438 sc->sc_dtvsubmitcb(sc->sc_dtvsubmitarg, &payload);
439 }
440
441 done:
442 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, s);
443
444 return 1;
445 }
446
447 static bool
coram_resume(device_t dv,const pmf_qual_t * qual)448 coram_resume(device_t dv, const pmf_qual_t *qual)
449 {
450 return true;
451 }
452
453 /* I2C Bus */
454
455 #define I2C_ADDR 0x0000
456 #define I2C_WDATA 0x0004
457 #define I2C_CTRL 0x0008
458 #define I2C_RDATA 0x000c
459 #define I2C_STAT 0x0010
460
461 #define I2C_EXTEND (1 << 3)
462 #define I2C_NOSTOP (1 << 4)
463
464 static int
coram_iic_exec(void * cookie,i2c_op_t op,i2c_addr_t addr,const void * cmdbuf,size_t cmdlen,void * buf,size_t len,int flags)465 coram_iic_exec(void *cookie, i2c_op_t op, i2c_addr_t addr,
466 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
467 {
468 struct coram_iic_softc *cic;
469 int ret;
470
471 cic = cookie;
472
473 if(cmdlen) {
474 ret = coram_iic_write(cic, op, addr, cmdbuf, cmdlen, buf, len, flags);
475 if(ret)
476 return ret;
477 }
478
479 if(len) {
480 ret = coram_iic_read(cic, op, addr, cmdbuf, cmdlen, buf, len, flags);
481 if(ret)
482 return ret;
483 }
484
485
486 return 0;
487
488 }
489
490 static int
coram_iic_read(struct coram_iic_softc * cic,i2c_op_t op,i2c_addr_t addr,const void * cmdbuf,size_t cmdlen,void * buf,size_t len,int flags)491 coram_iic_read(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr,
492 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
493 {
494 uint8_t *rb;
495 uint32_t ctrl;
496 int bn;
497
498 rb = buf;
499
500 for ( bn = 0; bn < len; bn++) {
501 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2) | 1;
502 if ( bn < len - 1 )
503 ctrl |= I2C_NOSTOP | I2C_EXTEND;
504
505 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addr<<25);
506 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl);
507
508 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh,
509 I2C_STAT) & 0x02)) {
510 delay(25);
511 }
512 if((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh,
513 I2C_STAT) & 0x01) == 0x00) {
514 // printf("%s %d no ack\n", __func__, bn);
515 return EIO;
516 }
517
518 rb[bn] = bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_RDATA);
519
520 }
521
522 return 0;
523 }
524
525 static int
coram_iic_write(struct coram_iic_softc * cic,i2c_op_t op,i2c_addr_t addr,const void * cmdbuf,size_t cmdlen,void * buf,size_t len,int flags)526 coram_iic_write(struct coram_iic_softc *cic, i2c_op_t op, i2c_addr_t addr,
527 const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
528 {
529 const uint8_t *wb;
530 uint32_t wdata, addrreg, ctrl;
531 int bn;
532
533 wb = cmdbuf;
534
535 addrreg = (addr << 25) | wb[0];
536 wdata = wb[0];
537 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2);
538
539 if ( cmdlen > 1 )
540 ctrl |= I2C_NOSTOP | I2C_EXTEND;
541 else if (len)
542 ctrl |= I2C_NOSTOP;
543
544 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg);
545 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata);
546 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl);
547
548 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) {
549 delay(25); }
550
551 for ( bn = 1; bn < cmdlen; bn++) {
552 ctrl = (0x9d << 24) | (1 << 12) | (1 << 2);
553 wdata = wb[bn];
554
555 if ( bn < cmdlen - 1 )
556 ctrl |= I2C_NOSTOP | I2C_EXTEND;
557 else if (len)
558 ctrl |= I2C_NOSTOP;
559
560 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_ADDR, addrreg);
561 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_WDATA, wdata);
562 bus_space_write_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_CTRL, ctrl);
563
564 while((bus_space_read_4(cic->cic_sc->sc_memt, cic->cic_regh, I2C_STAT) & 0x02)) {
565 delay(25); }
566 }
567
568 return 0;
569 }
570
571 static int
coram_mpeg_attach(struct coram_softc * sc)572 coram_mpeg_attach(struct coram_softc *sc)
573 {
574 struct coram_sram_ch *ch;
575
576 ch = &coram_sram_chs[CORAM_SRAM_CH6];
577
578 sc->sc_riscbufsz = ch->csc_riscsz;
579 sc->sc_riscbuf = kmem_alloc(ch->csc_riscsz, KM_SLEEP);
580
581 coram_mpeg_reset(sc);
582
583 sc->sc_tsbuf = NULL;
584
585 coram_rescan(sc->sc_dev, NULL, NULL);
586
587 return (sc->sc_dtvdev != NULL);
588 }
589
590 static int
coram_mpeg_detach(struct coram_softc * sc,int flags)591 coram_mpeg_detach(struct coram_softc *sc, int flags)
592 {
593 struct coram_sram_ch *ch = &coram_sram_chs[CORAM_SRAM_CH6];
594 int error;
595
596 if (sc->sc_dtvdev) {
597 error = config_detach(sc->sc_dtvdev, flags);
598 if (error)
599 return error;
600 }
601 if (sc->sc_riscbuf) {
602 kmem_free(sc->sc_riscbuf, ch->csc_riscsz);
603 }
604
605 return 0;
606 }
607
608 static void
coram_dtv_get_devinfo(void * cookie,struct dvb_frontend_info * info)609 coram_dtv_get_devinfo(void *cookie, struct dvb_frontend_info *info)
610 {
611 struct coram_softc *sc = cookie;
612
613 memset(info, 0, sizeof(*info));
614 strlcpy(info->name, sc->sc_board->name, sizeof(info->name));
615 info->type = FE_ATSC;
616 info->frequency_min = 54000000;
617 info->frequency_max = 858000000;
618 info->frequency_stepsize = 62500;
619 info->caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB;
620 }
621
622 static int
coram_dtv_open(void * cookie,int flags)623 coram_dtv_open(void *cookie, int flags)
624 {
625 struct coram_softc *sc = cookie;
626
627 #ifdef CORAM_DEBUG
628 device_printf(sc->sc_dev, "%s\n", __func__);
629 #endif
630
631 //KASSERT(sc->sc_tsbuf == NULL);
632
633 if (sc->sc_tuner == NULL || sc->sc_demod == NULL)
634 return ENXIO;
635
636 coram_mpeg_reset(sc);
637
638 /* allocate two alternating DMA areas for MPEG TS packets */
639 sc->sc_tsbuf = coram_mpeg_malloc(sc, CORAM_TS_PKTSIZE * 2);
640
641 if (sc->sc_tsbuf == NULL)
642 return ENOMEM;
643
644 return 0;
645 }
646
647 static void
coram_dtv_close(void * cookie)648 coram_dtv_close(void *cookie)
649 {
650 struct coram_softc *sc = cookie;
651
652 #ifdef CORAM_DEBUG
653 device_printf(sc->sc_dev, "%s\n", __func__);
654 #endif
655
656 coram_mpeg_halt(sc);
657
658 if (sc->sc_tsbuf != NULL) {
659 coram_mpeg_free(sc, sc->sc_tsbuf);
660 sc->sc_tsbuf = NULL;
661 }
662 }
663
664 static int
coram_dtv_set_tuner(void * cookie,const struct dvb_frontend_parameters * params)665 coram_dtv_set_tuner(void *cookie, const struct dvb_frontend_parameters *params)
666 {
667 struct coram_softc *sc = cookie;
668
669 KASSERT(sc->sc_tuner != NULL);
670 mt2131_tune_dtv(sc->sc_tuner, params);
671 KASSERT(sc->sc_demod != NULL);
672 return cx24227_set_modulation(sc->sc_demod, params->u.vsb.modulation);
673 }
674
675 static fe_status_t
coram_dtv_get_status(void * cookie)676 coram_dtv_get_status(void *cookie)
677 {
678 struct coram_softc *sc = cookie;
679
680 if (sc->sc_demod == NULL)
681 return ENXIO;
682
683 return cx24227_get_dtv_status(sc->sc_demod);
684 }
685
686 static uint16_t
coram_dtv_get_signal_strength(void * cookie)687 coram_dtv_get_signal_strength(void *cookie)
688 {
689 return 0;
690 }
691
692 static uint16_t
coram_dtv_get_snr(void * cookie)693 coram_dtv_get_snr(void *cookie)
694 {
695 return 0;
696 }
697
698 static int
coram_dtv_start_transfer(void * cookie,void (* cb)(void *,const struct dtv_payload *),void * arg)699 coram_dtv_start_transfer(void *cookie,
700 void (*cb)(void *, const struct dtv_payload *), void *arg)
701 {
702 struct coram_softc *sc = cookie;
703
704 #ifdef CORAM_DEBUG
705 device_printf(sc->sc_dev, "%s\n", __func__);
706 #endif
707
708 sc->sc_dtvsubmitcb = cb;
709 sc->sc_dtvsubmitarg = arg;
710
711 coram_mpeg_trigger(sc, sc->sc_tsbuf);
712
713 return 0;
714 }
715
716 static int
coram_dtv_stop_transfer(void * cookie)717 coram_dtv_stop_transfer(void *cookie)
718 {
719 struct coram_softc *sc = cookie;
720
721 #ifdef CORAM_DEBUG
722 device_printf(sc->sc_dev, "%s\n", __func__);
723 #endif
724
725 coram_mpeg_halt(sc);
726 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0);
727
728 sc->sc_dtvsubmitcb = NULL;
729 sc->sc_dtvsubmitarg = NULL;
730
731 return 0;
732 }
733
734
735 static int
coram_mpeg_reset(struct coram_softc * sc)736 coram_mpeg_reset(struct coram_softc *sc)
737 {
738 /* hold RISC in reset */
739 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, 0);
740
741 /* disable fifo + risc */
742 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0);
743
744 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, 0);
745 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, 0);
746
747 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_STAT, 0);
748 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_STAT, 0);
749
750 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz);
751
752 return 0;
753 }
754
755 static void *
coram_mpeg_malloc(struct coram_softc * sc,size_t size)756 coram_mpeg_malloc(struct coram_softc *sc, size_t size)
757 {
758 struct coram_dma *p;
759 int err;
760
761 p = kmem_alloc(sizeof(struct coram_dma), KM_SLEEP);
762 err = coram_allocmem(sc, size, 16, p);
763 if (err) {
764 kmem_free(p, sizeof(struct coram_dma));
765 return NULL;
766 }
767
768 p->next = sc->sc_dma;
769 sc->sc_dma = p;
770
771 return KERNADDR(p);
772 }
773
774 static int
coram_allocmem(struct coram_softc * sc,size_t size,size_t align,struct coram_dma * p)775 coram_allocmem(struct coram_softc *sc, size_t size, size_t align,
776 struct coram_dma *p)
777 {
778 int err;
779
780 p->size = size;
781 err = bus_dmamem_alloc(sc->sc_dmat, p->size, align, 0,
782 p->segs, sizeof(p->segs) / sizeof(p->segs[0]),
783 &p->nsegs, BUS_DMA_NOWAIT);
784 if (err)
785 return err;
786 err = bus_dmamem_map(sc->sc_dmat, p->segs, p->nsegs, p->size,
787 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
788 if (err)
789 goto free;
790 err = bus_dmamap_create(sc->sc_dmat, p->size, 1, p->size, 0,
791 BUS_DMA_NOWAIT, &p->map);
792 if (err)
793 goto unmap;
794 err = bus_dmamap_load(sc->sc_dmat, p->map, p->addr, p->size, NULL,
795 BUS_DMA_NOWAIT);
796 if (err)
797 goto destroy;
798
799 return 0;
800 destroy:
801 bus_dmamap_destroy(sc->sc_dmat, p->map);
802 unmap:
803 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size);
804 free:
805 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs);
806
807 return err;
808 }
809
810 static int
coram_mpeg_halt(struct coram_softc * sc)811 coram_mpeg_halt(struct coram_softc *sc)
812 {
813 uint32_t v;
814
815 #ifdef CORAM_DEBUG
816 device_printf(sc->sc_dev, "%s\n", __func__);
817 #endif
818
819 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0);
820
821 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK);
822 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK,
823 v & __BIT(2));
824
825 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK);
826 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK,
827 v & 0);
828
829 return 0;
830 }
831
832 static void
coram_mpeg_free(struct coram_softc * sc,void * addr)833 coram_mpeg_free(struct coram_softc *sc, void *addr)
834 {
835 struct coram_dma *p;
836 struct coram_dma **pp;
837
838 for (pp = &sc->sc_dma; (p = *pp) != NULL; pp = &p->next)
839 if (KERNADDR(p) == addr) {
840 coram_freemem(sc, p);
841 *pp = p->next;
842 kmem_free(p, sizeof(struct coram_dma));
843 return;
844 }
845
846 printf("%s: %p is already free\n", device_xname(sc->sc_dev), addr);
847 return;
848 }
849
850 static int
coram_freemem(struct coram_softc * sc,struct coram_dma * p)851 coram_freemem(struct coram_softc *sc, struct coram_dma *p)
852 {
853 bus_dmamap_unload(sc->sc_dmat, p->map);
854 bus_dmamap_destroy(sc->sc_dmat, p->map);
855 bus_dmamem_unmap(sc->sc_dmat, p->addr, p->size);
856 bus_dmamem_free(sc->sc_dmat, p->segs, p->nsegs);
857
858 return 0;
859 }
860
861 static int
coram_mpeg_trigger(struct coram_softc * sc,void * buf)862 coram_mpeg_trigger(struct coram_softc *sc, void *buf)
863 {
864 struct coram_dma *p;
865 struct coram_sram_ch *ch;
866 uint32_t v;
867
868 ch = &coram_sram_chs[CORAM_SRAM_CH6];
869
870 for (p = sc->sc_dma; p && KERNADDR(p) != buf; p = p->next)
871 continue;
872 if (p == NULL) {
873 printf("%s: coram_mpeg_trigger: bad addr %p\n",
874 device_xname(sc->sc_dev), buf);
875 return ENOENT;
876 }
877
878 /* disable fifo + risc */
879 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, 0);
880
881 coram_risc_buffer(sc, CORAM_TS_PKTSIZE, 1);
882 coram_sram_ch_setup(sc, ch, CORAM_TS_PKTSIZE);
883
884 /* let me hope this bit is the same as on the 2388[0-3] */
885 /* software reset */
886 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 0x0040);
887 delay (100*1000);
888
889 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_LNGTH, CORAM_TS_PKTSIZE);
890 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_HW_SOP_CTL, 0x47 << 16 | 188 << 4);
891 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_TS_CLK_EN, 1);
892 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_VLD_MISC, 0);
893 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL, 12);
894 delay (100*1000);
895
896 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PAD_CTRL);
897 v &= ~0x4; /* Clear TS2_SOP_OE */
898 bus_space_write_4(sc->sc_memt, sc->sc_memh, PAD_CTRL, v);
899
900 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK);
901 v |= 0x111111;
902 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_INT_MSK, v);
903
904 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL);
905 v |= 0x11; /* Enable RISC controller and FIFO */
906 bus_space_write_4(sc->sc_memt, sc->sc_memh, VID_C_DMA_CTL, v);
907
908 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2);
909 v |= __BIT(5); /* Enable RISC controller */
910 bus_space_write_4(sc->sc_memt, sc->sc_memh, DEV_CNTRL2, v);
911
912 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK);
913 v |= 0x001f00;
914 v |= 0x04;
915 bus_space_write_4(sc->sc_memt, sc->sc_memh, PCI_INT_MSK, v);
916
917 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL);
918 #ifdef CORAM_DEBUG
919 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v);
920 #endif
921 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS);
922 #ifdef CORAM_DEBUG
923 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v);
924 #endif
925 delay(100*1000);
926 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_GEN_CTL);
927 #ifdef CORAM_DEBUG
928 printf("%s, %06x %08x\n", __func__, VID_C_GEN_CTL, v);
929 #endif
930 v = bus_space_read_4(sc->sc_memt, sc->sc_memh, VID_C_SOP_STATUS);
931 #ifdef CORAM_DEBUG
932 printf("%s, %06x %08x\n", __func__, VID_C_SOP_STATUS, v);
933 #endif
934
935 return 0;
936 }
937
938 static int
coram_risc_buffer(struct coram_softc * sc,uint32_t bpl,uint32_t lines)939 coram_risc_buffer(struct coram_softc *sc, uint32_t bpl, uint32_t lines)
940 {
941 uint32_t *rm;
942 uint32_t size;
943
944 size = 1 + (bpl * lines) / PAGE_SIZE + lines;
945 size += 2;
946
947 if (sc->sc_riscbuf == NULL) {
948 return ENOMEM;
949 }
950
951 rm = (uint32_t *)sc->sc_riscbuf;
952 coram_risc_field(sc, rm, bpl);
953
954 return 0;
955 }
956
957 static int
coram_risc_field(struct coram_softc * sc,uint32_t * rm,uint32_t bpl)958 coram_risc_field(struct coram_softc *sc, uint32_t *rm, uint32_t bpl)
959 {
960 struct coram_dma *p;
961
962 for (p = sc->sc_dma; p && KERNADDR(p) != sc->sc_tsbuf; p = p->next)
963 continue;
964 if (p == NULL) {
965 printf("%s: coram_risc_field: bad addr %p\n",
966 device_xname(sc->sc_dev), sc->sc_tsbuf);
967 return ENOENT;
968 }
969
970 memset(sc->sc_riscbuf, 0, sc->sc_riscbufsz);
971
972 rm = sc->sc_riscbuf;
973
974 /* htole32 will be done when program is copied to chip sram */
975
976 /* XXX */
977 *(rm++) = (CX_RISC_SYNC|0);
978
979 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ1|bpl);
980 *(rm++) = (DMAADDR(p) + 0 * bpl);
981 *(rm++) = 0; /* high dword */
982
983 *(rm++) = (CX_RISC_WRITE|CX_RISC_SOL|CX_RISC_EOL|CX_RISC_IRQ2|bpl);
984 *(rm++) = (DMAADDR(p) + 1 * bpl);
985 *(rm++) = 0;
986
987 *(rm++) = (CX_RISC_JUMP|1);
988 *(rm++) = (coram_sram_chs[CORAM_SRAM_CH6].csc_risc + 4);
989 *(rm++) = 0;
990
991 return 0;
992 }
993
994 static int
coram_sram_ch_setup(struct coram_softc * sc,struct coram_sram_ch * csc,uint32_t bpl)995 coram_sram_ch_setup(struct coram_softc *sc, struct coram_sram_ch *csc,
996 uint32_t bpl)
997 {
998 unsigned int i, lines;
999 uint32_t cdt;
1000
1001 /* XXX why round? */
1002 bpl = (bpl + 7) & ~7;
1003 cdt = csc->csc_cdt;
1004 lines = csc->csc_fifosz / bpl;
1005 #ifdef CORAM_DEBUG
1006 printf("%s %d lines\n", __func__, lines);
1007 #endif
1008
1009 /* fill in CDT */
1010 for (i = 0; i < lines; i++) {
1011 #ifdef CORAM_DEBUG
1012 printf("CDT ent %08x, %08x\n", cdt + (16 * i),
1013 csc->csc_fifo + (bpl * i));
1014 #endif
1015 bus_space_write_4(sc->sc_memt, sc->sc_memh,
1016 cdt + (16 * i), csc->csc_fifo + (bpl * i));
1017 }
1018
1019 /* copy program */
1020 /* converts program to little endian as it goes into sram */
1021 bus_space_write_region_4(sc->sc_memt, sc->sc_memh,
1022 csc->csc_risc, (void *)sc->sc_riscbuf, sc->sc_riscbufsz >> 2);
1023
1024 /* fill in CMDS */
1025 bus_space_write_4(sc->sc_memt, sc->sc_memh,
1026 csc->csc_cmds + CMDS_O_IRPC, csc->csc_risc);
1027 bus_space_write_4(sc->sc_memt, sc->sc_memh,
1028 csc->csc_cmds + CMDS_O_IRPC + 4, 0);
1029
1030 bus_space_write_4(sc->sc_memt, sc->sc_memh,
1031 csc->csc_cmds + CMDS_O_CDTB, csc->csc_cdt);
1032 bus_space_write_4(sc->sc_memt, sc->sc_memh,
1033 csc->csc_cmds + CMDS_O_CDTS, (lines * 16) >> 3); /* XXX magic */
1034
1035 bus_space_write_4(sc->sc_memt, sc->sc_memh,
1036 csc->csc_cmds + CMDS_O_IQB, csc->csc_iq);
1037 bus_space_write_4(sc->sc_memt, sc->sc_memh,
1038 csc->csc_cmds + CMDS_O_IQS,
1039 CMDS_IQS_ISRP | (csc->csc_iqsz >> 2) );
1040
1041 /* zero rest of CMDS */
1042 bus_space_set_region_4(sc->sc_memt, sc->sc_memh, 0x18, 0, 20);
1043
1044 bus_space_write_4(sc->sc_memt, sc->sc_memh,
1045 csc->csc_ptr1, csc->csc_fifo);
1046 bus_space_write_4(sc->sc_memt, sc->sc_memh,
1047 csc->csc_ptr2, cdt);
1048 bus_space_write_4(sc->sc_memt, sc->sc_memh,
1049 csc->csc_cnt2, (lines * 16) >> 3);
1050 bus_space_write_4(sc->sc_memt, sc->sc_memh,
1051 csc->csc_cnt1, (bpl >> 3) - 1);
1052
1053 return 0;
1054 }
1055
1056 MODULE(MODULE_CLASS_DRIVER, coram, "cx24227,mt2131,pci");
1057
1058 #ifdef _MODULE
1059 #include "ioconf.c"
1060 #endif
1061
1062 static int
coram_modcmd(modcmd_t cmd,void * v)1063 coram_modcmd(modcmd_t cmd, void *v)
1064 {
1065 int error = 0;
1066
1067 switch (cmd) {
1068 case MODULE_CMD_INIT:
1069 #ifdef _MODULE
1070 error = config_init_component(cfdriver_ioconf_coram,
1071 cfattach_ioconf_coram, cfdata_ioconf_coram);
1072 #endif
1073 return error;
1074 case MODULE_CMD_FINI:
1075 #ifdef _MODULE
1076 error = config_fini_component(cfdriver_ioconf_coram,
1077 cfattach_ioconf_coram, cfdata_ioconf_coram);
1078 #endif
1079 return error;
1080 default:
1081 return ENOTTY;
1082 }
1083 }
1084