1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * Copyright(c) 2015-2018 Intel Corporation 3 */ 4 #ifndef _ICP_QAT_FW_COMP_H_ 5 #define _ICP_QAT_FW_COMP_H_ 6 7 #include "icp_qat_fw.h" 8 9 enum icp_qat_fw_comp_cmd_id { 10 ICP_QAT_FW_COMP_CMD_STATIC = 0, 11 /*!< Static Compress Request */ 12 13 ICP_QAT_FW_COMP_CMD_DYNAMIC = 1, 14 /*!< Dynamic Compress Request */ 15 16 ICP_QAT_FW_COMP_CMD_DECOMPRESS = 2, 17 /*!< Decompress Request */ 18 19 ICP_QAT_FW_COMP_CMD_DELIMITER 20 /**< Delimiter type */ 21 }; 22 23 /**< Flag usage */ 24 25 #define ICP_QAT_FW_COMP_STATELESS_SESSION 0 26 /**< @ingroup icp_qat_fw_comp 27 * Flag representing that session is stateless 28 */ 29 30 #define ICP_QAT_FW_COMP_STATEFUL_SESSION 1 31 /**< @ingroup icp_qat_fw_comp 32 * Flag representing that session is stateful 33 */ 34 35 #define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST 0 36 /**< @ingroup icp_qat_fw_comp 37 * Flag representing that autoselectbest is NOT used 38 */ 39 40 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST 1 41 /**< @ingroup icp_qat_fw_comp 42 * Flag representing that autoselectbest is used 43 */ 44 45 #define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST 0 46 /**< @ingroup icp_qat_fw_comp 47 * Flag representing that enhanced autoselectbest is NOT used 48 */ 49 50 #define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST 1 51 /**< @ingroup icp_qat_fw_comp 52 * Flag representing that enhanced autoselectbest is used 53 */ 54 55 #define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 0 56 /**< @ingroup icp_qat_fw_comp 57 * Flag representing that enhanced autoselectbest is NOT used 58 */ 59 60 #define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 1 61 /**< @ingroup icp_qat_fw_comp 62 * Flag representing that enhanced autoselectbest is used 63 */ 64 65 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF 1 66 /**< @ingroup icp_qat_fw_comp 67 * Flag representing secure RAM from being used as 68 * an intermediate buffer is DISABLED. 69 */ 70 71 #define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF 0 72 /**< @ingroup icp_qat_fw_comp 73 * Flag representing secure RAM from being used as 74 * an intermediate buffer is ENABLED. 75 */ 76 77 /**< Flag mask & bit position */ 78 79 #define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS 2 80 /**< @ingroup icp_qat_fw_comp 81 * Starting bit position for the session type 82 */ 83 84 #define ICP_QAT_FW_COMP_SESSION_TYPE_MASK 0x1 85 /**< @ingroup icp_qat_fw_comp 86 * One bit mask used to determine the session type 87 */ 88 89 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS 3 90 /**< @ingroup icp_qat_fw_comp 91 * Starting bit position for auto select best 92 */ 93 94 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK 0x1 95 /**< @ingroup icp_qat_fw_comp 96 * One bit mask for auto select best 97 */ 98 99 #define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS 4 100 /**< @ingroup icp_qat_fw_comp 101 * Starting bit position for enhanced auto select best 102 */ 103 104 #define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK 0x1 105 /**< @ingroup icp_qat_fw_comp 106 * One bit mask for enhanced auto select best 107 */ 108 109 #define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS 5 110 /**< @ingroup icp_qat_fw_comp 111 * Starting bit position for disabling type zero header write back 112 * when Enhanced autoselect best is enabled. If set firmware does 113 * not return type0 store block header, only copies src to dest. 114 * (if best output is Type0) 115 */ 116 117 #define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1 118 /**< @ingroup icp_qat_fw_comp 119 * One bit mask for auto select best 120 */ 121 122 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7 123 /**< @ingroup icp_qat_fw_comp 124 * Starting bit position for flag used to disable secure ram from 125 * being used as an intermediate buffer. 126 */ 127 128 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1 129 /**< @ingroup icp_qat_fw_comp 130 * One bit mask for disable secure ram for use as an intermediate 131 * buffer. 132 */ 133 134 #define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb, \ 135 ret_uncomp, secure_ram) \ 136 ((((sesstype)&ICP_QAT_FW_COMP_SESSION_TYPE_MASK) \ 137 << ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) | \ 138 (((autoselect)&ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) \ 139 << ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS) | \ 140 (((enhanced_asb)&ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) \ 141 << ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS) | \ 142 (((ret_uncomp)&ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) \ 143 << ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS) | \ 144 (((secure_ram)&ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) \ 145 << ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS)) 146 147 union icp_qat_fw_comp_req_hdr_cd_pars { 148 /**< LWs 2-5 */ 149 struct { 150 uint64_t content_desc_addr; 151 /**< Address of the content descriptor */ 152 153 uint16_t content_desc_resrvd1; 154 /**< Content descriptor reserved field */ 155 156 uint8_t content_desc_params_sz; 157 /**< Size of the content descriptor parameters in quad words. 158 * These parameters describe the session setup configuration 159 * info for the slices that this request relies upon i.e. 160 * the configuration word and cipher key needed by the cipher 161 * slice if there is a request for cipher processing. 162 */ 163 164 uint8_t content_desc_hdr_resrvd2; 165 /**< Content descriptor reserved field */ 166 167 uint32_t content_desc_resrvd3; 168 /**< Content descriptor reserved field */ 169 } s; 170 171 struct { 172 uint32_t comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2]; 173 /* Compression Slice Config Word */ 174 175 uint32_t content_desc_resrvd4; 176 /**< Content descriptor reserved field */ 177 178 } sl; 179 180 }; 181 182 struct icp_qat_fw_comp_req_params { 183 /**< LW 14 */ 184 uint32_t comp_len; 185 /**< Size of input to process in bytes Note: Only EOP requests can be 186 * odd for decompression. IA must set LSB to zero for odd sized 187 * intermediate inputs 188 */ 189 190 /**< LW 15 */ 191 uint32_t out_buffer_sz; 192 /**< Size of output buffer in bytes */ 193 194 /**< LW 16 */ 195 uint32_t initial_crc32; 196 /**< CRC of previously processed bytes */ 197 198 /**< LW 17 */ 199 uint32_t initial_adler; 200 /**< Adler of previously processed bytes */ 201 202 /**< LW 18 */ 203 uint32_t req_par_flags; 204 205 /**< LW 19 */ 206 uint32_t rsrvd; 207 }; 208 209 #define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr) \ 210 ((((sop)&ICP_QAT_FW_COMP_SOP_MASK) << ICP_QAT_FW_COMP_SOP_BITPOS) | \ 211 (((eop)&ICP_QAT_FW_COMP_EOP_MASK) << ICP_QAT_FW_COMP_EOP_BITPOS) | \ 212 (((bfinal)&ICP_QAT_FW_COMP_BFINAL_MASK) \ 213 << ICP_QAT_FW_COMP_BFINAL_BITPOS) | \ 214 ((cnv & ICP_QAT_FW_COMP_CNV_MASK) << ICP_QAT_FW_COMP_CNV_BITPOS) | \ 215 ((cnvnr & ICP_QAT_FW_COMP_CNV_RECOVERY_MASK) \ 216 << ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS)) 217 218 #define ICP_QAT_FW_COMP_NOT_SOP 0 219 /**< @ingroup icp_qat_fw_comp 220 * Flag representing that a request is NOT Start of Packet 221 */ 222 223 #define ICP_QAT_FW_COMP_SOP 1 224 /**< @ingroup icp_qat_fw_comp 225 * Flag representing that a request IS Start of Packet 226 */ 227 228 #define ICP_QAT_FW_COMP_NOT_EOP 0 229 /**< @ingroup icp_qat_fw_comp 230 * Flag representing that a request is NOT Start of Packet 231 */ 232 233 #define ICP_QAT_FW_COMP_EOP 1 234 /**< @ingroup icp_qat_fw_comp 235 * Flag representing that a request IS End of Packet 236 */ 237 238 #define ICP_QAT_FW_COMP_NOT_BFINAL 0 239 /**< @ingroup icp_qat_fw_comp 240 * Flag representing to indicate firmware this is not the last block 241 */ 242 243 #define ICP_QAT_FW_COMP_BFINAL 1 244 /**< @ingroup icp_qat_fw_comp 245 * Flag representing to indicate firmware this is the last block 246 */ 247 248 #define ICP_QAT_FW_COMP_NO_CNV 0 249 /**< @ingroup icp_qat_fw_comp 250 * Flag indicating that NO cnv check is to be performed on the request 251 */ 252 253 #define ICP_QAT_FW_COMP_CNV 1 254 /**< @ingroup icp_qat_fw_comp 255 * Flag indicating that a cnv check IS to be performed on the request 256 */ 257 258 #define ICP_QAT_FW_COMP_NO_CNV_RECOVERY 0 259 /**< @ingroup icp_qat_fw_comp 260 * Flag indicating that NO cnv recovery is to be performed on the request 261 */ 262 263 #define ICP_QAT_FW_COMP_CNV_RECOVERY 1 264 /**< @ingroup icp_qat_fw_comp 265 * Flag indicating that a cnv recovery is to be performed on the request 266 */ 267 268 #define ICP_QAT_FW_COMP_SOP_BITPOS 0 269 /**< @ingroup icp_qat_fw_comp 270 * Starting bit position for SOP 271 */ 272 273 #define ICP_QAT_FW_COMP_SOP_MASK 0x1 274 /**< @ingroup icp_qat_fw_comp 275 * One bit mask used to determine SOP 276 */ 277 278 #define ICP_QAT_FW_COMP_EOP_BITPOS 1 279 /**< @ingroup icp_qat_fw_comp 280 * Starting bit position for EOP 281 */ 282 283 #define ICP_QAT_FW_COMP_EOP_MASK 0x1 284 /**< @ingroup icp_qat_fw_comp 285 * One bit mask used to determine EOP 286 */ 287 288 #define ICP_QAT_FW_COMP_BFINAL_MASK 0x1 289 /**< @ingroup icp_qat_fw_comp 290 * One bit mask for the bfinal bit 291 */ 292 293 #define ICP_QAT_FW_COMP_BFINAL_BITPOS 6 294 /**< @ingroup icp_qat_fw_comp 295 * Starting bit position for the bfinal bit 296 */ 297 298 #define ICP_QAT_FW_COMP_CNV_MASK 0x1 299 /**< @ingroup icp_qat_fw_comp 300 * One bit mask for the CNV bit 301 */ 302 303 #define ICP_QAT_FW_COMP_CNV_BITPOS 16 304 /**< @ingroup icp_qat_fw_comp 305 * Starting bit position for the CNV bit 306 */ 307 308 #define ICP_QAT_FW_COMP_CNV_RECOVERY_MASK 0x1 309 /**< @ingroup icp_qat_fw_comp 310 * One bit mask for the CNV Recovery bit 311 */ 312 313 #define ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS 17 314 /**< @ingroup icp_qat_fw_comp 315 * Starting bit position for the CNV Recovery bit 316 */ 317 318 struct icp_qat_fw_xlt_req_params { 319 /**< LWs 20-21 */ 320 uint64_t inter_buff_ptr; 321 /**< This field specifies the physical address of an intermediate 322 * buffer SGL array. The array contains a pair of 64-bit 323 * intermediate buffer pointers to SGL buffer descriptors, one pair 324 * per CPM. Please refer to the CPM1.6 Firmware Interface HLD 325 * specification for more details. 326 */ 327 }; 328 329 330 struct icp_qat_fw_comp_cd_hdr { 331 /**< LW 24 */ 332 uint16_t ram_bank_flags; 333 /**< Flags to show which ram banks to access */ 334 335 uint8_t comp_cfg_offset; 336 /**< Quad word offset from the content descriptor parameters address 337 * to the parameters for the compression processing 338 */ 339 340 uint8_t next_curr_id; 341 /**< This field combines the next and current id (each four bits) - 342 * the next id is the most significant nibble. 343 * Next Id: Set to the next slice to pass the compressed data through. 344 * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through 345 * anymore slices after compression 346 * Current Id: Initialised with the compression slice type 347 */ 348 349 /**< LW 25 */ 350 uint32_t resrvd; 351 /**< LWs 26-27 */ 352 353 uint64_t comp_state_addr; 354 /**< Pointer to compression state */ 355 356 /**< LWs 28-29 */ 357 uint64_t ram_banks_addr; 358 /**< Pointer to banks */ 359 360 }; 361 362 363 struct icp_qat_fw_xlt_cd_hdr { 364 /**< LW 30 */ 365 uint16_t resrvd1; 366 /**< Reserved field and assumed set to 0 */ 367 368 uint8_t resrvd2; 369 /**< Reserved field and assumed set to 0 */ 370 371 uint8_t next_curr_id; 372 /**< This field combines the next and current id (each four bits) - 373 * the next id is the most significant nibble. 374 * Next Id: Set to the next slice to pass the translated data through. 375 * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through 376 * any more slices after compression 377 * Current Id: Initialised with the translation slice type 378 */ 379 380 /**< LW 31 */ 381 uint32_t resrvd3; 382 /**< Reserved and should be set to zero, needed for quadword 383 * alignment 384 */ 385 }; 386 387 struct icp_qat_fw_comp_req { 388 /**< LWs 0-1 */ 389 struct icp_qat_fw_comn_req_hdr comn_hdr; 390 /**< Common request header - for Service Command Id, 391 * use service-specific Compression Command Id. 392 * Service Specific Flags - use Compression Command Flags 393 */ 394 395 /**< LWs 2-5 */ 396 union icp_qat_fw_comp_req_hdr_cd_pars cd_pars; 397 /**< Compression service-specific content descriptor field which points 398 * either to a content descriptor parameter block or contains the 399 * compression slice config word. 400 */ 401 402 /**< LWs 6-13 */ 403 struct icp_qat_fw_comn_req_mid comn_mid; 404 /**< Common request middle section */ 405 406 /**< LWs 14-19 */ 407 struct icp_qat_fw_comp_req_params comp_pars; 408 /**< Compression request Parameters block */ 409 410 /**< LWs 20-21 */ 411 union { 412 struct icp_qat_fw_xlt_req_params xlt_pars; 413 /**< Translation request Parameters block */ 414 uint32_t resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2]; 415 /**< Reserved if not used for translation */ 416 417 } u1; 418 419 /**< LWs 22-23 */ 420 union { 421 uint32_t resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2]; 422 /**< Reserved - not used if Batch and Pack is disabled.*/ 423 424 uint64_t bnp_res_table_addr; 425 /**< A generic pointer to the unbounded list of 426 * icp_qat_fw_resp_comp_pars members. This pointer is only 427 * used when the Batch and Pack is enabled. 428 */ 429 } u3; 430 431 /**< LWs 24-29 */ 432 struct icp_qat_fw_comp_cd_hdr comp_cd_ctrl; 433 /**< Compression request content descriptor control block header */ 434 435 /**< LWs 30-31 */ 436 union { 437 struct icp_qat_fw_xlt_cd_hdr xlt_cd_ctrl; 438 /**< Translation request content descriptor 439 * control block header 440 */ 441 442 uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_2]; 443 /**< Reserved if not used for translation */ 444 } u2; 445 }; 446 447 struct icp_qat_fw_resp_comp_pars { 448 /**< LW 4 */ 449 uint32_t input_byte_counter; 450 /**< Input byte counter */ 451 452 /**< LW 5 */ 453 uint32_t output_byte_counter; 454 /**< Output byte counter */ 455 456 /**< LW 6 & 7*/ 457 union { 458 uint64_t curr_chksum; 459 struct { 460 /**< LW 6 */ 461 uint32_t curr_crc32; 462 /**< LW 7 */ 463 uint32_t curr_adler_32; 464 }; 465 }; 466 }; 467 468 struct icp_qat_fw_comp_resp { 469 /**< LWs 0-1 */ 470 struct icp_qat_fw_comn_resp_hdr comn_resp; 471 /**< Common interface response format see icp_qat_fw.h */ 472 473 /**< LWs 2-3 */ 474 uint64_t opaque_data; 475 /**< Opaque data passed from the request to the response message */ 476 477 /**< LWs 4-7 */ 478 struct icp_qat_fw_resp_comp_pars comp_resp_pars; 479 /**< Common response params (checksums and byte counts) */ 480 }; 481 482 /* RAM Bank definitions */ 483 #define QAT_FW_COMP_BANK_FLAG_MASK 0x1 484 485 #define QAT_FW_COMP_BANK_I_BITPOS 8 486 #define QAT_FW_COMP_BANK_H_BITPOS 7 487 #define QAT_FW_COMP_BANK_G_BITPOS 6 488 #define QAT_FW_COMP_BANK_F_BITPOS 5 489 #define QAT_FW_COMP_BANK_E_BITPOS 4 490 #define QAT_FW_COMP_BANK_D_BITPOS 3 491 #define QAT_FW_COMP_BANK_C_BITPOS 2 492 #define QAT_FW_COMP_BANK_B_BITPOS 1 493 #define QAT_FW_COMP_BANK_A_BITPOS 0 494 495 /** 496 ***************************************************************************** 497 * @ingroup icp_qat_fw_comp 498 * Definition of the ram bank enabled values 499 * @description 500 * Enumeration used to define whether a ram bank is enabled or not 501 * 502 *****************************************************************************/ 503 enum icp_qat_fw_comp_bank_enabled { 504 ICP_QAT_FW_COMP_BANK_DISABLED = 0, /*!< BANK DISABLED */ 505 ICP_QAT_FW_COMP_BANK_ENABLED = 1, /*!< BANK ENABLED */ 506 ICP_QAT_FW_COMP_BANK_DELIMITER = 2 /**< Delimiter type */ 507 }; 508 509 /** 510 ****************************************************************************** 511 * @ingroup icp_qat_fw_comp 512 * 513 * @description 514 * Build the ram bank flags in the compression content descriptor 515 * which specify which banks are used to save history 516 * 517 * @param bank_i_enable 518 * @param bank_h_enable 519 * @param bank_g_enable 520 * @param bank_f_enable 521 * @param bank_e_enable 522 * @param bank_d_enable 523 * @param bank_c_enable 524 * @param bank_b_enable 525 * @param bank_a_enable 526 *****************************************************************************/ 527 #define ICP_QAT_FW_COMP_RAM_FLAGS_BUILD(bank_i_enable, \ 528 bank_h_enable, \ 529 bank_g_enable, \ 530 bank_f_enable, \ 531 bank_e_enable, \ 532 bank_d_enable, \ 533 bank_c_enable, \ 534 bank_b_enable, \ 535 bank_a_enable) \ 536 ((((bank_i_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 537 << QAT_FW_COMP_BANK_I_BITPOS) | \ 538 (((bank_h_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 539 << QAT_FW_COMP_BANK_H_BITPOS) | \ 540 (((bank_g_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 541 << QAT_FW_COMP_BANK_G_BITPOS) | \ 542 (((bank_f_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 543 << QAT_FW_COMP_BANK_F_BITPOS) | \ 544 (((bank_e_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 545 << QAT_FW_COMP_BANK_E_BITPOS) | \ 546 (((bank_d_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 547 << QAT_FW_COMP_BANK_D_BITPOS) | \ 548 (((bank_c_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 549 << QAT_FW_COMP_BANK_C_BITPOS) | \ 550 (((bank_b_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 551 << QAT_FW_COMP_BANK_B_BITPOS) | \ 552 (((bank_a_enable)&QAT_FW_COMP_BANK_FLAG_MASK) \ 553 << QAT_FW_COMP_BANK_A_BITPOS)) 554 555 #endif 556