1 /* $NetBSD: sunxi_gmac.c,v 1.11 2024/08/10 12:16:47 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 31 __KERNEL_RCSID(0, "$NetBSD: sunxi_gmac.c,v 1.11 2024/08/10 12:16:47 skrll Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/device.h> 36 #include <sys/intr.h> 37 #include <sys/systm.h> 38 #include <sys/gpio.h> 39 #include <sys/rndsource.h> 40 41 #include <net/if.h> 42 #include <net/if_ether.h> 43 #include <net/if_media.h> 44 45 #include <dev/mii/miivar.h> 46 47 #include <dev/ic/dwc_gmac_var.h> 48 #include <dev/ic/dwc_gmac_reg.h> 49 50 #include <dev/fdt/fdtvar.h> 51 52 #define GMAC_TX_RATE_MII 25000000 53 #define GMAC_TX_RATE_RGMII 125000000 54 55 static const struct device_compatible_entry compat_data[] = { 56 { .compat = "allwinner,sun7i-a20-gmac" }, 57 DEVICE_COMPAT_EOL 58 }; 59 60 static int 61 sunxi_gmac_reset(const int phandle) 62 { 63 struct fdtbus_gpio_pin *pin_reset; 64 const u_int *reset_delay_us; 65 bool reset_active_low; 66 int len, val; 67 68 pin_reset = fdtbus_gpio_acquire(phandle, "snps,reset-gpio", GPIO_PIN_OUTPUT); 69 if (pin_reset == NULL) 70 return 0; 71 72 reset_delay_us = fdtbus_get_prop(phandle, "snps,reset-delays-us", &len); 73 if (reset_delay_us == NULL || len != 12) 74 return ENXIO; 75 76 reset_active_low = of_hasprop(phandle, "snps,reset-active-low"); 77 78 val = reset_active_low ? 1 : 0; 79 80 fdtbus_gpio_write(pin_reset, val); 81 delay(be32toh(reset_delay_us[0])); 82 fdtbus_gpio_write(pin_reset, !val); 83 delay(be32toh(reset_delay_us[1])); 84 fdtbus_gpio_write(pin_reset, val); 85 delay(be32toh(reset_delay_us[2])); 86 87 return 0; 88 } 89 90 static int 91 sunxi_gmac_intr(void *arg) 92 { 93 return dwc_gmac_intr(arg); 94 } 95 96 static int 97 sunxi_gmac_get_phyid(int phandle) 98 { 99 bus_addr_t addr; 100 int phy_phandle; 101 102 phy_phandle = fdtbus_get_phandle(phandle, "phy"); 103 if (phy_phandle == -1) 104 phy_phandle = fdtbus_get_phandle(phandle, "phy-handle"); 105 if (phy_phandle == -1) 106 return MII_PHY_ANY; 107 108 if (fdtbus_get_reg(phy_phandle, 0, &addr, NULL) != 0) 109 return MII_PHY_ANY; 110 111 return (int)addr; 112 } 113 114 static int 115 sunxi_gmac_match(device_t parent, cfdata_t cf, void *aux) 116 { 117 struct fdt_attach_args * const faa = aux; 118 119 return of_compatible_match(faa->faa_phandle, compat_data); 120 } 121 122 static void 123 sunxi_gmac_attach(device_t parent, device_t self, void *aux) 124 { 125 struct dwc_gmac_softc * const sc = device_private(self); 126 struct fdt_attach_args * const faa = aux; 127 const int phandle = faa->faa_phandle; 128 struct clk *clk_gmac, *clk_gmac_tx; 129 struct fdtbus_reset *rst_gmac; 130 struct fdtbus_regulator *reg_phy; 131 const char *phy_mode; 132 char intrstr[128]; 133 bus_addr_t addr; 134 bus_size_t size; 135 136 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) { 137 aprint_error(": couldn't get registers\n"); 138 return; 139 } 140 141 sc->sc_dev = self; 142 sc->sc_bst = faa->faa_bst; 143 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) { 144 aprint_error(": couldn't map registers\n"); 145 return; 146 } 147 sc->sc_dmat = faa->faa_dmat; 148 149 if (!fdtbus_intr_str(phandle, 0, intrstr, sizeof(intrstr))) { 150 aprint_error(": failed to decode interrupt\n"); 151 return; 152 } 153 154 clk_gmac = fdtbus_clock_get(phandle, "stmmaceth"); 155 clk_gmac_tx = fdtbus_clock_get(phandle, "allwinner_gmac_tx"); 156 if (clk_gmac == NULL || clk_gmac_tx == NULL) { 157 aprint_error(": couldn't get clocks\n"); 158 return; 159 } 160 161 rst_gmac = fdtbus_reset_get(phandle, "stmmaceth"); 162 163 phy_mode = fdtbus_get_string(phandle, "phy-mode"); 164 if (phy_mode == NULL) { 165 aprint_error(": missing 'phy-mode' property\n"); 166 return; 167 } 168 169 reg_phy = fdtbus_regulator_acquire(phandle, "phy-supply"); 170 if (reg_phy != NULL && fdtbus_regulator_enable(reg_phy) != 0) { 171 aprint_error(": couldn't enable PHY regualtor\n"); 172 return; 173 } 174 175 if (strcmp(phy_mode, "mii") == 0) { 176 if (clk_set_rate(clk_gmac_tx, GMAC_TX_RATE_MII) != 0) { 177 aprint_error(": failed to set TX clock rate (MII)\n"); 178 return; 179 } 180 } else if (strncmp(phy_mode, "rgmii", 5) == 0) { 181 if (clk_set_rate(clk_gmac_tx, GMAC_TX_RATE_RGMII) != 0) { 182 aprint_error(": failed to set TX clock rate (RGMII)\n"); 183 return; 184 } 185 } else { 186 aprint_error(": unsupported phy-mode '%s'\n", phy_mode); 187 return; 188 } 189 190 if (clk_enable(clk_gmac_tx) != 0 || clk_enable(clk_gmac) != 0) { 191 aprint_error(": couldn't enable clocks\n"); 192 return; 193 } 194 195 if (rst_gmac != NULL && fdtbus_reset_deassert(rst_gmac) != 0) { 196 aprint_error(": couldn't de-assert reset\n"); 197 return; 198 } 199 200 aprint_naive("\n"); 201 aprint_normal(": GMAC\n"); 202 203 if (fdtbus_intr_establish_xname(phandle, 0, IPL_NET, 204 FDT_INTR_MPSAFE, sunxi_gmac_intr, sc, 205 device_xname(self)) == NULL) { 206 aprint_error_dev(self, "failed to establish interrupt on %s\n", intrstr); 207 return; 208 } 209 aprint_normal_dev(self, "interrupting on %s\n", intrstr); 210 211 if (sunxi_gmac_reset(phandle) != 0) 212 aprint_error_dev(self, "PHY reset failed\n"); 213 214 dwc_gmac_attach(sc, sunxi_gmac_get_phyid(phandle), 215 GMAC_MII_CLK_150_250M_DIV102); 216 } 217 218 CFATTACH_DECL_NEW(sunxi_gmac, sizeof(struct dwc_gmac_softc), 219 sunxi_gmac_match, sunxi_gmac_attach, NULL, NULL); 220