1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2024 Free Software Foundation, Inc.
3
4 This file is part of the GNU opcodes library.
5
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
23 July 1988
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
27
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
34
35 #include "sysdep.h"
36 #include "disassemble.h"
37 #include "opintl.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
40 #include "safe-ctype.h"
41
42 typedef struct instr_info instr_info;
43
44 static bool dofloat (instr_info *, int);
45 static int putop (instr_info *, const char *, int);
46 static void oappend_with_style (instr_info *, const char *,
47 enum disassembler_style);
48
49 static bool OP_E (instr_info *, int, int);
50 static bool OP_E_memory (instr_info *, int, int);
51 static bool OP_indirE (instr_info *, int, int);
52 static bool OP_G (instr_info *, int, int);
53 static bool OP_ST (instr_info *, int, int);
54 static bool OP_STi (instr_info *, int, int);
55 static bool OP_Skip_MODRM (instr_info *, int, int);
56 static bool OP_REG (instr_info *, int, int);
57 static bool OP_IMREG (instr_info *, int, int);
58 static bool OP_I (instr_info *, int, int);
59 static bool OP_I64 (instr_info *, int, int);
60 static bool OP_sI (instr_info *, int, int);
61 static bool OP_J (instr_info *, int, int);
62 static bool OP_SEG (instr_info *, int, int);
63 static bool OP_DIR (instr_info *, int, int);
64 static bool OP_OFF (instr_info *, int, int);
65 static bool OP_OFF64 (instr_info *, int, int);
66 static bool OP_ESreg (instr_info *, int, int);
67 static bool OP_DSreg (instr_info *, int, int);
68 static bool OP_C (instr_info *, int, int);
69 static bool OP_D (instr_info *, int, int);
70 static bool OP_T (instr_info *, int, int);
71 static bool OP_MMX (instr_info *, int, int);
72 static bool OP_XMM (instr_info *, int, int);
73 static bool OP_EM (instr_info *, int, int);
74 static bool OP_EX (instr_info *, int, int);
75 static bool OP_EMC (instr_info *, int,int);
76 static bool OP_MXC (instr_info *, int,int);
77 static bool OP_R (instr_info *, int, int);
78 static bool OP_M (instr_info *, int, int);
79 static bool OP_VEX (instr_info *, int, int);
80 static bool OP_VexR (instr_info *, int, int);
81 static bool OP_VexW (instr_info *, int, int);
82 static bool OP_Rounding (instr_info *, int, int);
83 static bool OP_REG_VexI4 (instr_info *, int, int);
84 static bool OP_VexI4 (instr_info *, int, int);
85 static bool OP_0f07 (instr_info *, int, int);
86 static bool OP_Monitor (instr_info *, int, int);
87 static bool OP_Mwait (instr_info *, int, int);
88
89 static bool PCLMUL_Fixup (instr_info *, int, int);
90 static bool VPCMP_Fixup (instr_info *, int, int);
91 static bool VPCOM_Fixup (instr_info *, int, int);
92 static bool NOP_Fixup (instr_info *, int, int);
93 static bool OP_3DNowSuffix (instr_info *, int, int);
94 static bool CMP_Fixup (instr_info *, int, int);
95 static bool REP_Fixup (instr_info *, int, int);
96 static bool SEP_Fixup (instr_info *, int, int);
97 static bool BND_Fixup (instr_info *, int, int);
98 static bool NOTRACK_Fixup (instr_info *, int, int);
99 static bool HLE_Fixup1 (instr_info *, int, int);
100 static bool HLE_Fixup2 (instr_info *, int, int);
101 static bool HLE_Fixup3 (instr_info *, int, int);
102 static bool CMPXCHG8B_Fixup (instr_info *, int, int);
103 static bool XMM_Fixup (instr_info *, int, int);
104 static bool FXSAVE_Fixup (instr_info *, int, int);
105 static bool MOVSXD_Fixup (instr_info *, int, int);
106 static bool DistinctDest_Fixup (instr_info *, int, int);
107 static bool PREFETCHI_Fixup (instr_info *, int, int);
108 static bool PUSH2_POP2_Fixup (instr_info *, int, int);
109 static bool JMPABS_Fixup (instr_info *, int, int);
110
111 static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,
112 enum disassembler_style,
113 const char *, ...);
114
115 /* This character is used to encode style information within the output
116 buffers. See oappend_insert_style for more details. */
117 #define STYLE_MARKER_CHAR '\002'
118
119 /* The maximum operand buffer size. */
120 #define MAX_OPERAND_BUFFER_SIZE 128
121
122 enum address_mode
123 {
124 mode_16bit,
125 mode_32bit,
126 mode_64bit
127 };
128
129 static const char *prefix_name (enum address_mode, uint8_t, int);
130
131 enum x86_64_isa
132 {
133 amd64 = 1,
134 intel64
135 };
136
137 enum evex_type
138 {
139 evex_default = 0,
140 evex_from_legacy,
141 evex_from_vex,
142 };
143
144 struct instr_info
145 {
146 enum address_mode address_mode;
147
148 /* Flags for the prefixes for the current instruction. See below. */
149 int prefixes;
150
151 /* REX prefix the current instruction. See below. */
152 uint8_t rex;
153 /* Bits of REX we've already used. */
154 uint8_t rex_used;
155
156 /* Record W R4 X4 B4 bits for rex2. */
157 unsigned char rex2;
158 /* Bits of rex2 we've already used. */
159 unsigned char rex2_used;
160 unsigned char rex2_payload;
161
162 bool need_modrm;
163 unsigned char need_vex;
164 bool has_sib;
165
166 /* Flags for ins->prefixes which we somehow handled when printing the
167 current instruction. */
168 int used_prefixes;
169
170 /* Flags for EVEX bits which we somehow handled when printing the
171 current instruction. */
172 int evex_used;
173
174 char obuf[MAX_OPERAND_BUFFER_SIZE];
175 char *obufp;
176 char *mnemonicendp;
177 const uint8_t *start_codep;
178 uint8_t *codep;
179 const uint8_t *end_codep;
180 unsigned char nr_prefixes;
181 signed char last_lock_prefix;
182 signed char last_repz_prefix;
183 signed char last_repnz_prefix;
184 signed char last_data_prefix;
185 signed char last_addr_prefix;
186 signed char last_rex_prefix;
187 signed char last_rex2_prefix;
188 signed char last_seg_prefix;
189 signed char fwait_prefix;
190 /* The active segment register prefix. */
191 unsigned char active_seg_prefix;
192
193 #define MAX_CODE_LENGTH 15
194 /* We can up to 14 ins->prefixes since the maximum instruction length is
195 15bytes. */
196 uint8_t all_prefixes[MAX_CODE_LENGTH - 1];
197 disassemble_info *info;
198
199 struct
200 {
201 int mod;
202 int reg;
203 int rm;
204 }
205 modrm;
206
207 struct
208 {
209 int scale;
210 int index;
211 int base;
212 }
213 sib;
214
215 struct
216 {
217 int register_specifier;
218 int length;
219 int prefix;
220 int mask_register_specifier;
221 int ll;
222 bool w;
223 bool evex;
224 bool v;
225 bool zeroing;
226 bool b;
227 bool no_broadcast;
228 }
229 vex;
230
231 /* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b. */
232 #define nd b
233
234 enum evex_type evex_type;
235
236 /* Remember if the current op is a jump instruction. */
237 bool op_is_jump;
238
239 bool two_source_ops;
240
241 /* Record whether EVEX masking is used incorrectly. */
242 bool illegal_masking;
243
244 /* Record whether the modrm byte has been skipped. */
245 bool has_skipped_modrm;
246
247 unsigned char op_ad;
248 signed char op_index[MAX_OPERANDS];
249 bool op_riprel[MAX_OPERANDS];
250 char *op_out[MAX_OPERANDS];
251 bfd_vma op_address[MAX_OPERANDS];
252 bfd_vma start_pc;
253
254 /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
255 * (see topic "Redundant ins->prefixes" in the "Differences from 8086"
256 * section of the "Virtual 8086 Mode" chapter.)
257 * 'pc' should be the address of this instruction, it will
258 * be used to print the target address if this is a relative jump or call
259 * The function returns the length of this instruction in bytes.
260 */
261 char intel_syntax;
262 bool intel_mnemonic;
263 char open_char;
264 char close_char;
265 char separator_char;
266 char scale_char;
267
268 enum x86_64_isa isa64;
269 };
270
271 struct dis_private {
272 bfd_vma insn_start;
273 int orig_sizeflag;
274
275 /* Indexes first byte not fetched. */
276 unsigned int fetched;
277 uint8_t the_buffer[2 * MAX_CODE_LENGTH - 1];
278 };
279
280 /* Mark parts used in the REX prefix. When we are testing for
281 empty prefix (for 8bit register REX extension), just mask it
282 out. Otherwise test for REX bit is excuse for existence of REX
283 only in case value is nonzero. */
284 #define USED_REX(value) \
285 { \
286 if (value) \
287 { \
288 if (ins->rex & value) \
289 ins->rex_used |= (value) | REX_OPCODE; \
290 if (ins->rex2 & value) \
291 { \
292 ins->rex2_used |= (value); \
293 ins->rex_used |= REX_OPCODE; \
294 } \
295 } \
296 else \
297 ins->rex_used |= REX_OPCODE; \
298 }
299
300
301 #define EVEX_b_used 1
302 #define EVEX_len_used 2
303
304
305 /* {rex2} is not printed when the REX2_SPECIAL is set. */
306 #define REX2_SPECIAL 16
307
308 /* Flags stored in PREFIXES. */
309 #define PREFIX_REPZ 1
310 #define PREFIX_REPNZ 2
311 #define PREFIX_CS 4
312 #define PREFIX_SS 8
313 #define PREFIX_DS 0x10
314 #define PREFIX_ES 0x20
315 #define PREFIX_FS 0x40
316 #define PREFIX_GS 0x80
317 #define PREFIX_LOCK 0x100
318 #define PREFIX_DATA 0x200
319 #define PREFIX_ADDR 0x400
320 #define PREFIX_FWAIT 0x800
321 #define PREFIX_REX2 0x1000
322 #define PREFIX_NP_OR_DATA 0x2000
323 #define NO_PREFIX 0x4000
324
325 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
326 to ADDR (exclusive) are valid. Returns true for success, false
327 on error. */
328 static bool
fetch_code(struct disassemble_info * info,const uint8_t * until)329 fetch_code (struct disassemble_info *info, const uint8_t *until)
330 {
331 int status = -1;
332 struct dis_private *priv = info->private_data;
333 bfd_vma start = priv->insn_start + priv->fetched;
334 uint8_t *fetch_end = priv->the_buffer + priv->fetched;
335 ptrdiff_t needed = until - fetch_end;
336
337 if (needed <= 0)
338 return true;
339
340 if (priv->fetched + (size_t) needed <= ARRAY_SIZE (priv->the_buffer))
341 status = (*info->read_memory_func) (start, fetch_end, needed, info);
342 if (status != 0)
343 {
344 /* If we did manage to read at least one byte, then
345 print_insn_i386 will do something sensible. Otherwise, print
346 an error. We do that here because this is where we know
347 STATUS. */
348 if (!priv->fetched)
349 (*info->memory_error_func) (status, start, info);
350 return false;
351 }
352
353 priv->fetched += needed;
354 return true;
355 }
356
357 static bool
fetch_modrm(instr_info * ins)358 fetch_modrm (instr_info *ins)
359 {
360 if (!fetch_code (ins->info, ins->codep + 1))
361 return false;
362
363 ins->modrm.mod = (*ins->codep >> 6) & 3;
364 ins->modrm.reg = (*ins->codep >> 3) & 7;
365 ins->modrm.rm = *ins->codep & 7;
366
367 return true;
368 }
369
370 static int
fetch_error(const instr_info * ins)371 fetch_error (const instr_info *ins)
372 {
373 /* Getting here means we tried for data but didn't get it. That
374 means we have an incomplete instruction of some sort. Just
375 print the first byte as a prefix or a .byte pseudo-op. */
376 const struct dis_private *priv = ins->info->private_data;
377 const char *name = NULL;
378
379 if (ins->codep <= priv->the_buffer)
380 return -1;
381
382 if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE))
383 name = prefix_name (ins->address_mode, priv->the_buffer[0],
384 priv->orig_sizeflag);
385 if (name != NULL)
386 i386_dis_printf (ins->info, dis_style_mnemonic, "%s", name);
387 else
388 {
389 /* Just print the first byte as a .byte instruction. */
390 i386_dis_printf (ins->info, dis_style_assembler_directive, ".byte ");
391 i386_dis_printf (ins->info, dis_style_immediate, "%#x",
392 (unsigned int) priv->the_buffer[0]);
393 }
394
395 return 1;
396 }
397
398 /* Possible values for prefix requirement. */
399 #define PREFIX_IGNORED_SHIFT 16
400 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
401 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
402 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
403 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
404 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
405 #define PREFIX_REX2_ILLEGAL (PREFIX_REX2 << PREFIX_IGNORED_SHIFT)
406
407 /* Opcode prefixes. */
408 #define PREFIX_OPCODE (PREFIX_REPZ \
409 | PREFIX_REPNZ \
410 | PREFIX_DATA)
411
412 /* Prefixes ignored. */
413 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
414 | PREFIX_IGNORED_REPNZ \
415 | PREFIX_IGNORED_DATA)
416
417 #define XX { NULL, 0 }
418 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
419
420 #define Eb { OP_E, b_mode }
421 #define Ebnd { OP_E, bnd_mode }
422 #define EbS { OP_E, b_swap_mode }
423 #define EbndS { OP_E, bnd_swap_mode }
424 #define Ev { OP_E, v_mode }
425 #define Eva { OP_E, va_mode }
426 #define Ev_bnd { OP_E, v_bnd_mode }
427 #define EvS { OP_E, v_swap_mode }
428 #define Ed { OP_E, d_mode }
429 #define Edq { OP_E, dq_mode }
430 #define Edb { OP_E, db_mode }
431 #define Edw { OP_E, dw_mode }
432 #define Eq { OP_E, q_mode }
433 #define indirEv { OP_indirE, indir_v_mode }
434 #define indirEp { OP_indirE, f_mode }
435 #define stackEv { OP_E, stack_v_mode }
436 #define Em { OP_E, m_mode }
437 #define Ew { OP_E, w_mode }
438 #define M { OP_M, 0 } /* lea, lgdt, etc. */
439 #define Ma { OP_M, a_mode }
440 #define Mb { OP_M, b_mode }
441 #define Md { OP_M, d_mode }
442 #define Mdq { OP_M, dq_mode }
443 #define Mo { OP_M, o_mode }
444 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
445 #define Mq { OP_M, q_mode }
446 #define Mv { OP_M, v_mode }
447 #define Mv_bnd { OP_M, v_bndmk_mode }
448 #define Mw { OP_M, w_mode }
449 #define Mx { OP_M, x_mode }
450 #define Mxmm { OP_M, xmm_mode }
451 #define Mymm { OP_M, ymm_mode }
452 #define Gb { OP_G, b_mode }
453 #define Gbnd { OP_G, bnd_mode }
454 #define Gv { OP_G, v_mode }
455 #define Gd { OP_G, d_mode }
456 #define Gdq { OP_G, dq_mode }
457 #define Gq { OP_G, q_mode }
458 #define Gm { OP_G, m_mode }
459 #define Gva { OP_G, va_mode }
460 #define Gw { OP_G, w_mode }
461 #define Ib { OP_I, b_mode }
462 #define sIb { OP_sI, b_mode } /* sign extened byte */
463 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
464 #define Iv { OP_I, v_mode }
465 #define sIv { OP_sI, v_mode }
466 #define Iv64 { OP_I64, v_mode }
467 #define Id { OP_I, d_mode }
468 #define Iw { OP_I, w_mode }
469 #define I1 { OP_I, const_1_mode }
470 #define Jb { OP_J, b_mode }
471 #define Jv { OP_J, v_mode }
472 #define Jdqw { OP_J, dqw_mode }
473 #define Cm { OP_C, m_mode }
474 #define Dm { OP_D, m_mode }
475 #define Td { OP_T, d_mode }
476 #define Skip_MODRM { OP_Skip_MODRM, 0 }
477
478 #define RMeAX { OP_REG, eAX_reg }
479 #define RMeBX { OP_REG, eBX_reg }
480 #define RMeCX { OP_REG, eCX_reg }
481 #define RMeDX { OP_REG, eDX_reg }
482 #define RMeSP { OP_REG, eSP_reg }
483 #define RMeBP { OP_REG, eBP_reg }
484 #define RMeSI { OP_REG, eSI_reg }
485 #define RMeDI { OP_REG, eDI_reg }
486 #define RMrAX { OP_REG, rAX_reg }
487 #define RMrBX { OP_REG, rBX_reg }
488 #define RMrCX { OP_REG, rCX_reg }
489 #define RMrDX { OP_REG, rDX_reg }
490 #define RMrSP { OP_REG, rSP_reg }
491 #define RMrBP { OP_REG, rBP_reg }
492 #define RMrSI { OP_REG, rSI_reg }
493 #define RMrDI { OP_REG, rDI_reg }
494 #define RMAL { OP_REG, al_reg }
495 #define RMCL { OP_REG, cl_reg }
496 #define RMDL { OP_REG, dl_reg }
497 #define RMBL { OP_REG, bl_reg }
498 #define RMAH { OP_REG, ah_reg }
499 #define RMCH { OP_REG, ch_reg }
500 #define RMDH { OP_REG, dh_reg }
501 #define RMBH { OP_REG, bh_reg }
502 #define RMAX { OP_REG, ax_reg }
503 #define RMDX { OP_REG, dx_reg }
504
505 #define eAX { OP_IMREG, eAX_reg }
506 #define AL { OP_IMREG, al_reg }
507 #define CL { OP_IMREG, cl_reg }
508 #define zAX { OP_IMREG, z_mode_ax_reg }
509 #define indirDX { OP_IMREG, indir_dx_reg }
510
511 #define Sw { OP_SEG, w_mode }
512 #define Sv { OP_SEG, v_mode }
513 #define Ap { OP_DIR, 0 }
514 #define Ob { OP_OFF64, b_mode }
515 #define Ov { OP_OFF64, v_mode }
516 #define Xb { OP_DSreg, eSI_reg }
517 #define Xv { OP_DSreg, eSI_reg }
518 #define Xz { OP_DSreg, eSI_reg }
519 #define Yb { OP_ESreg, eDI_reg }
520 #define Yv { OP_ESreg, eDI_reg }
521 #define DSBX { OP_DSreg, eBX_reg }
522
523 #define es { OP_REG, es_reg }
524 #define ss { OP_REG, ss_reg }
525 #define cs { OP_REG, cs_reg }
526 #define ds { OP_REG, ds_reg }
527 #define fs { OP_REG, fs_reg }
528 #define gs { OP_REG, gs_reg }
529
530 #define MX { OP_MMX, 0 }
531 #define XM { OP_XMM, 0 }
532 #define XMScalar { OP_XMM, scalar_mode }
533 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
534 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
535 #define XMM { OP_XMM, xmm_mode }
536 #define TMM { OP_XMM, tmm_mode }
537 #define XMxmmq { OP_XMM, xmmq_mode }
538 #define EM { OP_EM, v_mode }
539 #define EMS { OP_EM, v_swap_mode }
540 #define EMd { OP_EM, d_mode }
541 #define EMx { OP_EM, x_mode }
542 #define EXbwUnit { OP_EX, bw_unit_mode }
543 #define EXb { OP_EX, b_mode }
544 #define EXw { OP_EX, w_mode }
545 #define EXd { OP_EX, d_mode }
546 #define EXdS { OP_EX, d_swap_mode }
547 #define EXwS { OP_EX, w_swap_mode }
548 #define EXq { OP_EX, q_mode }
549 #define EXqS { OP_EX, q_swap_mode }
550 #define EXdq { OP_EX, dq_mode }
551 #define EXx { OP_EX, x_mode }
552 #define EXxh { OP_EX, xh_mode }
553 #define EXxS { OP_EX, x_swap_mode }
554 #define EXxmm { OP_EX, xmm_mode }
555 #define EXymm { OP_EX, ymm_mode }
556 #define EXxmmq { OP_EX, xmmq_mode }
557 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
558 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
559 #define EXxmmdw { OP_EX, xmmdw_mode }
560 #define EXxmmqd { OP_EX, xmmqd_mode }
561 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
562 #define EXymmq { OP_EX, ymmq_mode }
563 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
564 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
565 #define Rd { OP_R, d_mode }
566 #define Rdq { OP_R, dq_mode }
567 #define Rq { OP_R, q_mode }
568 #define Nq { OP_R, q_mm_mode }
569 #define Ux { OP_R, x_mode }
570 #define Uxmm { OP_R, xmm_mode }
571 #define Rxmmq { OP_R, xmmq_mode }
572 #define Rymm { OP_R, ymm_mode }
573 #define Rtmm { OP_R, tmm_mode }
574 #define EMCq { OP_EMC, q_mode }
575 #define MXC { OP_MXC, 0 }
576 #define OPSUF { OP_3DNowSuffix, 0 }
577 #define SEP { SEP_Fixup, 0 }
578 #define CMP { CMP_Fixup, 0 }
579 #define XMM0 { XMM_Fixup, 0 }
580 #define FXSAVE { FXSAVE_Fixup, 0 }
581
582 #define Vex { OP_VEX, x_mode }
583 #define VexW { OP_VexW, x_mode }
584 #define VexScalar { OP_VEX, scalar_mode }
585 #define VexScalarR { OP_VexR, scalar_mode }
586 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
587 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
588 #define VexGdq { OP_VEX, dq_mode }
589 #define VexGb { OP_VEX, b_mode }
590 #define VexGv { OP_VEX, v_mode }
591 #define VexTmm { OP_VEX, tmm_mode }
592 #define XMVexI4 { OP_REG_VexI4, x_mode }
593 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
594 #define VexI4 { OP_VexI4, 0 }
595 #define PCLMUL { PCLMUL_Fixup, 0 }
596 #define VPCMP { VPCMP_Fixup, 0 }
597 #define VPCOM { VPCOM_Fixup, 0 }
598
599 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
600 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
601 #define EXxEVexS { OP_Rounding, evex_sae_mode }
602
603 #define MaskG { OP_G, mask_mode }
604 #define MaskE { OP_E, mask_mode }
605 #define MaskR { OP_R, mask_mode }
606 #define MaskBDE { OP_E, mask_bd_mode }
607 #define MaskVex { OP_VEX, mask_mode }
608
609 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
610 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
611
612 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
613
614 /* Used handle "rep" prefix for string instructions. */
615 #define Xbr { REP_Fixup, eSI_reg }
616 #define Xvr { REP_Fixup, eSI_reg }
617 #define Ybr { REP_Fixup, eDI_reg }
618 #define Yvr { REP_Fixup, eDI_reg }
619 #define Yzr { REP_Fixup, eDI_reg }
620 #define indirDXr { REP_Fixup, indir_dx_reg }
621 #define ALr { REP_Fixup, al_reg }
622 #define eAXr { REP_Fixup, eAX_reg }
623
624 /* Used handle HLE prefix for lockable instructions. */
625 #define Ebh1 { HLE_Fixup1, b_mode }
626 #define Evh1 { HLE_Fixup1, v_mode }
627 #define Ebh2 { HLE_Fixup2, b_mode }
628 #define Evh2 { HLE_Fixup2, v_mode }
629 #define Ebh3 { HLE_Fixup3, b_mode }
630 #define Evh3 { HLE_Fixup3, v_mode }
631
632 #define BND { BND_Fixup, 0 }
633 #define NOTRACK { NOTRACK_Fixup, 0 }
634
635 #define cond_jump_flag { NULL, cond_jump_mode }
636 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
637
638 /* bits in sizeflag */
639 #define SUFFIX_ALWAYS 4
640 #define AFLAG 2
641 #define DFLAG 1
642
643 enum
644 {
645 /* byte operand */
646 b_mode = 1,
647 /* byte operand with operand swapped */
648 b_swap_mode,
649 /* byte operand, sign extend like 'T' suffix */
650 b_T_mode,
651 /* operand size depends on prefixes */
652 v_mode,
653 /* operand size depends on prefixes with operand swapped */
654 v_swap_mode,
655 /* operand size depends on address prefix */
656 va_mode,
657 /* word operand */
658 w_mode,
659 /* double word operand */
660 d_mode,
661 /* word operand with operand swapped */
662 w_swap_mode,
663 /* double word operand with operand swapped */
664 d_swap_mode,
665 /* quad word operand */
666 q_mode,
667 /* 8-byte MM operand */
668 q_mm_mode,
669 /* quad word operand with operand swapped */
670 q_swap_mode,
671 /* ten-byte operand */
672 t_mode,
673 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
674 broadcast enabled. */
675 x_mode,
676 /* Similar to x_mode, but with different EVEX mem shifts. */
677 evex_x_gscat_mode,
678 /* Similar to x_mode, but with yet different EVEX mem shifts. */
679 bw_unit_mode,
680 /* Similar to x_mode, but with disabled broadcast. */
681 evex_x_nobcst_mode,
682 /* Similar to x_mode, but with operands swapped and disabled broadcast
683 in EVEX. */
684 x_swap_mode,
685 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
686 broadcast of 16bit enabled. */
687 xh_mode,
688 /* 16-byte XMM operand */
689 xmm_mode,
690 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
691 memory operand (depending on vector length). Broadcast isn't
692 allowed. */
693 xmmq_mode,
694 /* Same as xmmq_mode, but broadcast is allowed. */
695 evex_half_bcst_xmmq_mode,
696 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
697 memory operand (depending on vector length). 16bit broadcast. */
698 evex_half_bcst_xmmqh_mode,
699 /* 16-byte XMM, word, double word or quad word operand. */
700 xmmdw_mode,
701 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
702 xmmqd_mode,
703 /* 16-byte XMM, double word, quad word operand or xmm word operand.
704 16bit broadcast. */
705 evex_half_bcst_xmmqdh_mode,
706 /* 32-byte YMM operand */
707 ymm_mode,
708 /* quad word, ymmword or zmmword memory operand. */
709 ymmq_mode,
710 /* TMM operand */
711 tmm_mode,
712 /* d_mode in 32bit, q_mode in 64bit mode. */
713 m_mode,
714 /* pair of v_mode operands */
715 a_mode,
716 cond_jump_mode,
717 loop_jcxz_mode,
718 movsxd_mode,
719 v_bnd_mode,
720 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
721 v_bndmk_mode,
722 /* operand size depends on REX.W / VEX.W. */
723 dq_mode,
724 /* Displacements like v_mode without considering Intel64 ISA. */
725 dqw_mode,
726 /* bounds operand */
727 bnd_mode,
728 /* bounds operand with operand swapped */
729 bnd_swap_mode,
730 /* 4- or 6-byte pointer operand */
731 f_mode,
732 const_1_mode,
733 /* v_mode for indirect branch opcodes. */
734 indir_v_mode,
735 /* v_mode for stack-related opcodes. */
736 stack_v_mode,
737 /* non-quad operand size depends on prefixes */
738 z_mode,
739 /* 16-byte operand */
740 o_mode,
741 /* registers like d_mode, memory like b_mode. */
742 db_mode,
743 /* registers like d_mode, memory like w_mode. */
744 dw_mode,
745
746 /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
747 vex_vsib_d_w_dq_mode,
748 /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
749 vex_vsib_q_w_dq_mode,
750 /* mandatory non-vector SIB. */
751 vex_sibmem_mode,
752
753 /* scalar, ignore vector length. */
754 scalar_mode,
755
756 /* Static rounding. */
757 evex_rounding_mode,
758 /* Static rounding, 64-bit mode only. */
759 evex_rounding_64_mode,
760 /* Supress all exceptions. */
761 evex_sae_mode,
762
763 /* Mask register operand. */
764 mask_mode,
765 /* Mask register operand. */
766 mask_bd_mode,
767
768 es_reg,
769 cs_reg,
770 ss_reg,
771 ds_reg,
772 fs_reg,
773 gs_reg,
774
775 eAX_reg,
776 eCX_reg,
777 eDX_reg,
778 eBX_reg,
779 eSP_reg,
780 eBP_reg,
781 eSI_reg,
782 eDI_reg,
783
784 al_reg,
785 cl_reg,
786 dl_reg,
787 bl_reg,
788 ah_reg,
789 ch_reg,
790 dh_reg,
791 bh_reg,
792
793 ax_reg,
794 cx_reg,
795 dx_reg,
796 bx_reg,
797 sp_reg,
798 bp_reg,
799 si_reg,
800 di_reg,
801
802 rAX_reg,
803 rCX_reg,
804 rDX_reg,
805 rBX_reg,
806 rSP_reg,
807 rBP_reg,
808 rSI_reg,
809 rDI_reg,
810
811 z_mode_ax_reg,
812 indir_dx_reg
813 };
814
815 enum
816 {
817 FLOATCODE = 1,
818 USE_REG_TABLE,
819 USE_MOD_TABLE,
820 USE_RM_TABLE,
821 USE_PREFIX_TABLE,
822 USE_X86_64_TABLE,
823 USE_X86_64_EVEX_FROM_VEX_TABLE,
824 USE_3BYTE_TABLE,
825 USE_XOP_8F_TABLE,
826 USE_VEX_C4_TABLE,
827 USE_VEX_C5_TABLE,
828 USE_VEX_LEN_TABLE,
829 USE_VEX_W_TABLE,
830 USE_EVEX_TABLE,
831 USE_EVEX_LEN_TABLE
832 };
833
834 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
835
836 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
837 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
838 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
839 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
840 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
841 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
842 #define X86_64_EVEX_FROM_VEX_TABLE(I) \
843 DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I))
844 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
845 #define XOP_8F_TABLE() DIS386 (USE_XOP_8F_TABLE, 0)
846 #define VEX_C4_TABLE() DIS386 (USE_VEX_C4_TABLE, 0)
847 #define VEX_C5_TABLE() DIS386 (USE_VEX_C5_TABLE, 0)
848 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
849 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
850 #define EVEX_TABLE() DIS386 (USE_EVEX_TABLE, 0)
851 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
852
853 enum
854 {
855 REG_80 = 0,
856 REG_81,
857 REG_83,
858 REG_8F,
859 REG_C0,
860 REG_C1,
861 REG_C6,
862 REG_C7,
863 REG_D0,
864 REG_D1,
865 REG_D2,
866 REG_D3,
867 REG_F6,
868 REG_F7,
869 REG_FE,
870 REG_FF,
871 REG_0F00,
872 REG_0F01,
873 REG_0F0D,
874 REG_0F18,
875 REG_0F1C_P_0_MOD_0,
876 REG_0F1E_P_1_MOD_3,
877 REG_0F38D8_PREFIX_1,
878 REG_0F3A0F_P_1,
879 REG_0F71,
880 REG_0F72,
881 REG_0F73,
882 REG_0FA6,
883 REG_0FA7,
884 REG_0FAE,
885 REG_0FBA,
886 REG_0FC7,
887 REG_VEX_0F71,
888 REG_VEX_0F72,
889 REG_VEX_0F73,
890 REG_VEX_0FAE,
891 REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
892 REG_VEX_0F38F3_L_0_P_0,
893 REG_VEX_MAP7_F8_L_0_W_0,
894
895 REG_XOP_09_01_L_0,
896 REG_XOP_09_02_L_0,
897 REG_XOP_09_12_L_0,
898 REG_XOP_0A_12_L_0,
899
900 REG_EVEX_0F71,
901 REG_EVEX_0F72,
902 REG_EVEX_0F73,
903 REG_EVEX_0F38C6_L_2,
904 REG_EVEX_0F38C7_L_2,
905 REG_EVEX_MAP4_80,
906 REG_EVEX_MAP4_81,
907 REG_EVEX_MAP4_83,
908 REG_EVEX_MAP4_8F,
909 REG_EVEX_MAP4_F6,
910 REG_EVEX_MAP4_F7,
911 REG_EVEX_MAP4_FE,
912 REG_EVEX_MAP4_FF,
913 };
914
915 enum
916 {
917 MOD_62_32BIT = 0,
918 MOD_C4_32BIT,
919 MOD_C5_32BIT,
920 MOD_0F01_REG_0,
921 MOD_0F01_REG_1,
922 MOD_0F01_REG_2,
923 MOD_0F01_REG_3,
924 MOD_0F01_REG_5,
925 MOD_0F01_REG_7,
926 MOD_0F12_PREFIX_0,
927 MOD_0F16_PREFIX_0,
928 MOD_0F18_REG_0,
929 MOD_0F18_REG_1,
930 MOD_0F18_REG_2,
931 MOD_0F18_REG_3,
932 MOD_0F18_REG_6,
933 MOD_0F18_REG_7,
934 MOD_0F1A_PREFIX_0,
935 MOD_0F1B_PREFIX_0,
936 MOD_0F1B_PREFIX_1,
937 MOD_0F1C_PREFIX_0,
938 MOD_0F1E_PREFIX_1,
939 MOD_0FAE_REG_0,
940 MOD_0FAE_REG_1,
941 MOD_0FAE_REG_2,
942 MOD_0FAE_REG_3,
943 MOD_0FAE_REG_4,
944 MOD_0FAE_REG_5,
945 MOD_0FAE_REG_6,
946 MOD_0FAE_REG_7,
947 MOD_0FC7_REG_6,
948 MOD_0FC7_REG_7,
949 MOD_0F38DC_PREFIX_1,
950 MOD_0F38F8,
951
952 MOD_VEX_0F3849_X86_64_L_0_W_0,
953
954 MOD_EVEX_MAP4_F8_P_1,
955 MOD_EVEX_MAP4_F8_P_3,
956 };
957
958 enum
959 {
960 RM_C6_REG_7 = 0,
961 RM_C7_REG_7,
962 RM_0F01_REG_0,
963 RM_0F01_REG_1,
964 RM_0F01_REG_2,
965 RM_0F01_REG_3,
966 RM_0F01_REG_5_MOD_3,
967 RM_0F01_REG_7_MOD_3,
968 RM_0F1E_P_1_MOD_3_REG_7,
969 RM_0FAE_REG_6_MOD_3_P_0,
970 RM_0FAE_REG_7_MOD_3,
971 RM_0F3A0F_P_1_R_0,
972
973 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
974 RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
975 };
976
977 enum
978 {
979 PREFIX_90 = 0,
980 PREFIX_0F00_REG_6_X86_64,
981 PREFIX_0F01_REG_0_MOD_3_RM_6,
982 PREFIX_0F01_REG_0_MOD_3_RM_7,
983 PREFIX_0F01_REG_1_RM_2,
984 PREFIX_0F01_REG_1_RM_4,
985 PREFIX_0F01_REG_1_RM_5,
986 PREFIX_0F01_REG_1_RM_6,
987 PREFIX_0F01_REG_1_RM_7,
988 PREFIX_0F01_REG_3_RM_1,
989 PREFIX_0F01_REG_5_MOD_0,
990 PREFIX_0F01_REG_5_MOD_3_RM_0,
991 PREFIX_0F01_REG_5_MOD_3_RM_1,
992 PREFIX_0F01_REG_5_MOD_3_RM_2,
993 PREFIX_0F01_REG_5_MOD_3_RM_4,
994 PREFIX_0F01_REG_5_MOD_3_RM_5,
995 PREFIX_0F01_REG_5_MOD_3_RM_6,
996 PREFIX_0F01_REG_5_MOD_3_RM_7,
997 PREFIX_0F01_REG_7_MOD_3_RM_2,
998 PREFIX_0F01_REG_7_MOD_3_RM_5,
999 PREFIX_0F01_REG_7_MOD_3_RM_6,
1000 PREFIX_0F01_REG_7_MOD_3_RM_7,
1001 PREFIX_0F09,
1002 PREFIX_0F10,
1003 PREFIX_0F11,
1004 PREFIX_0F12,
1005 PREFIX_0F16,
1006 PREFIX_0F18_REG_6_MOD_0_X86_64,
1007 PREFIX_0F18_REG_7_MOD_0_X86_64,
1008 PREFIX_0F1A,
1009 PREFIX_0F1B,
1010 PREFIX_0F1C,
1011 PREFIX_0F1E,
1012 PREFIX_0F2A,
1013 PREFIX_0F2B,
1014 PREFIX_0F2C,
1015 PREFIX_0F2D,
1016 PREFIX_0F2E,
1017 PREFIX_0F2F,
1018 PREFIX_0F51,
1019 PREFIX_0F52,
1020 PREFIX_0F53,
1021 PREFIX_0F58,
1022 PREFIX_0F59,
1023 PREFIX_0F5A,
1024 PREFIX_0F5B,
1025 PREFIX_0F5C,
1026 PREFIX_0F5D,
1027 PREFIX_0F5E,
1028 PREFIX_0F5F,
1029 PREFIX_0F60,
1030 PREFIX_0F61,
1031 PREFIX_0F62,
1032 PREFIX_0F6F,
1033 PREFIX_0F70,
1034 PREFIX_0F78,
1035 PREFIX_0F79,
1036 PREFIX_0F7C,
1037 PREFIX_0F7D,
1038 PREFIX_0F7E,
1039 PREFIX_0F7F,
1040 PREFIX_0FAE_REG_0_MOD_3,
1041 PREFIX_0FAE_REG_1_MOD_3,
1042 PREFIX_0FAE_REG_2_MOD_3,
1043 PREFIX_0FAE_REG_3_MOD_3,
1044 PREFIX_0FAE_REG_4_MOD_0,
1045 PREFIX_0FAE_REG_4_MOD_3,
1046 PREFIX_0FAE_REG_5_MOD_3,
1047 PREFIX_0FAE_REG_6_MOD_0,
1048 PREFIX_0FAE_REG_6_MOD_3,
1049 PREFIX_0FAE_REG_7_MOD_0,
1050 PREFIX_0FB8,
1051 PREFIX_0FBC,
1052 PREFIX_0FBD,
1053 PREFIX_0FC2,
1054 PREFIX_0FC7_REG_6_MOD_0,
1055 PREFIX_0FC7_REG_6_MOD_3,
1056 PREFIX_0FC7_REG_7_MOD_3,
1057 PREFIX_0FD0,
1058 PREFIX_0FD6,
1059 PREFIX_0FE6,
1060 PREFIX_0FE7,
1061 PREFIX_0FF0,
1062 PREFIX_0FF7,
1063 PREFIX_0F38D8,
1064 PREFIX_0F38DC,
1065 PREFIX_0F38DD,
1066 PREFIX_0F38DE,
1067 PREFIX_0F38DF,
1068 PREFIX_0F38F0,
1069 PREFIX_0F38F1,
1070 PREFIX_0F38F6,
1071 PREFIX_0F38F8_M_0,
1072 PREFIX_0F38F8_M_1_X86_64,
1073 PREFIX_0F38FA,
1074 PREFIX_0F38FB,
1075 PREFIX_0F38FC,
1076 PREFIX_0F3A0F,
1077 PREFIX_VEX_0F12,
1078 PREFIX_VEX_0F16,
1079 PREFIX_VEX_0F2A,
1080 PREFIX_VEX_0F2C,
1081 PREFIX_VEX_0F2D,
1082 PREFIX_VEX_0F41_L_1_W_0,
1083 PREFIX_VEX_0F41_L_1_W_1,
1084 PREFIX_VEX_0F42_L_1_W_0,
1085 PREFIX_VEX_0F42_L_1_W_1,
1086 PREFIX_VEX_0F44_L_0_W_0,
1087 PREFIX_VEX_0F44_L_0_W_1,
1088 PREFIX_VEX_0F45_L_1_W_0,
1089 PREFIX_VEX_0F45_L_1_W_1,
1090 PREFIX_VEX_0F46_L_1_W_0,
1091 PREFIX_VEX_0F46_L_1_W_1,
1092 PREFIX_VEX_0F47_L_1_W_0,
1093 PREFIX_VEX_0F47_L_1_W_1,
1094 PREFIX_VEX_0F4A_L_1_W_0,
1095 PREFIX_VEX_0F4A_L_1_W_1,
1096 PREFIX_VEX_0F4B_L_1_W_0,
1097 PREFIX_VEX_0F4B_L_1_W_1,
1098 PREFIX_VEX_0F6F,
1099 PREFIX_VEX_0F70,
1100 PREFIX_VEX_0F7E,
1101 PREFIX_VEX_0F7F,
1102 PREFIX_VEX_0F90_L_0_W_0,
1103 PREFIX_VEX_0F90_L_0_W_1,
1104 PREFIX_VEX_0F91_L_0_W_0,
1105 PREFIX_VEX_0F91_L_0_W_1,
1106 PREFIX_VEX_0F92_L_0_W_0,
1107 PREFIX_VEX_0F92_L_0_W_1,
1108 PREFIX_VEX_0F93_L_0_W_0,
1109 PREFIX_VEX_0F93_L_0_W_1,
1110 PREFIX_VEX_0F98_L_0_W_0,
1111 PREFIX_VEX_0F98_L_0_W_1,
1112 PREFIX_VEX_0F99_L_0_W_0,
1113 PREFIX_VEX_0F99_L_0_W_1,
1114 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
1115 PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
1116 PREFIX_VEX_0F384B_X86_64_L_0_W_0,
1117 PREFIX_VEX_0F3850_W_0,
1118 PREFIX_VEX_0F3851_W_0,
1119 PREFIX_VEX_0F385C_X86_64_L_0_W_0,
1120 PREFIX_VEX_0F385E_X86_64_L_0_W_0,
1121 PREFIX_VEX_0F386C_X86_64_L_0_W_0,
1122 PREFIX_VEX_0F3872,
1123 PREFIX_VEX_0F38B0_W_0,
1124 PREFIX_VEX_0F38B1_W_0,
1125 PREFIX_VEX_0F38D2_W_0,
1126 PREFIX_VEX_0F38D3_W_0,
1127 PREFIX_VEX_0F38CB,
1128 PREFIX_VEX_0F38CC,
1129 PREFIX_VEX_0F38CD,
1130 PREFIX_VEX_0F38DA_W_0,
1131 PREFIX_VEX_0F38F2_L_0,
1132 PREFIX_VEX_0F38F3_L_0,
1133 PREFIX_VEX_0F38F5_L_0,
1134 PREFIX_VEX_0F38F6_L_0,
1135 PREFIX_VEX_0F38F7_L_0,
1136 PREFIX_VEX_0F3AF0_L_0,
1137 PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64,
1138
1139 PREFIX_EVEX_0F5B,
1140 PREFIX_EVEX_0F6F,
1141 PREFIX_EVEX_0F70,
1142 PREFIX_EVEX_0F78,
1143 PREFIX_EVEX_0F79,
1144 PREFIX_EVEX_0F7A,
1145 PREFIX_EVEX_0F7B,
1146 PREFIX_EVEX_0F7E,
1147 PREFIX_EVEX_0F7F,
1148 PREFIX_EVEX_0FC2,
1149 PREFIX_EVEX_0FE6,
1150 PREFIX_EVEX_0F3810,
1151 PREFIX_EVEX_0F3811,
1152 PREFIX_EVEX_0F3812,
1153 PREFIX_EVEX_0F3813,
1154 PREFIX_EVEX_0F3814,
1155 PREFIX_EVEX_0F3815,
1156 PREFIX_EVEX_0F3820,
1157 PREFIX_EVEX_0F3821,
1158 PREFIX_EVEX_0F3822,
1159 PREFIX_EVEX_0F3823,
1160 PREFIX_EVEX_0F3824,
1161 PREFIX_EVEX_0F3825,
1162 PREFIX_EVEX_0F3826,
1163 PREFIX_EVEX_0F3827,
1164 PREFIX_EVEX_0F3828,
1165 PREFIX_EVEX_0F3829,
1166 PREFIX_EVEX_0F382A,
1167 PREFIX_EVEX_0F3830,
1168 PREFIX_EVEX_0F3831,
1169 PREFIX_EVEX_0F3832,
1170 PREFIX_EVEX_0F3833,
1171 PREFIX_EVEX_0F3834,
1172 PREFIX_EVEX_0F3835,
1173 PREFIX_EVEX_0F3838,
1174 PREFIX_EVEX_0F3839,
1175 PREFIX_EVEX_0F383A,
1176 PREFIX_EVEX_0F3852,
1177 PREFIX_EVEX_0F3853,
1178 PREFIX_EVEX_0F3868,
1179 PREFIX_EVEX_0F3872,
1180 PREFIX_EVEX_0F389A,
1181 PREFIX_EVEX_0F389B,
1182 PREFIX_EVEX_0F38AA,
1183 PREFIX_EVEX_0F38AB,
1184
1185 PREFIX_EVEX_0F3A08,
1186 PREFIX_EVEX_0F3A0A,
1187 PREFIX_EVEX_0F3A26,
1188 PREFIX_EVEX_0F3A27,
1189 PREFIX_EVEX_0F3A56,
1190 PREFIX_EVEX_0F3A57,
1191 PREFIX_EVEX_0F3A66,
1192 PREFIX_EVEX_0F3A67,
1193 PREFIX_EVEX_0F3AC2,
1194
1195 PREFIX_EVEX_MAP4_D8,
1196 PREFIX_EVEX_MAP4_DA,
1197 PREFIX_EVEX_MAP4_DB,
1198 PREFIX_EVEX_MAP4_DC,
1199 PREFIX_EVEX_MAP4_DD,
1200 PREFIX_EVEX_MAP4_DE,
1201 PREFIX_EVEX_MAP4_DF,
1202 PREFIX_EVEX_MAP4_F0,
1203 PREFIX_EVEX_MAP4_F1,
1204 PREFIX_EVEX_MAP4_F2,
1205 PREFIX_EVEX_MAP4_F8,
1206
1207 PREFIX_EVEX_MAP5_10,
1208 PREFIX_EVEX_MAP5_11,
1209 PREFIX_EVEX_MAP5_1D,
1210 PREFIX_EVEX_MAP5_2A,
1211 PREFIX_EVEX_MAP5_2C,
1212 PREFIX_EVEX_MAP5_2D,
1213 PREFIX_EVEX_MAP5_2E,
1214 PREFIX_EVEX_MAP5_2F,
1215 PREFIX_EVEX_MAP5_51,
1216 PREFIX_EVEX_MAP5_58,
1217 PREFIX_EVEX_MAP5_59,
1218 PREFIX_EVEX_MAP5_5A,
1219 PREFIX_EVEX_MAP5_5B,
1220 PREFIX_EVEX_MAP5_5C,
1221 PREFIX_EVEX_MAP5_5D,
1222 PREFIX_EVEX_MAP5_5E,
1223 PREFIX_EVEX_MAP5_5F,
1224 PREFIX_EVEX_MAP5_78,
1225 PREFIX_EVEX_MAP5_79,
1226 PREFIX_EVEX_MAP5_7A,
1227 PREFIX_EVEX_MAP5_7B,
1228 PREFIX_EVEX_MAP5_7C,
1229 PREFIX_EVEX_MAP5_7D,
1230
1231 PREFIX_EVEX_MAP6_13,
1232 PREFIX_EVEX_MAP6_56,
1233 PREFIX_EVEX_MAP6_57,
1234 PREFIX_EVEX_MAP6_D6,
1235 PREFIX_EVEX_MAP6_D7,
1236 };
1237
1238 enum
1239 {
1240 X86_64_06 = 0,
1241 X86_64_07,
1242 X86_64_0E,
1243 X86_64_16,
1244 X86_64_17,
1245 X86_64_1E,
1246 X86_64_1F,
1247 X86_64_27,
1248 X86_64_2F,
1249 X86_64_37,
1250 X86_64_3F,
1251 X86_64_60,
1252 X86_64_61,
1253 X86_64_62,
1254 X86_64_63,
1255 X86_64_6D,
1256 X86_64_6F,
1257 X86_64_82,
1258 X86_64_9A,
1259 X86_64_C2,
1260 X86_64_C3,
1261 X86_64_C4,
1262 X86_64_C5,
1263 X86_64_CE,
1264 X86_64_D4,
1265 X86_64_D5,
1266 X86_64_E8,
1267 X86_64_E9,
1268 X86_64_EA,
1269 X86_64_0F00_REG_6,
1270 X86_64_0F01_REG_0,
1271 X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
1272 X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
1273 X86_64_0F01_REG_0_MOD_3_RM_7_P_0,
1274 X86_64_0F01_REG_1,
1275 X86_64_0F01_REG_1_RM_2_PREFIX_1,
1276 X86_64_0F01_REG_1_RM_2_PREFIX_3,
1277 X86_64_0F01_REG_1_RM_5_PREFIX_2,
1278 X86_64_0F01_REG_1_RM_6_PREFIX_2,
1279 X86_64_0F01_REG_1_RM_7_PREFIX_2,
1280 X86_64_0F01_REG_2,
1281 X86_64_0F01_REG_3,
1282 X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1283 X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1284 X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1285 X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1286 X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
1287 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1288 X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1289 X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1290 X86_64_0F18_REG_6_MOD_0,
1291 X86_64_0F18_REG_7_MOD_0,
1292 X86_64_0F24,
1293 X86_64_0F26,
1294 X86_64_0F38F8_M_1,
1295 X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1296
1297 X86_64_VEX_0F3849,
1298 X86_64_VEX_0F384B,
1299 X86_64_VEX_0F385C,
1300 X86_64_VEX_0F385E,
1301 X86_64_VEX_0F386C,
1302 X86_64_VEX_0F38E0,
1303 X86_64_VEX_0F38E1,
1304 X86_64_VEX_0F38E2,
1305 X86_64_VEX_0F38E3,
1306 X86_64_VEX_0F38E4,
1307 X86_64_VEX_0F38E5,
1308 X86_64_VEX_0F38E6,
1309 X86_64_VEX_0F38E7,
1310 X86_64_VEX_0F38E8,
1311 X86_64_VEX_0F38E9,
1312 X86_64_VEX_0F38EA,
1313 X86_64_VEX_0F38EB,
1314 X86_64_VEX_0F38EC,
1315 X86_64_VEX_0F38ED,
1316 X86_64_VEX_0F38EE,
1317 X86_64_VEX_0F38EF,
1318
1319 X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
1320
1321 X86_64_EVEX_0F90,
1322 X86_64_EVEX_0F91,
1323 X86_64_EVEX_0F92,
1324 X86_64_EVEX_0F93,
1325 X86_64_EVEX_0F38F2,
1326 X86_64_EVEX_0F38F3,
1327 X86_64_EVEX_0F38F5,
1328 X86_64_EVEX_0F38F6,
1329 X86_64_EVEX_0F38F7,
1330 X86_64_EVEX_0F3AF0,
1331 };
1332
1333 enum
1334 {
1335 THREE_BYTE_0F38 = 0,
1336 THREE_BYTE_0F3A
1337 };
1338
1339 enum
1340 {
1341 XOP_08 = 0,
1342 XOP_09,
1343 XOP_0A
1344 };
1345
1346 enum
1347 {
1348 VEX_0F = 0,
1349 VEX_0F38,
1350 VEX_0F3A,
1351 VEX_MAP7,
1352 };
1353
1354 enum
1355 {
1356 EVEX_0F = 0,
1357 EVEX_0F38,
1358 EVEX_0F3A,
1359 EVEX_MAP4,
1360 EVEX_MAP5,
1361 EVEX_MAP6,
1362 EVEX_MAP7,
1363 };
1364
1365 enum
1366 {
1367 VEX_LEN_0F12_P_0 = 0,
1368 VEX_LEN_0F12_P_2,
1369 VEX_LEN_0F13,
1370 VEX_LEN_0F16_P_0,
1371 VEX_LEN_0F16_P_2,
1372 VEX_LEN_0F17,
1373 VEX_LEN_0F41,
1374 VEX_LEN_0F42,
1375 VEX_LEN_0F44,
1376 VEX_LEN_0F45,
1377 VEX_LEN_0F46,
1378 VEX_LEN_0F47,
1379 VEX_LEN_0F4A,
1380 VEX_LEN_0F4B,
1381 VEX_LEN_0F6E,
1382 VEX_LEN_0F77,
1383 VEX_LEN_0F7E_P_1,
1384 VEX_LEN_0F7E_P_2,
1385 VEX_LEN_0F90,
1386 VEX_LEN_0F91,
1387 VEX_LEN_0F92,
1388 VEX_LEN_0F93,
1389 VEX_LEN_0F98,
1390 VEX_LEN_0F99,
1391 VEX_LEN_0FAE_R_2,
1392 VEX_LEN_0FAE_R_3,
1393 VEX_LEN_0FC4,
1394 VEX_LEN_0FD6,
1395 VEX_LEN_0F3816,
1396 VEX_LEN_0F3819,
1397 VEX_LEN_0F381A,
1398 VEX_LEN_0F3836,
1399 VEX_LEN_0F3841,
1400 VEX_LEN_0F3849_X86_64,
1401 VEX_LEN_0F384B_X86_64,
1402 VEX_LEN_0F385A,
1403 VEX_LEN_0F385C_X86_64,
1404 VEX_LEN_0F385E_X86_64,
1405 VEX_LEN_0F386C_X86_64,
1406 VEX_LEN_0F38CB_P_3_W_0,
1407 VEX_LEN_0F38CC_P_3_W_0,
1408 VEX_LEN_0F38CD_P_3_W_0,
1409 VEX_LEN_0F38DA_W_0_P_0,
1410 VEX_LEN_0F38DA_W_0_P_2,
1411 VEX_LEN_0F38DB,
1412 VEX_LEN_0F38F2,
1413 VEX_LEN_0F38F3,
1414 VEX_LEN_0F38F5,
1415 VEX_LEN_0F38F6,
1416 VEX_LEN_0F38F7,
1417 VEX_LEN_0F3A00,
1418 VEX_LEN_0F3A01,
1419 VEX_LEN_0F3A06,
1420 VEX_LEN_0F3A14,
1421 VEX_LEN_0F3A15,
1422 VEX_LEN_0F3A16,
1423 VEX_LEN_0F3A17,
1424 VEX_LEN_0F3A18,
1425 VEX_LEN_0F3A19,
1426 VEX_LEN_0F3A20,
1427 VEX_LEN_0F3A21,
1428 VEX_LEN_0F3A22,
1429 VEX_LEN_0F3A30,
1430 VEX_LEN_0F3A31,
1431 VEX_LEN_0F3A32,
1432 VEX_LEN_0F3A33,
1433 VEX_LEN_0F3A38,
1434 VEX_LEN_0F3A39,
1435 VEX_LEN_0F3A41,
1436 VEX_LEN_0F3A46,
1437 VEX_LEN_0F3A60,
1438 VEX_LEN_0F3A61,
1439 VEX_LEN_0F3A62,
1440 VEX_LEN_0F3A63,
1441 VEX_LEN_0F3ADE_W_0,
1442 VEX_LEN_0F3ADF,
1443 VEX_LEN_0F3AF0,
1444 VEX_LEN_MAP7_F8,
1445 VEX_LEN_XOP_08_85,
1446 VEX_LEN_XOP_08_86,
1447 VEX_LEN_XOP_08_87,
1448 VEX_LEN_XOP_08_8E,
1449 VEX_LEN_XOP_08_8F,
1450 VEX_LEN_XOP_08_95,
1451 VEX_LEN_XOP_08_96,
1452 VEX_LEN_XOP_08_97,
1453 VEX_LEN_XOP_08_9E,
1454 VEX_LEN_XOP_08_9F,
1455 VEX_LEN_XOP_08_A3,
1456 VEX_LEN_XOP_08_A6,
1457 VEX_LEN_XOP_08_B6,
1458 VEX_LEN_XOP_08_C0,
1459 VEX_LEN_XOP_08_C1,
1460 VEX_LEN_XOP_08_C2,
1461 VEX_LEN_XOP_08_C3,
1462 VEX_LEN_XOP_08_CC,
1463 VEX_LEN_XOP_08_CD,
1464 VEX_LEN_XOP_08_CE,
1465 VEX_LEN_XOP_08_CF,
1466 VEX_LEN_XOP_08_EC,
1467 VEX_LEN_XOP_08_ED,
1468 VEX_LEN_XOP_08_EE,
1469 VEX_LEN_XOP_08_EF,
1470 VEX_LEN_XOP_09_01,
1471 VEX_LEN_XOP_09_02,
1472 VEX_LEN_XOP_09_12,
1473 VEX_LEN_XOP_09_82_W_0,
1474 VEX_LEN_XOP_09_83_W_0,
1475 VEX_LEN_XOP_09_90,
1476 VEX_LEN_XOP_09_91,
1477 VEX_LEN_XOP_09_92,
1478 VEX_LEN_XOP_09_93,
1479 VEX_LEN_XOP_09_94,
1480 VEX_LEN_XOP_09_95,
1481 VEX_LEN_XOP_09_96,
1482 VEX_LEN_XOP_09_97,
1483 VEX_LEN_XOP_09_98,
1484 VEX_LEN_XOP_09_99,
1485 VEX_LEN_XOP_09_9A,
1486 VEX_LEN_XOP_09_9B,
1487 VEX_LEN_XOP_09_C1,
1488 VEX_LEN_XOP_09_C2,
1489 VEX_LEN_XOP_09_C3,
1490 VEX_LEN_XOP_09_C6,
1491 VEX_LEN_XOP_09_C7,
1492 VEX_LEN_XOP_09_CB,
1493 VEX_LEN_XOP_09_D1,
1494 VEX_LEN_XOP_09_D2,
1495 VEX_LEN_XOP_09_D3,
1496 VEX_LEN_XOP_09_D6,
1497 VEX_LEN_XOP_09_D7,
1498 VEX_LEN_XOP_09_DB,
1499 VEX_LEN_XOP_09_E1,
1500 VEX_LEN_XOP_09_E2,
1501 VEX_LEN_XOP_09_E3,
1502 VEX_LEN_XOP_0A_12,
1503 };
1504
1505 enum
1506 {
1507 EVEX_LEN_0F3816 = 0,
1508 EVEX_LEN_0F3819,
1509 EVEX_LEN_0F381A,
1510 EVEX_LEN_0F381B,
1511 EVEX_LEN_0F3836,
1512 EVEX_LEN_0F385A,
1513 EVEX_LEN_0F385B,
1514 EVEX_LEN_0F38C6,
1515 EVEX_LEN_0F38C7,
1516 EVEX_LEN_0F3A00,
1517 EVEX_LEN_0F3A01,
1518 EVEX_LEN_0F3A18,
1519 EVEX_LEN_0F3A19,
1520 EVEX_LEN_0F3A1A,
1521 EVEX_LEN_0F3A1B,
1522 EVEX_LEN_0F3A23,
1523 EVEX_LEN_0F3A38,
1524 EVEX_LEN_0F3A39,
1525 EVEX_LEN_0F3A3A,
1526 EVEX_LEN_0F3A3B,
1527 EVEX_LEN_0F3A43
1528 };
1529
1530 enum
1531 {
1532 VEX_W_0F41_L_1 = 0,
1533 VEX_W_0F42_L_1,
1534 VEX_W_0F44_L_0,
1535 VEX_W_0F45_L_1,
1536 VEX_W_0F46_L_1,
1537 VEX_W_0F47_L_1,
1538 VEX_W_0F4A_L_1,
1539 VEX_W_0F4B_L_1,
1540 VEX_W_0F90_L_0,
1541 VEX_W_0F91_L_0,
1542 VEX_W_0F92_L_0,
1543 VEX_W_0F93_L_0,
1544 VEX_W_0F98_L_0,
1545 VEX_W_0F99_L_0,
1546 VEX_W_0F380C,
1547 VEX_W_0F380D,
1548 VEX_W_0F380E,
1549 VEX_W_0F380F,
1550 VEX_W_0F3813,
1551 VEX_W_0F3816_L_1,
1552 VEX_W_0F3818,
1553 VEX_W_0F3819_L_1,
1554 VEX_W_0F381A_L_1,
1555 VEX_W_0F382C,
1556 VEX_W_0F382D,
1557 VEX_W_0F382E,
1558 VEX_W_0F382F,
1559 VEX_W_0F3836,
1560 VEX_W_0F3846,
1561 VEX_W_0F3849_X86_64_L_0,
1562 VEX_W_0F384B_X86_64_L_0,
1563 VEX_W_0F3850,
1564 VEX_W_0F3851,
1565 VEX_W_0F3852,
1566 VEX_W_0F3853,
1567 VEX_W_0F3858,
1568 VEX_W_0F3859,
1569 VEX_W_0F385A_L_0,
1570 VEX_W_0F385C_X86_64_L_0,
1571 VEX_W_0F385E_X86_64_L_0,
1572 VEX_W_0F386C_X86_64_L_0,
1573 VEX_W_0F3872_P_1,
1574 VEX_W_0F3878,
1575 VEX_W_0F3879,
1576 VEX_W_0F38B0,
1577 VEX_W_0F38B1,
1578 VEX_W_0F38B4,
1579 VEX_W_0F38B5,
1580 VEX_W_0F38CB_P_3,
1581 VEX_W_0F38CC_P_3,
1582 VEX_W_0F38CD_P_3,
1583 VEX_W_0F38CF,
1584 VEX_W_0F38D2,
1585 VEX_W_0F38D3,
1586 VEX_W_0F38DA,
1587 VEX_W_0F3A00_L_1,
1588 VEX_W_0F3A01_L_1,
1589 VEX_W_0F3A02,
1590 VEX_W_0F3A04,
1591 VEX_W_0F3A05,
1592 VEX_W_0F3A06_L_1,
1593 VEX_W_0F3A18_L_1,
1594 VEX_W_0F3A19_L_1,
1595 VEX_W_0F3A1D,
1596 VEX_W_0F3A38_L_1,
1597 VEX_W_0F3A39_L_1,
1598 VEX_W_0F3A46_L_1,
1599 VEX_W_0F3A4A,
1600 VEX_W_0F3A4B,
1601 VEX_W_0F3A4C,
1602 VEX_W_0F3ACE,
1603 VEX_W_0F3ACF,
1604 VEX_W_0F3ADE,
1605 VEX_W_MAP7_F8_L_0,
1606
1607 VEX_W_XOP_08_85_L_0,
1608 VEX_W_XOP_08_86_L_0,
1609 VEX_W_XOP_08_87_L_0,
1610 VEX_W_XOP_08_8E_L_0,
1611 VEX_W_XOP_08_8F_L_0,
1612 VEX_W_XOP_08_95_L_0,
1613 VEX_W_XOP_08_96_L_0,
1614 VEX_W_XOP_08_97_L_0,
1615 VEX_W_XOP_08_9E_L_0,
1616 VEX_W_XOP_08_9F_L_0,
1617 VEX_W_XOP_08_A6_L_0,
1618 VEX_W_XOP_08_B6_L_0,
1619 VEX_W_XOP_08_C0_L_0,
1620 VEX_W_XOP_08_C1_L_0,
1621 VEX_W_XOP_08_C2_L_0,
1622 VEX_W_XOP_08_C3_L_0,
1623 VEX_W_XOP_08_CC_L_0,
1624 VEX_W_XOP_08_CD_L_0,
1625 VEX_W_XOP_08_CE_L_0,
1626 VEX_W_XOP_08_CF_L_0,
1627 VEX_W_XOP_08_EC_L_0,
1628 VEX_W_XOP_08_ED_L_0,
1629 VEX_W_XOP_08_EE_L_0,
1630 VEX_W_XOP_08_EF_L_0,
1631
1632 VEX_W_XOP_09_80,
1633 VEX_W_XOP_09_81,
1634 VEX_W_XOP_09_82,
1635 VEX_W_XOP_09_83,
1636 VEX_W_XOP_09_C1_L_0,
1637 VEX_W_XOP_09_C2_L_0,
1638 VEX_W_XOP_09_C3_L_0,
1639 VEX_W_XOP_09_C6_L_0,
1640 VEX_W_XOP_09_C7_L_0,
1641 VEX_W_XOP_09_CB_L_0,
1642 VEX_W_XOP_09_D1_L_0,
1643 VEX_W_XOP_09_D2_L_0,
1644 VEX_W_XOP_09_D3_L_0,
1645 VEX_W_XOP_09_D6_L_0,
1646 VEX_W_XOP_09_D7_L_0,
1647 VEX_W_XOP_09_DB_L_0,
1648 VEX_W_XOP_09_E1_L_0,
1649 VEX_W_XOP_09_E2_L_0,
1650 VEX_W_XOP_09_E3_L_0,
1651
1652 EVEX_W_0F5B_P_0,
1653 EVEX_W_0F62,
1654 EVEX_W_0F66,
1655 EVEX_W_0F6A,
1656 EVEX_W_0F6B,
1657 EVEX_W_0F6C,
1658 EVEX_W_0F6D,
1659 EVEX_W_0F6F_P_1,
1660 EVEX_W_0F6F_P_2,
1661 EVEX_W_0F6F_P_3,
1662 EVEX_W_0F70_P_2,
1663 EVEX_W_0F72_R_2,
1664 EVEX_W_0F72_R_6,
1665 EVEX_W_0F73_R_2,
1666 EVEX_W_0F73_R_6,
1667 EVEX_W_0F76,
1668 EVEX_W_0F78_P_0,
1669 EVEX_W_0F78_P_2,
1670 EVEX_W_0F79_P_0,
1671 EVEX_W_0F79_P_2,
1672 EVEX_W_0F7A_P_1,
1673 EVEX_W_0F7A_P_2,
1674 EVEX_W_0F7A_P_3,
1675 EVEX_W_0F7B_P_2,
1676 EVEX_W_0F7E_P_1,
1677 EVEX_W_0F7F_P_1,
1678 EVEX_W_0F7F_P_2,
1679 EVEX_W_0F7F_P_3,
1680 EVEX_W_0FD2,
1681 EVEX_W_0FD3,
1682 EVEX_W_0FD4,
1683 EVEX_W_0FD6,
1684 EVEX_W_0FE6_P_1,
1685 EVEX_W_0FE7,
1686 EVEX_W_0FF2,
1687 EVEX_W_0FF3,
1688 EVEX_W_0FF4,
1689 EVEX_W_0FFA,
1690 EVEX_W_0FFB,
1691 EVEX_W_0FFE,
1692
1693 EVEX_W_0F3810_P_1,
1694 EVEX_W_0F3810_P_2,
1695 EVEX_W_0F3811_P_1,
1696 EVEX_W_0F3811_P_2,
1697 EVEX_W_0F3812_P_1,
1698 EVEX_W_0F3812_P_2,
1699 EVEX_W_0F3813_P_1,
1700 EVEX_W_0F3814_P_1,
1701 EVEX_W_0F3815_P_1,
1702 EVEX_W_0F3819_L_n,
1703 EVEX_W_0F381A_L_n,
1704 EVEX_W_0F381B_L_2,
1705 EVEX_W_0F381E,
1706 EVEX_W_0F381F,
1707 EVEX_W_0F3820_P_1,
1708 EVEX_W_0F3821_P_1,
1709 EVEX_W_0F3822_P_1,
1710 EVEX_W_0F3823_P_1,
1711 EVEX_W_0F3824_P_1,
1712 EVEX_W_0F3825_P_1,
1713 EVEX_W_0F3825_P_2,
1714 EVEX_W_0F3828_P_2,
1715 EVEX_W_0F3829_P_2,
1716 EVEX_W_0F382A_P_1,
1717 EVEX_W_0F382A_P_2,
1718 EVEX_W_0F382B,
1719 EVEX_W_0F3830_P_1,
1720 EVEX_W_0F3831_P_1,
1721 EVEX_W_0F3832_P_1,
1722 EVEX_W_0F3833_P_1,
1723 EVEX_W_0F3834_P_1,
1724 EVEX_W_0F3835_P_1,
1725 EVEX_W_0F3835_P_2,
1726 EVEX_W_0F3837,
1727 EVEX_W_0F383A_P_1,
1728 EVEX_W_0F3859,
1729 EVEX_W_0F385A_L_n,
1730 EVEX_W_0F385B_L_2,
1731 EVEX_W_0F3870,
1732 EVEX_W_0F3872_P_2,
1733 EVEX_W_0F387A,
1734 EVEX_W_0F387B,
1735 EVEX_W_0F3883,
1736
1737 EVEX_W_0F3A18_L_n,
1738 EVEX_W_0F3A19_L_n,
1739 EVEX_W_0F3A1A_L_2,
1740 EVEX_W_0F3A1B_L_2,
1741 EVEX_W_0F3A21,
1742 EVEX_W_0F3A23_L_n,
1743 EVEX_W_0F3A38_L_n,
1744 EVEX_W_0F3A39_L_n,
1745 EVEX_W_0F3A3A_L_2,
1746 EVEX_W_0F3A3B_L_2,
1747 EVEX_W_0F3A42,
1748 EVEX_W_0F3A43_L_n,
1749 EVEX_W_0F3A70,
1750 EVEX_W_0F3A72,
1751
1752 EVEX_W_MAP4_8F_R_0,
1753 EVEX_W_MAP4_FF_R_6,
1754
1755 EVEX_W_MAP5_5B_P_0,
1756 EVEX_W_MAP5_7A_P_3,
1757 };
1758
1759 typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1760
1761 struct dis386 {
1762 const char *name;
1763 struct
1764 {
1765 op_rtn rtn;
1766 int bytemode;
1767 } op[MAX_OPERANDS];
1768 unsigned int prefix_requirement;
1769 };
1770
1771 /* Upper case letters in the instruction names here are macros.
1772 'A' => print 'b' if no (suitable) register operand or suffix_always is true
1773 'B' => print 'b' if suffix_always is true
1774 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1775 size prefix
1776 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1777 suffix_always is true
1778 'E' => print 'e' if 32-bit form of jcxz
1779 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1780 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1781 'H' => print ",pt" or ",pn" branch hint
1782 'I' unused.
1783 'J' unused.
1784 'K' => print 'd' or 'q' if rex prefix is present.
1785 'L' => print 'l' or 'q' if suffix_always is true
1786 'M' => print 'r' if intel_mnemonic is false.
1787 'N' => print 'n' if instruction has no wait "prefix"
1788 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1789 'P' => behave as 'T' except with register operand outside of suffix_always
1790 mode
1791 'Q' => print 'w', 'l' or 'q' if no (suitable) register operand or
1792 suffix_always is true
1793 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1794 'S' => print 'w', 'l' or 'q' if suffix_always is true
1795 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1796 prefix or if suffix_always is true.
1797 'U' unused.
1798 'V' => print 'v' for VEX/EVEX and nothing for legacy encodings.
1799 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1800 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1801 'Y' => no output, mark EVEX.aaa != 0 as bad.
1802 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1803 '!' => change condition from true to false or from false to true.
1804 '%' => add 1 upper case letter to the macro.
1805 '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1806 prefix or suffix_always is true (lcall/ljmp).
1807 '@' => in 64bit mode for Intel64 ISA or if instruction
1808 has no operand sizing prefix, print 'q' if suffix_always is true or
1809 nothing otherwise; behave as 'P' in all other cases
1810
1811 2 upper case letter macros:
1812 "XY" => print 'x' or 'y' if suffix_always is true or no register
1813 operands and no broadcast.
1814 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1815 register operands and no broadcast.
1816 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1817 "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1818 "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1819 "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1820 "XV" => print "{vex} " pseudo prefix
1821 "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1822 is used by an EVEX-encoded (AVX512VL) instruction.
1823 "YK" keep unused, to avoid ambiguity with the combined use of Y and K.
1824 "YX" keep unused, to avoid ambiguity with the combined use of Y and X.
1825 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1826 being false, or no operand at all in 64bit mode, or if suffix_always
1827 is true.
1828 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1829 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1830 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1831 "DQ" => print 'd' or 'q' depending on the VEX.W bit
1832 "BW" => print 'b' or 'w' depending on the VEX.W bit
1833 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1834 an operand size prefix, or suffix_always is true. print
1835 'q' if rex prefix is present.
1836
1837 Many of the above letters print nothing in Intel mode. See "putop"
1838 for the details.
1839
1840 Braces '{' and '}', and vertical bars '|', indicate alternative
1841 mnemonic strings for AT&T and Intel. */
1842
1843 static const struct dis386 dis386[] = {
1844 /* 00 */
1845 { "addB", { Ebh1, Gb }, 0 },
1846 { "addS", { Evh1, Gv }, 0 },
1847 { "addB", { Gb, EbS }, 0 },
1848 { "addS", { Gv, EvS }, 0 },
1849 { "addB", { AL, Ib }, 0 },
1850 { "addS", { eAX, Iv }, 0 },
1851 { X86_64_TABLE (X86_64_06) },
1852 { X86_64_TABLE (X86_64_07) },
1853 /* 08 */
1854 { "orB", { Ebh1, Gb }, 0 },
1855 { "orS", { Evh1, Gv }, 0 },
1856 { "orB", { Gb, EbS }, 0 },
1857 { "orS", { Gv, EvS }, 0 },
1858 { "orB", { AL, Ib }, 0 },
1859 { "orS", { eAX, Iv }, 0 },
1860 { X86_64_TABLE (X86_64_0E) },
1861 { Bad_Opcode }, /* 0x0f extended opcode escape */
1862 /* 10 */
1863 { "adcB", { Ebh1, Gb }, 0 },
1864 { "adcS", { Evh1, Gv }, 0 },
1865 { "adcB", { Gb, EbS }, 0 },
1866 { "adcS", { Gv, EvS }, 0 },
1867 { "adcB", { AL, Ib }, 0 },
1868 { "adcS", { eAX, Iv }, 0 },
1869 { X86_64_TABLE (X86_64_16) },
1870 { X86_64_TABLE (X86_64_17) },
1871 /* 18 */
1872 { "sbbB", { Ebh1, Gb }, 0 },
1873 { "sbbS", { Evh1, Gv }, 0 },
1874 { "sbbB", { Gb, EbS }, 0 },
1875 { "sbbS", { Gv, EvS }, 0 },
1876 { "sbbB", { AL, Ib }, 0 },
1877 { "sbbS", { eAX, Iv }, 0 },
1878 { X86_64_TABLE (X86_64_1E) },
1879 { X86_64_TABLE (X86_64_1F) },
1880 /* 20 */
1881 { "andB", { Ebh1, Gb }, 0 },
1882 { "andS", { Evh1, Gv }, 0 },
1883 { "andB", { Gb, EbS }, 0 },
1884 { "andS", { Gv, EvS }, 0 },
1885 { "andB", { AL, Ib }, 0 },
1886 { "andS", { eAX, Iv }, 0 },
1887 { Bad_Opcode }, /* SEG ES prefix */
1888 { X86_64_TABLE (X86_64_27) },
1889 /* 28 */
1890 { "subB", { Ebh1, Gb }, 0 },
1891 { "subS", { Evh1, Gv }, 0 },
1892 { "subB", { Gb, EbS }, 0 },
1893 { "subS", { Gv, EvS }, 0 },
1894 { "subB", { AL, Ib }, 0 },
1895 { "subS", { eAX, Iv }, 0 },
1896 { Bad_Opcode }, /* SEG CS prefix */
1897 { X86_64_TABLE (X86_64_2F) },
1898 /* 30 */
1899 { "xorB", { Ebh1, Gb }, 0 },
1900 { "xorS", { Evh1, Gv }, 0 },
1901 { "xorB", { Gb, EbS }, 0 },
1902 { "xorS", { Gv, EvS }, 0 },
1903 { "xorB", { AL, Ib }, 0 },
1904 { "xorS", { eAX, Iv }, 0 },
1905 { Bad_Opcode }, /* SEG SS prefix */
1906 { X86_64_TABLE (X86_64_37) },
1907 /* 38 */
1908 { "cmpB", { Eb, Gb }, 0 },
1909 { "cmpS", { Ev, Gv }, 0 },
1910 { "cmpB", { Gb, EbS }, 0 },
1911 { "cmpS", { Gv, EvS }, 0 },
1912 { "cmpB", { AL, Ib }, 0 },
1913 { "cmpS", { eAX, Iv }, 0 },
1914 { Bad_Opcode }, /* SEG DS prefix */
1915 { X86_64_TABLE (X86_64_3F) },
1916 /* 40 */
1917 { "inc{S|}", { RMeAX }, 0 },
1918 { "inc{S|}", { RMeCX }, 0 },
1919 { "inc{S|}", { RMeDX }, 0 },
1920 { "inc{S|}", { RMeBX }, 0 },
1921 { "inc{S|}", { RMeSP }, 0 },
1922 { "inc{S|}", { RMeBP }, 0 },
1923 { "inc{S|}", { RMeSI }, 0 },
1924 { "inc{S|}", { RMeDI }, 0 },
1925 /* 48 */
1926 { "dec{S|}", { RMeAX }, 0 },
1927 { "dec{S|}", { RMeCX }, 0 },
1928 { "dec{S|}", { RMeDX }, 0 },
1929 { "dec{S|}", { RMeBX }, 0 },
1930 { "dec{S|}", { RMeSP }, 0 },
1931 { "dec{S|}", { RMeBP }, 0 },
1932 { "dec{S|}", { RMeSI }, 0 },
1933 { "dec{S|}", { RMeDI }, 0 },
1934 /* 50 */
1935 { "push!P", { RMrAX }, 0 },
1936 { "push!P", { RMrCX }, 0 },
1937 { "push!P", { RMrDX }, 0 },
1938 { "push!P", { RMrBX }, 0 },
1939 { "push!P", { RMrSP }, 0 },
1940 { "push!P", { RMrBP }, 0 },
1941 { "push!P", { RMrSI }, 0 },
1942 { "push!P", { RMrDI }, 0 },
1943 /* 58 */
1944 { "pop!P", { RMrAX }, 0 },
1945 { "pop!P", { RMrCX }, 0 },
1946 { "pop!P", { RMrDX }, 0 },
1947 { "pop!P", { RMrBX }, 0 },
1948 { "pop!P", { RMrSP }, 0 },
1949 { "pop!P", { RMrBP }, 0 },
1950 { "pop!P", { RMrSI }, 0 },
1951 { "pop!P", { RMrDI }, 0 },
1952 /* 60 */
1953 { X86_64_TABLE (X86_64_60) },
1954 { X86_64_TABLE (X86_64_61) },
1955 { X86_64_TABLE (X86_64_62) },
1956 { X86_64_TABLE (X86_64_63) },
1957 { Bad_Opcode }, /* seg fs */
1958 { Bad_Opcode }, /* seg gs */
1959 { Bad_Opcode }, /* op size prefix */
1960 { Bad_Opcode }, /* adr size prefix */
1961 /* 68 */
1962 { "pushP", { sIv }, 0 },
1963 { "imulS", { Gv, Ev, Iv }, 0 },
1964 { "pushP", { sIbT }, 0 },
1965 { "imulS", { Gv, Ev, sIb }, 0 },
1966 { "ins{b|}", { Ybr, indirDX }, 0 },
1967 { X86_64_TABLE (X86_64_6D) },
1968 { "outs{b|}", { indirDXr, Xb }, 0 },
1969 { X86_64_TABLE (X86_64_6F) },
1970 /* 70 */
1971 { "joH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1972 { "jnoH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1973 { "jbH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1974 { "jaeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1975 { "jeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1976 { "jneH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1977 { "jbeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1978 { "jaH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1979 /* 78 */
1980 { "jsH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1981 { "jnsH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1982 { "jpH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1983 { "jnpH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1984 { "jlH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1985 { "jgeH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1986 { "jleH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1987 { "jgH", { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1988 /* 80 */
1989 { REG_TABLE (REG_80) },
1990 { REG_TABLE (REG_81) },
1991 { X86_64_TABLE (X86_64_82) },
1992 { REG_TABLE (REG_83) },
1993 { "testB", { Eb, Gb }, 0 },
1994 { "testS", { Ev, Gv }, 0 },
1995 { "xchgB", { Ebh2, Gb }, 0 },
1996 { "xchgS", { Evh2, Gv }, 0 },
1997 /* 88 */
1998 { "movB", { Ebh3, Gb }, 0 },
1999 { "movS", { Evh3, Gv }, 0 },
2000 { "movB", { Gb, EbS }, 0 },
2001 { "movS", { Gv, EvS }, 0 },
2002 { "movD", { Sv, Sw }, 0 },
2003 { "leaS", { Gv, M }, 0 },
2004 { "movD", { Sw, Sv }, 0 },
2005 { REG_TABLE (REG_8F) },
2006 /* 90 */
2007 { PREFIX_TABLE (PREFIX_90) },
2008 { "xchgS", { RMeCX, eAX }, 0 },
2009 { "xchgS", { RMeDX, eAX }, 0 },
2010 { "xchgS", { RMeBX, eAX }, 0 },
2011 { "xchgS", { RMeSP, eAX }, 0 },
2012 { "xchgS", { RMeBP, eAX }, 0 },
2013 { "xchgS", { RMeSI, eAX }, 0 },
2014 { "xchgS", { RMeDI, eAX }, 0 },
2015 /* 98 */
2016 { "cW{t|}R", { XX }, 0 },
2017 { "cR{t|}O", { XX }, 0 },
2018 { X86_64_TABLE (X86_64_9A) },
2019 { Bad_Opcode }, /* fwait */
2020 { "pushfP", { XX }, 0 },
2021 { "popfP", { XX }, 0 },
2022 { "sahf", { XX }, 0 },
2023 { "lahf", { XX }, 0 },
2024 /* a0 */
2025 { "mov%LB", { AL, Ob }, PREFIX_REX2_ILLEGAL },
2026 { "mov%LS", { { JMPABS_Fixup, eAX_reg }, { JMPABS_Fixup, v_mode } }, PREFIX_REX2_ILLEGAL },
2027 { "mov%LB", { Ob, AL }, PREFIX_REX2_ILLEGAL },
2028 { "mov%LS", { Ov, eAX }, PREFIX_REX2_ILLEGAL },
2029 { "movs{b|}", { Ybr, Xb }, PREFIX_REX2_ILLEGAL },
2030 { "movs{R|}", { Yvr, Xv }, PREFIX_REX2_ILLEGAL },
2031 { "cmps{b|}", { Xb, Yb }, PREFIX_REX2_ILLEGAL },
2032 { "cmps{R|}", { Xv, Yv }, PREFIX_REX2_ILLEGAL },
2033 /* a8 */
2034 { "testB", { AL, Ib }, PREFIX_REX2_ILLEGAL },
2035 { "testS", { eAX, Iv }, PREFIX_REX2_ILLEGAL },
2036 { "stosB", { Ybr, AL }, PREFIX_REX2_ILLEGAL },
2037 { "stosS", { Yvr, eAX }, PREFIX_REX2_ILLEGAL },
2038 { "lodsB", { ALr, Xb }, PREFIX_REX2_ILLEGAL },
2039 { "lodsS", { eAXr, Xv }, PREFIX_REX2_ILLEGAL },
2040 { "scasB", { AL, Yb }, PREFIX_REX2_ILLEGAL },
2041 { "scasS", { eAX, Yv }, PREFIX_REX2_ILLEGAL },
2042 /* b0 */
2043 { "movB", { RMAL, Ib }, 0 },
2044 { "movB", { RMCL, Ib }, 0 },
2045 { "movB", { RMDL, Ib }, 0 },
2046 { "movB", { RMBL, Ib }, 0 },
2047 { "movB", { RMAH, Ib }, 0 },
2048 { "movB", { RMCH, Ib }, 0 },
2049 { "movB", { RMDH, Ib }, 0 },
2050 { "movB", { RMBH, Ib }, 0 },
2051 /* b8 */
2052 { "mov%LV", { RMeAX, Iv64 }, 0 },
2053 { "mov%LV", { RMeCX, Iv64 }, 0 },
2054 { "mov%LV", { RMeDX, Iv64 }, 0 },
2055 { "mov%LV", { RMeBX, Iv64 }, 0 },
2056 { "mov%LV", { RMeSP, Iv64 }, 0 },
2057 { "mov%LV", { RMeBP, Iv64 }, 0 },
2058 { "mov%LV", { RMeSI, Iv64 }, 0 },
2059 { "mov%LV", { RMeDI, Iv64 }, 0 },
2060 /* c0 */
2061 { REG_TABLE (REG_C0) },
2062 { REG_TABLE (REG_C1) },
2063 { X86_64_TABLE (X86_64_C2) },
2064 { X86_64_TABLE (X86_64_C3) },
2065 { X86_64_TABLE (X86_64_C4) },
2066 { X86_64_TABLE (X86_64_C5) },
2067 { REG_TABLE (REG_C6) },
2068 { REG_TABLE (REG_C7) },
2069 /* c8 */
2070 { "enterP", { Iw, Ib }, 0 },
2071 { "leaveP", { XX }, 0 },
2072 { "{l|}ret{|f}%LP", { Iw }, 0 },
2073 { "{l|}ret{|f}%LP", { XX }, 0 },
2074 { "int3", { XX }, 0 },
2075 { "int", { Ib }, 0 },
2076 { X86_64_TABLE (X86_64_CE) },
2077 { "iret%LP", { XX }, 0 },
2078 /* d0 */
2079 { REG_TABLE (REG_D0) },
2080 { REG_TABLE (REG_D1) },
2081 { REG_TABLE (REG_D2) },
2082 { REG_TABLE (REG_D3) },
2083 { X86_64_TABLE (X86_64_D4) },
2084 { X86_64_TABLE (X86_64_D5) },
2085 { Bad_Opcode },
2086 { "xlat", { DSBX }, 0 },
2087 /* d8 */
2088 { FLOAT },
2089 { FLOAT },
2090 { FLOAT },
2091 { FLOAT },
2092 { FLOAT },
2093 { FLOAT },
2094 { FLOAT },
2095 { FLOAT },
2096 /* e0 */
2097 { "loopneFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2098 { "loopeFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2099 { "loopFH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2100 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2101 { "inB", { AL, Ib }, PREFIX_REX2_ILLEGAL },
2102 { "inG", { zAX, Ib }, PREFIX_REX2_ILLEGAL },
2103 { "outB", { Ib, AL }, PREFIX_REX2_ILLEGAL },
2104 { "outG", { Ib, zAX }, PREFIX_REX2_ILLEGAL },
2105 /* e8 */
2106 { X86_64_TABLE (X86_64_E8) },
2107 { X86_64_TABLE (X86_64_E9) },
2108 { X86_64_TABLE (X86_64_EA) },
2109 { "jmp", { Jb, BND }, PREFIX_REX2_ILLEGAL },
2110 { "inB", { AL, indirDX }, PREFIX_REX2_ILLEGAL },
2111 { "inG", { zAX, indirDX }, PREFIX_REX2_ILLEGAL },
2112 { "outB", { indirDX, AL }, PREFIX_REX2_ILLEGAL },
2113 { "outG", { indirDX, zAX }, PREFIX_REX2_ILLEGAL },
2114 /* f0 */
2115 { Bad_Opcode }, /* lock prefix */
2116 { "int1", { XX }, 0 },
2117 { Bad_Opcode }, /* repne */
2118 { Bad_Opcode }, /* repz */
2119 { "hlt", { XX }, 0 },
2120 { "cmc", { XX }, 0 },
2121 { REG_TABLE (REG_F6) },
2122 { REG_TABLE (REG_F7) },
2123 /* f8 */
2124 { "clc", { XX }, 0 },
2125 { "stc", { XX }, 0 },
2126 { "cli", { XX }, 0 },
2127 { "sti", { XX }, 0 },
2128 { "cld", { XX }, 0 },
2129 { "std", { XX }, 0 },
2130 { REG_TABLE (REG_FE) },
2131 { REG_TABLE (REG_FF) },
2132 };
2133
2134 static const struct dis386 dis386_twobyte[] = {
2135 /* 00 */
2136 { REG_TABLE (REG_0F00 ) },
2137 { REG_TABLE (REG_0F01 ) },
2138 { "larS", { Gv, Sv }, 0 },
2139 { "lslS", { Gv, Sv }, 0 },
2140 { Bad_Opcode },
2141 { "syscall", { XX }, 0 },
2142 { "clts", { XX }, 0 },
2143 { "sysret%LQ", { XX }, 0 },
2144 /* 08 */
2145 { "invd", { XX }, 0 },
2146 { PREFIX_TABLE (PREFIX_0F09) },
2147 { Bad_Opcode },
2148 { "ud2", { XX }, 0 },
2149 { Bad_Opcode },
2150 { REG_TABLE (REG_0F0D) },
2151 { "femms", { XX }, 0 },
2152 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2153 /* 10 */
2154 { PREFIX_TABLE (PREFIX_0F10) },
2155 { PREFIX_TABLE (PREFIX_0F11) },
2156 { PREFIX_TABLE (PREFIX_0F12) },
2157 { "movlpX", { Mq, XM }, PREFIX_OPCODE },
2158 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2159 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2160 { PREFIX_TABLE (PREFIX_0F16) },
2161 { "movhpX", { Mq, XM }, PREFIX_OPCODE },
2162 /* 18 */
2163 { REG_TABLE (REG_0F18) },
2164 { "nopQ", { Ev }, 0 },
2165 { PREFIX_TABLE (PREFIX_0F1A) },
2166 { PREFIX_TABLE (PREFIX_0F1B) },
2167 { PREFIX_TABLE (PREFIX_0F1C) },
2168 { "nopQ", { Ev }, 0 },
2169 { PREFIX_TABLE (PREFIX_0F1E) },
2170 { "nopQ", { Ev }, 0 },
2171 /* 20 */
2172 { "movZ", { Em, Cm }, 0 },
2173 { "movZ", { Em, Dm }, 0 },
2174 { "movZ", { Cm, Em }, 0 },
2175 { "movZ", { Dm, Em }, 0 },
2176 { X86_64_TABLE (X86_64_0F24) },
2177 { Bad_Opcode },
2178 { X86_64_TABLE (X86_64_0F26) },
2179 { Bad_Opcode },
2180 /* 28 */
2181 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2182 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2183 { PREFIX_TABLE (PREFIX_0F2A) },
2184 { PREFIX_TABLE (PREFIX_0F2B) },
2185 { PREFIX_TABLE (PREFIX_0F2C) },
2186 { PREFIX_TABLE (PREFIX_0F2D) },
2187 { PREFIX_TABLE (PREFIX_0F2E) },
2188 { PREFIX_TABLE (PREFIX_0F2F) },
2189 /* 30 */
2190 { "wrmsr", { XX }, PREFIX_REX2_ILLEGAL },
2191 { "rdtsc", { XX }, PREFIX_REX2_ILLEGAL },
2192 { "rdmsr", { XX }, PREFIX_REX2_ILLEGAL },
2193 { "rdpmc", { XX }, PREFIX_REX2_ILLEGAL },
2194 { "sysenter", { SEP }, PREFIX_REX2_ILLEGAL },
2195 { "sysexit%LQ", { SEP }, PREFIX_REX2_ILLEGAL },
2196 { Bad_Opcode },
2197 { "getsec", { XX }, 0 },
2198 /* 38 */
2199 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2200 { Bad_Opcode },
2201 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2202 { Bad_Opcode },
2203 { Bad_Opcode },
2204 { Bad_Opcode },
2205 { Bad_Opcode },
2206 { Bad_Opcode },
2207 /* 40 */
2208 { "cmovoS", { Gv, Ev }, 0 },
2209 { "cmovnoS", { Gv, Ev }, 0 },
2210 { "cmovbS", { Gv, Ev }, 0 },
2211 { "cmovaeS", { Gv, Ev }, 0 },
2212 { "cmoveS", { Gv, Ev }, 0 },
2213 { "cmovneS", { Gv, Ev }, 0 },
2214 { "cmovbeS", { Gv, Ev }, 0 },
2215 { "cmovaS", { Gv, Ev }, 0 },
2216 /* 48 */
2217 { "cmovsS", { Gv, Ev }, 0 },
2218 { "cmovnsS", { Gv, Ev }, 0 },
2219 { "cmovpS", { Gv, Ev }, 0 },
2220 { "cmovnpS", { Gv, Ev }, 0 },
2221 { "cmovlS", { Gv, Ev }, 0 },
2222 { "cmovgeS", { Gv, Ev }, 0 },
2223 { "cmovleS", { Gv, Ev }, 0 },
2224 { "cmovgS", { Gv, Ev }, 0 },
2225 /* 50 */
2226 { "movmskpX", { Gdq, Ux }, PREFIX_OPCODE },
2227 { PREFIX_TABLE (PREFIX_0F51) },
2228 { PREFIX_TABLE (PREFIX_0F52) },
2229 { PREFIX_TABLE (PREFIX_0F53) },
2230 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2231 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2232 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2233 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2234 /* 58 */
2235 { PREFIX_TABLE (PREFIX_0F58) },
2236 { PREFIX_TABLE (PREFIX_0F59) },
2237 { PREFIX_TABLE (PREFIX_0F5A) },
2238 { PREFIX_TABLE (PREFIX_0F5B) },
2239 { PREFIX_TABLE (PREFIX_0F5C) },
2240 { PREFIX_TABLE (PREFIX_0F5D) },
2241 { PREFIX_TABLE (PREFIX_0F5E) },
2242 { PREFIX_TABLE (PREFIX_0F5F) },
2243 /* 60 */
2244 { PREFIX_TABLE (PREFIX_0F60) },
2245 { PREFIX_TABLE (PREFIX_0F61) },
2246 { PREFIX_TABLE (PREFIX_0F62) },
2247 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2248 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2249 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2250 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2251 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2252 /* 68 */
2253 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2254 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2255 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2256 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2257 { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2258 { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2259 { "movK", { MX, Edq }, PREFIX_OPCODE },
2260 { PREFIX_TABLE (PREFIX_0F6F) },
2261 /* 70 */
2262 { PREFIX_TABLE (PREFIX_0F70) },
2263 { REG_TABLE (REG_0F71) },
2264 { REG_TABLE (REG_0F72) },
2265 { REG_TABLE (REG_0F73) },
2266 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2267 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2268 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2269 { "emms", { XX }, PREFIX_OPCODE },
2270 /* 78 */
2271 { PREFIX_TABLE (PREFIX_0F78) },
2272 { PREFIX_TABLE (PREFIX_0F79) },
2273 { Bad_Opcode },
2274 { Bad_Opcode },
2275 { PREFIX_TABLE (PREFIX_0F7C) },
2276 { PREFIX_TABLE (PREFIX_0F7D) },
2277 { PREFIX_TABLE (PREFIX_0F7E) },
2278 { PREFIX_TABLE (PREFIX_0F7F) },
2279 /* 80 */
2280 { "joH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2281 { "jnoH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2282 { "jbH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2283 { "jaeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2284 { "jeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2285 { "jneH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2286 { "jbeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2287 { "jaH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2288 /* 88 */
2289 { "jsH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2290 { "jnsH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2291 { "jpH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2292 { "jnpH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2293 { "jlH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2294 { "jgeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2295 { "jleH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2296 { "jgH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2297 /* 90 */
2298 { "seto", { Eb }, 0 },
2299 { "setno", { Eb }, 0 },
2300 { "setb", { Eb }, 0 },
2301 { "setae", { Eb }, 0 },
2302 { "sete", { Eb }, 0 },
2303 { "setne", { Eb }, 0 },
2304 { "setbe", { Eb }, 0 },
2305 { "seta", { Eb }, 0 },
2306 /* 98 */
2307 { "sets", { Eb }, 0 },
2308 { "setns", { Eb }, 0 },
2309 { "setp", { Eb }, 0 },
2310 { "setnp", { Eb }, 0 },
2311 { "setl", { Eb }, 0 },
2312 { "setge", { Eb }, 0 },
2313 { "setle", { Eb }, 0 },
2314 { "setg", { Eb }, 0 },
2315 /* a0 */
2316 { "pushP", { fs }, 0 },
2317 { "popP", { fs }, 0 },
2318 { "cpuid", { XX }, 0 },
2319 { "btS", { Ev, Gv }, 0 },
2320 { "shldS", { Ev, Gv, Ib }, 0 },
2321 { "shldS", { Ev, Gv, CL }, 0 },
2322 { REG_TABLE (REG_0FA6) },
2323 { REG_TABLE (REG_0FA7) },
2324 /* a8 */
2325 { "pushP", { gs }, 0 },
2326 { "popP", { gs }, 0 },
2327 { "rsm", { XX }, 0 },
2328 { "btsS", { Evh1, Gv }, 0 },
2329 { "shrdS", { Ev, Gv, Ib }, 0 },
2330 { "shrdS", { Ev, Gv, CL }, 0 },
2331 { REG_TABLE (REG_0FAE) },
2332 { "imulS", { Gv, Ev }, 0 },
2333 /* b0 */
2334 { "cmpxchgB", { Ebh1, Gb }, 0 },
2335 { "cmpxchgS", { Evh1, Gv }, 0 },
2336 { "lssS", { Gv, Mp }, 0 },
2337 { "btrS", { Evh1, Gv }, 0 },
2338 { "lfsS", { Gv, Mp }, 0 },
2339 { "lgsS", { Gv, Mp }, 0 },
2340 { "movz{bR|x}", { Gv, Eb }, 0 },
2341 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2342 /* b8 */
2343 { PREFIX_TABLE (PREFIX_0FB8) },
2344 { "ud1S", { Gv, Ev }, 0 },
2345 { REG_TABLE (REG_0FBA) },
2346 { "btcS", { Evh1, Gv }, 0 },
2347 { PREFIX_TABLE (PREFIX_0FBC) },
2348 { PREFIX_TABLE (PREFIX_0FBD) },
2349 { "movs{bR|x}", { Gv, Eb }, 0 },
2350 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2351 /* c0 */
2352 { "xaddB", { Ebh1, Gb }, 0 },
2353 { "xaddS", { Evh1, Gv }, 0 },
2354 { PREFIX_TABLE (PREFIX_0FC2) },
2355 { "movntiS", { Mdq, Gdq }, PREFIX_OPCODE },
2356 { "pinsrw", { MX, Edw, Ib }, PREFIX_OPCODE },
2357 { "pextrw", { Gd, Nq, Ib }, PREFIX_OPCODE },
2358 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2359 { REG_TABLE (REG_0FC7) },
2360 /* c8 */
2361 { "bswap", { RMeAX }, 0 },
2362 { "bswap", { RMeCX }, 0 },
2363 { "bswap", { RMeDX }, 0 },
2364 { "bswap", { RMeBX }, 0 },
2365 { "bswap", { RMeSP }, 0 },
2366 { "bswap", { RMeBP }, 0 },
2367 { "bswap", { RMeSI }, 0 },
2368 { "bswap", { RMeDI }, 0 },
2369 /* d0 */
2370 { PREFIX_TABLE (PREFIX_0FD0) },
2371 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2372 { "psrld", { MX, EM }, PREFIX_OPCODE },
2373 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2374 { "paddq", { MX, EM }, PREFIX_OPCODE },
2375 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2376 { PREFIX_TABLE (PREFIX_0FD6) },
2377 { "pmovmskb", { Gdq, Nq }, PREFIX_OPCODE },
2378 /* d8 */
2379 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2380 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2381 { "pminub", { MX, EM }, PREFIX_OPCODE },
2382 { "pand", { MX, EM }, PREFIX_OPCODE },
2383 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2384 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2385 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2386 { "pandn", { MX, EM }, PREFIX_OPCODE },
2387 /* e0 */
2388 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2389 { "psraw", { MX, EM }, PREFIX_OPCODE },
2390 { "psrad", { MX, EM }, PREFIX_OPCODE },
2391 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2392 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2393 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2394 { PREFIX_TABLE (PREFIX_0FE6) },
2395 { PREFIX_TABLE (PREFIX_0FE7) },
2396 /* e8 */
2397 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2398 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2399 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2400 { "por", { MX, EM }, PREFIX_OPCODE },
2401 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2402 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2403 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2404 { "pxor", { MX, EM }, PREFIX_OPCODE },
2405 /* f0 */
2406 { PREFIX_TABLE (PREFIX_0FF0) },
2407 { "psllw", { MX, EM }, PREFIX_OPCODE },
2408 { "pslld", { MX, EM }, PREFIX_OPCODE },
2409 { "psllq", { MX, EM }, PREFIX_OPCODE },
2410 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2411 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2412 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2413 { PREFIX_TABLE (PREFIX_0FF7) },
2414 /* f8 */
2415 { "psubb", { MX, EM }, PREFIX_OPCODE },
2416 { "psubw", { MX, EM }, PREFIX_OPCODE },
2417 { "psubd", { MX, EM }, PREFIX_OPCODE },
2418 { "psubq", { MX, EM }, PREFIX_OPCODE },
2419 { "paddb", { MX, EM }, PREFIX_OPCODE },
2420 { "paddw", { MX, EM }, PREFIX_OPCODE },
2421 { "paddd", { MX, EM }, PREFIX_OPCODE },
2422 { "ud0S", { Gv, Ev }, 0 },
2423 };
2424
2425 static const bool onebyte_has_modrm[256] = {
2426 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2427 /* ------------------------------- */
2428 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2429 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2430 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2431 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2432 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2433 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2434 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2435 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2436 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2437 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2438 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2439 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2440 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2441 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2442 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2443 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2444 /* ------------------------------- */
2445 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2446 };
2447
2448 static const bool twobyte_has_modrm[256] = {
2449 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2450 /* ------------------------------- */
2451 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2452 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2453 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2454 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2455 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2456 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2457 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2458 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2459 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2460 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2461 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2462 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2463 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2464 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2465 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2466 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2467 /* ------------------------------- */
2468 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2469 };
2470
2471
2472 struct op
2473 {
2474 const char *name;
2475 unsigned int len;
2476 };
2477
2478 /* If we are accessing mod/rm/reg without need_modrm set, then the
2479 values are stale. Hitting this abort likely indicates that you
2480 need to update onebyte_has_modrm or twobyte_has_modrm. */
2481 #define MODRM_CHECK if (!ins->need_modrm) abort ()
2482
2483 static const char intel_index16[][6] = {
2484 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2485 };
2486
2487 static const char att_names64[][8] = {
2488 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2489 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
2490 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
2491 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
2492 };
2493 static const char att_names32[][8] = {
2494 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2495 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d",
2496 "%r16d", "%r17d", "%r18d", "%r19d", "%r20d", "%r21d", "%r22d", "%r23d",
2497 "%r24d", "%r25d", "%r26d", "%r27d", "%r28d", "%r29d", "%r30d", "%r31d",
2498 };
2499 static const char att_names16[][8] = {
2500 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2501 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w",
2502 "%r16w", "%r17w", "%r18w", "%r19w", "%r20w", "%r21w", "%r22w", "%r23w",
2503 "%r24w", "%r25w", "%r26w", "%r27w", "%r28w", "%r29w", "%r30w", "%r31w",
2504 };
2505 static const char att_names8[][8] = {
2506 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2507 };
2508 static const char att_names8rex[][8] = {
2509 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2510 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b",
2511 "%r16b", "%r17b", "%r18b", "%r19b", "%r20b", "%r21b", "%r22b", "%r23b",
2512 "%r24b", "%r25b", "%r26b", "%r27b", "%r28b", "%r29b", "%r30b", "%r31b",
2513 };
2514 static const char att_names_seg[][4] = {
2515 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2516 };
2517 static const char att_index64[] = "%riz";
2518 static const char att_index32[] = "%eiz";
2519 static const char att_index16[][8] = {
2520 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2521 };
2522
2523 static const char att_names_mm[][8] = {
2524 "%mm0", "%mm1", "%mm2", "%mm3",
2525 "%mm4", "%mm5", "%mm6", "%mm7"
2526 };
2527
2528 static const char att_names_bnd[][8] = {
2529 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2530 };
2531
2532 static const char att_names_xmm[][8] = {
2533 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2534 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2535 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2536 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2537 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2538 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2539 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2540 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2541 };
2542
2543 static const char att_names_ymm[][8] = {
2544 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2545 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2546 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2547 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2548 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2549 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2550 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2551 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2552 };
2553
2554 static const char att_names_zmm[][8] = {
2555 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2556 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2557 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2558 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2559 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2560 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2561 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2562 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2563 };
2564
2565 static const char att_names_tmm[][8] = {
2566 "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2567 "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2568 };
2569
2570 static const char att_names_mask[][8] = {
2571 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2572 };
2573
2574 static const char *const names_rounding[] =
2575 {
2576 "{rn-",
2577 "{rd-",
2578 "{ru-",
2579 "{rz-"
2580 };
2581
2582 static const struct dis386 reg_table[][8] = {
2583 /* REG_80 */
2584 {
2585 { "addA", { Ebh1, Ib }, 0 },
2586 { "orA", { Ebh1, Ib }, 0 },
2587 { "adcA", { Ebh1, Ib }, 0 },
2588 { "sbbA", { Ebh1, Ib }, 0 },
2589 { "andA", { Ebh1, Ib }, 0 },
2590 { "subA", { Ebh1, Ib }, 0 },
2591 { "xorA", { Ebh1, Ib }, 0 },
2592 { "cmpA", { Eb, Ib }, 0 },
2593 },
2594 /* REG_81 */
2595 {
2596 { "addQ", { Evh1, Iv }, 0 },
2597 { "orQ", { Evh1, Iv }, 0 },
2598 { "adcQ", { Evh1, Iv }, 0 },
2599 { "sbbQ", { Evh1, Iv }, 0 },
2600 { "andQ", { Evh1, Iv }, 0 },
2601 { "subQ", { Evh1, Iv }, 0 },
2602 { "xorQ", { Evh1, Iv }, 0 },
2603 { "cmpQ", { Ev, Iv }, 0 },
2604 },
2605 /* REG_83 */
2606 {
2607 { "addQ", { Evh1, sIb }, 0 },
2608 { "orQ", { Evh1, sIb }, 0 },
2609 { "adcQ", { Evh1, sIb }, 0 },
2610 { "sbbQ", { Evh1, sIb }, 0 },
2611 { "andQ", { Evh1, sIb }, 0 },
2612 { "subQ", { Evh1, sIb }, 0 },
2613 { "xorQ", { Evh1, sIb }, 0 },
2614 { "cmpQ", { Ev, sIb }, 0 },
2615 },
2616 /* REG_8F */
2617 {
2618 { "pop{P|}", { stackEv }, 0 },
2619 { XOP_8F_TABLE () },
2620 { Bad_Opcode },
2621 { Bad_Opcode },
2622 { Bad_Opcode },
2623 { XOP_8F_TABLE () },
2624 },
2625 /* REG_C0 */
2626 {
2627 { "rolA", { VexGb, Eb, Ib }, NO_PREFIX },
2628 { "rorA", { VexGb, Eb, Ib }, NO_PREFIX },
2629 { "rclA", { VexGb, Eb, Ib }, NO_PREFIX },
2630 { "rcrA", { VexGb, Eb, Ib }, NO_PREFIX },
2631 { "shlA", { VexGb, Eb, Ib }, NO_PREFIX },
2632 { "shrA", { VexGb, Eb, Ib }, NO_PREFIX },
2633 { "shlA", { VexGb, Eb, Ib }, NO_PREFIX },
2634 { "sarA", { VexGb, Eb, Ib }, NO_PREFIX },
2635 },
2636 /* REG_C1 */
2637 {
2638 { "rolQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2639 { "rorQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2640 { "rclQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2641 { "rcrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2642 { "shlQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2643 { "shrQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2644 { "shlQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2645 { "sarQ", { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2646 },
2647 /* REG_C6 */
2648 {
2649 { "movA", { Ebh3, Ib }, 0 },
2650 { Bad_Opcode },
2651 { Bad_Opcode },
2652 { Bad_Opcode },
2653 { Bad_Opcode },
2654 { Bad_Opcode },
2655 { Bad_Opcode },
2656 { RM_TABLE (RM_C6_REG_7) },
2657 },
2658 /* REG_C7 */
2659 {
2660 { "movQ", { Evh3, Iv }, 0 },
2661 { Bad_Opcode },
2662 { Bad_Opcode },
2663 { Bad_Opcode },
2664 { Bad_Opcode },
2665 { Bad_Opcode },
2666 { Bad_Opcode },
2667 { RM_TABLE (RM_C7_REG_7) },
2668 },
2669 /* REG_D0 */
2670 {
2671 { "rolA", { VexGb, Eb, I1 }, NO_PREFIX },
2672 { "rorA", { VexGb, Eb, I1 }, NO_PREFIX },
2673 { "rclA", { VexGb, Eb, I1 }, NO_PREFIX },
2674 { "rcrA", { VexGb, Eb, I1 }, NO_PREFIX },
2675 { "shlA", { VexGb, Eb, I1 }, NO_PREFIX },
2676 { "shrA", { VexGb, Eb, I1 }, NO_PREFIX },
2677 { "shlA", { VexGb, Eb, I1 }, NO_PREFIX },
2678 { "sarA", { VexGb, Eb, I1 }, NO_PREFIX },
2679 },
2680 /* REG_D1 */
2681 {
2682 { "rolQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2683 { "rorQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2684 { "rclQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2685 { "rcrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2686 { "shlQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2687 { "shrQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2688 { "shlQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2689 { "sarQ", { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2690 },
2691 /* REG_D2 */
2692 {
2693 { "rolA", { VexGb, Eb, CL }, NO_PREFIX },
2694 { "rorA", { VexGb, Eb, CL }, NO_PREFIX },
2695 { "rclA", { VexGb, Eb, CL }, NO_PREFIX },
2696 { "rcrA", { VexGb, Eb, CL }, NO_PREFIX },
2697 { "shlA", { VexGb, Eb, CL }, NO_PREFIX },
2698 { "shrA", { VexGb, Eb, CL }, NO_PREFIX },
2699 { "shlA", { VexGb, Eb, CL }, NO_PREFIX },
2700 { "sarA", { VexGb, Eb, CL }, NO_PREFIX },
2701 },
2702 /* REG_D3 */
2703 {
2704 { "rolQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2705 { "rorQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2706 { "rclQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2707 { "rcrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2708 { "shlQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2709 { "shrQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2710 { "shlQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2711 { "sarQ", { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2712 },
2713 /* REG_F6 */
2714 {
2715 { "testA", { Eb, Ib }, 0 },
2716 { "testA", { Eb, Ib }, 0 },
2717 { "notA", { Ebh1 }, 0 },
2718 { "negA", { Ebh1 }, 0 },
2719 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
2720 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
2721 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
2722 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
2723 },
2724 /* REG_F7 */
2725 {
2726 { "testQ", { Ev, Iv }, 0 },
2727 { "testQ", { Ev, Iv }, 0 },
2728 { "notQ", { Evh1 }, 0 },
2729 { "negQ", { Evh1 }, 0 },
2730 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
2731 { "imulQ", { Ev }, 0 },
2732 { "divQ", { Ev }, 0 },
2733 { "idivQ", { Ev }, 0 },
2734 },
2735 /* REG_FE */
2736 {
2737 { "incA", { Ebh1 }, 0 },
2738 { "decA", { Ebh1 }, 0 },
2739 },
2740 /* REG_FF */
2741 {
2742 { "incQ", { Evh1 }, 0 },
2743 { "decQ", { Evh1 }, 0 },
2744 { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2745 { "{l|}call^", { indirEp }, 0 },
2746 { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2747 { "{l|}jmp^", { indirEp }, 0 },
2748 { "push{P|}", { stackEv }, 0 },
2749 { Bad_Opcode },
2750 },
2751 /* REG_0F00 */
2752 {
2753 { "sldtD", { Sv }, 0 },
2754 { "strD", { Sv }, 0 },
2755 { "lldtD", { Sv }, 0 },
2756 { "ltrD", { Sv }, 0 },
2757 { "verrD", { Sv }, 0 },
2758 { "verwD", { Sv }, 0 },
2759 { X86_64_TABLE (X86_64_0F00_REG_6) },
2760 { Bad_Opcode },
2761 },
2762 /* REG_0F01 */
2763 {
2764 { MOD_TABLE (MOD_0F01_REG_0) },
2765 { MOD_TABLE (MOD_0F01_REG_1) },
2766 { MOD_TABLE (MOD_0F01_REG_2) },
2767 { MOD_TABLE (MOD_0F01_REG_3) },
2768 { "smswD", { Sv }, 0 },
2769 { MOD_TABLE (MOD_0F01_REG_5) },
2770 { "lmsw", { Ew }, 0 },
2771 { MOD_TABLE (MOD_0F01_REG_7) },
2772 },
2773 /* REG_0F0D */
2774 {
2775 { "prefetch", { Mb }, 0 },
2776 { "prefetchw", { Mb }, 0 },
2777 { "prefetchwt1", { Mb }, 0 },
2778 { "prefetch", { Mb }, 0 },
2779 { "prefetch", { Mb }, 0 },
2780 { "prefetch", { Mb }, 0 },
2781 { "prefetch", { Mb }, 0 },
2782 { "prefetch", { Mb }, 0 },
2783 },
2784 /* REG_0F18 */
2785 {
2786 { MOD_TABLE (MOD_0F18_REG_0) },
2787 { MOD_TABLE (MOD_0F18_REG_1) },
2788 { MOD_TABLE (MOD_0F18_REG_2) },
2789 { MOD_TABLE (MOD_0F18_REG_3) },
2790 { "nopQ", { Ev }, 0 },
2791 { "nopQ", { Ev }, 0 },
2792 { MOD_TABLE (MOD_0F18_REG_6) },
2793 { MOD_TABLE (MOD_0F18_REG_7) },
2794 },
2795 /* REG_0F1C_P_0_MOD_0 */
2796 {
2797 { "cldemote", { Mb }, 0 },
2798 { "nopQ", { Ev }, 0 },
2799 { "nopQ", { Ev }, 0 },
2800 { "nopQ", { Ev }, 0 },
2801 { "nopQ", { Ev }, 0 },
2802 { "nopQ", { Ev }, 0 },
2803 { "nopQ", { Ev }, 0 },
2804 { "nopQ", { Ev }, 0 },
2805 },
2806 /* REG_0F1E_P_1_MOD_3 */
2807 {
2808 { "nopQ", { Ev }, PREFIX_IGNORED },
2809 { "rdsspK", { Edq }, 0 },
2810 { "nopQ", { Ev }, PREFIX_IGNORED },
2811 { "nopQ", { Ev }, PREFIX_IGNORED },
2812 { "nopQ", { Ev }, PREFIX_IGNORED },
2813 { "nopQ", { Ev }, PREFIX_IGNORED },
2814 { "nopQ", { Ev }, PREFIX_IGNORED },
2815 { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2816 },
2817 /* REG_0F38D8_PREFIX_1 */
2818 {
2819 { "aesencwide128kl", { M }, 0 },
2820 { "aesdecwide128kl", { M }, 0 },
2821 { "aesencwide256kl", { M }, 0 },
2822 { "aesdecwide256kl", { M }, 0 },
2823 },
2824 /* REG_0F3A0F_P_1 */
2825 {
2826 { RM_TABLE (RM_0F3A0F_P_1_R_0) },
2827 },
2828 /* REG_0F71 */
2829 {
2830 { Bad_Opcode },
2831 { Bad_Opcode },
2832 { "psrlw", { Nq, Ib }, PREFIX_OPCODE },
2833 { Bad_Opcode },
2834 { "psraw", { Nq, Ib }, PREFIX_OPCODE },
2835 { Bad_Opcode },
2836 { "psllw", { Nq, Ib }, PREFIX_OPCODE },
2837 },
2838 /* REG_0F72 */
2839 {
2840 { Bad_Opcode },
2841 { Bad_Opcode },
2842 { "psrld", { Nq, Ib }, PREFIX_OPCODE },
2843 { Bad_Opcode },
2844 { "psrad", { Nq, Ib }, PREFIX_OPCODE },
2845 { Bad_Opcode },
2846 { "pslld", { Nq, Ib }, PREFIX_OPCODE },
2847 },
2848 /* REG_0F73 */
2849 {
2850 { Bad_Opcode },
2851 { Bad_Opcode },
2852 { "psrlq", { Nq, Ib }, PREFIX_OPCODE },
2853 { "psrldq", { Ux, Ib }, PREFIX_DATA },
2854 { Bad_Opcode },
2855 { Bad_Opcode },
2856 { "psllq", { Nq, Ib }, PREFIX_OPCODE },
2857 { "pslldq", { Ux, Ib }, PREFIX_DATA },
2858 },
2859 /* REG_0FA6 */
2860 {
2861 { "montmul", { { OP_0f07, 0 } }, 0 },
2862 { "xsha1", { { OP_0f07, 0 } }, 0 },
2863 { "xsha256", { { OP_0f07, 0 } }, 0 },
2864 },
2865 /* REG_0FA7 */
2866 {
2867 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
2868 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
2869 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
2870 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
2871 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
2872 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
2873 },
2874 /* REG_0FAE */
2875 {
2876 { MOD_TABLE (MOD_0FAE_REG_0) },
2877 { MOD_TABLE (MOD_0FAE_REG_1) },
2878 { MOD_TABLE (MOD_0FAE_REG_2) },
2879 { MOD_TABLE (MOD_0FAE_REG_3) },
2880 { MOD_TABLE (MOD_0FAE_REG_4) },
2881 { MOD_TABLE (MOD_0FAE_REG_5) },
2882 { MOD_TABLE (MOD_0FAE_REG_6) },
2883 { MOD_TABLE (MOD_0FAE_REG_7) },
2884 },
2885 /* REG_0FBA */
2886 {
2887 { Bad_Opcode },
2888 { Bad_Opcode },
2889 { Bad_Opcode },
2890 { Bad_Opcode },
2891 { "btQ", { Ev, Ib }, 0 },
2892 { "btsQ", { Evh1, Ib }, 0 },
2893 { "btrQ", { Evh1, Ib }, 0 },
2894 { "btcQ", { Evh1, Ib }, 0 },
2895 },
2896 /* REG_0FC7 */
2897 {
2898 { Bad_Opcode },
2899 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2900 { Bad_Opcode },
2901 { "xrstors", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2902 { "xsavec", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2903 { "xsaves", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2904 { MOD_TABLE (MOD_0FC7_REG_6) },
2905 { MOD_TABLE (MOD_0FC7_REG_7) },
2906 },
2907 /* REG_VEX_0F71 */
2908 {
2909 { Bad_Opcode },
2910 { Bad_Opcode },
2911 { "vpsrlw", { Vex, Ux, Ib }, PREFIX_DATA },
2912 { Bad_Opcode },
2913 { "vpsraw", { Vex, Ux, Ib }, PREFIX_DATA },
2914 { Bad_Opcode },
2915 { "vpsllw", { Vex, Ux, Ib }, PREFIX_DATA },
2916 },
2917 /* REG_VEX_0F72 */
2918 {
2919 { Bad_Opcode },
2920 { Bad_Opcode },
2921 { "vpsrld", { Vex, Ux, Ib }, PREFIX_DATA },
2922 { Bad_Opcode },
2923 { "vpsrad", { Vex, Ux, Ib }, PREFIX_DATA },
2924 { Bad_Opcode },
2925 { "vpslld", { Vex, Ux, Ib }, PREFIX_DATA },
2926 },
2927 /* REG_VEX_0F73 */
2928 {
2929 { Bad_Opcode },
2930 { Bad_Opcode },
2931 { "vpsrlq", { Vex, Ux, Ib }, PREFIX_DATA },
2932 { "vpsrldq", { Vex, Ux, Ib }, PREFIX_DATA },
2933 { Bad_Opcode },
2934 { Bad_Opcode },
2935 { "vpsllq", { Vex, Ux, Ib }, PREFIX_DATA },
2936 { "vpslldq", { Vex, Ux, Ib }, PREFIX_DATA },
2937 },
2938 /* REG_VEX_0FAE */
2939 {
2940 { Bad_Opcode },
2941 { Bad_Opcode },
2942 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2) },
2943 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3) },
2944 },
2945 /* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */
2946 {
2947 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) },
2948 },
2949 /* REG_VEX_0F38F3_L_0_P_0 */
2950 {
2951 { Bad_Opcode },
2952 { "blsrS", { VexGdq, Edq }, 0 },
2953 { "blsmskS", { VexGdq, Edq }, 0 },
2954 { "blsiS", { VexGdq, Edq }, 0 },
2955 },
2956 /* REG_VEX_MAP7_F8_L_0_W_0 */
2957 {
2958 { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) },
2959 },
2960 /* REG_XOP_09_01_L_0 */
2961 {
2962 { Bad_Opcode },
2963 { "blcfill", { VexGdq, Edq }, 0 },
2964 { "blsfill", { VexGdq, Edq }, 0 },
2965 { "blcs", { VexGdq, Edq }, 0 },
2966 { "tzmsk", { VexGdq, Edq }, 0 },
2967 { "blcic", { VexGdq, Edq }, 0 },
2968 { "blsic", { VexGdq, Edq }, 0 },
2969 { "t1mskc", { VexGdq, Edq }, 0 },
2970 },
2971 /* REG_XOP_09_02_L_0 */
2972 {
2973 { Bad_Opcode },
2974 { "blcmsk", { VexGdq, Edq }, 0 },
2975 { Bad_Opcode },
2976 { Bad_Opcode },
2977 { Bad_Opcode },
2978 { Bad_Opcode },
2979 { "blci", { VexGdq, Edq }, 0 },
2980 },
2981 /* REG_XOP_09_12_L_0 */
2982 {
2983 { "llwpcb", { Rdq }, 0 },
2984 { "slwpcb", { Rdq }, 0 },
2985 },
2986 /* REG_XOP_0A_12_L_0 */
2987 {
2988 { "lwpins", { VexGdq, Ed, Id }, 0 },
2989 { "lwpval", { VexGdq, Ed, Id }, 0 },
2990 },
2991
2992 #include "i386-dis-evex-reg.h"
2993 };
2994
2995 static const struct dis386 prefix_table[][4] = {
2996 /* PREFIX_90 */
2997 {
2998 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2999 { "pause", { XX }, 0 },
3000 { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
3001 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3002 },
3003
3004 /* PREFIX_0F00_REG_6_X86_64 */
3005 {
3006 { Bad_Opcode },
3007 { Bad_Opcode },
3008 { Bad_Opcode },
3009 { "lkgsD", { Sv }, 0 },
3010 },
3011
3012 /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
3013 {
3014 { "wrmsrns", { Skip_MODRM }, 0 },
3015 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
3016 { Bad_Opcode },
3017 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
3018 },
3019
3020 /* PREFIX_0F01_REG_0_MOD_3_RM_7 */
3021 {
3022 { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_7_P_0) },
3023 },
3024
3025 /* PREFIX_0F01_REG_1_RM_2 */
3026 {
3027 { "clac", { Skip_MODRM }, 0 },
3028 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) },
3029 { Bad_Opcode },
3030 { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)},
3031 },
3032
3033 /* PREFIX_0F01_REG_1_RM_4 */
3034 {
3035 { Bad_Opcode },
3036 { Bad_Opcode },
3037 { "tdcall", { Skip_MODRM }, 0 },
3038 { Bad_Opcode },
3039 },
3040
3041 /* PREFIX_0F01_REG_1_RM_5 */
3042 {
3043 { Bad_Opcode },
3044 { Bad_Opcode },
3045 { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3046 { Bad_Opcode },
3047 },
3048
3049 /* PREFIX_0F01_REG_1_RM_6 */
3050 {
3051 { Bad_Opcode },
3052 { Bad_Opcode },
3053 { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3054 { Bad_Opcode },
3055 },
3056
3057 /* PREFIX_0F01_REG_1_RM_7 */
3058 {
3059 { "encls", { Skip_MODRM }, 0 },
3060 { Bad_Opcode },
3061 { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3062 { Bad_Opcode },
3063 },
3064
3065 /* PREFIX_0F01_REG_3_RM_1 */
3066 {
3067 { "vmmcall", { Skip_MODRM }, 0 },
3068 { "vmgexit", { Skip_MODRM }, 0 },
3069 { Bad_Opcode },
3070 { "vmgexit", { Skip_MODRM }, 0 },
3071 },
3072
3073 /* PREFIX_0F01_REG_5_MOD_0 */
3074 {
3075 { Bad_Opcode },
3076 { "rstorssp", { Mq }, PREFIX_OPCODE },
3077 },
3078
3079 /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3080 {
3081 { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
3082 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3083 { Bad_Opcode },
3084 { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3085 },
3086
3087 /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3088 {
3089 { Bad_Opcode },
3090 { Bad_Opcode },
3091 { Bad_Opcode },
3092 { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
3093 },
3094
3095 /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3096 {
3097 { Bad_Opcode },
3098 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3099 },
3100
3101 /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3102 {
3103 { Bad_Opcode },
3104 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3105 },
3106
3107 /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3108 {
3109 { Bad_Opcode },
3110 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3111 },
3112
3113 /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3114 {
3115 { "rdpkru", { Skip_MODRM }, 0 },
3116 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3117 },
3118
3119 /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3120 {
3121 { "wrpkru", { Skip_MODRM }, 0 },
3122 { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3123 },
3124
3125 /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3126 {
3127 { "monitorx", { { OP_Monitor, 0 } }, 0 },
3128 { "mcommit", { Skip_MODRM }, 0 },
3129 },
3130
3131 /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
3132 {
3133 { "rdpru", { Skip_MODRM }, 0 },
3134 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
3135 },
3136
3137 /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3138 {
3139 { "invlpgb", { Skip_MODRM }, 0 },
3140 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3141 { Bad_Opcode },
3142 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3143 },
3144
3145 /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3146 {
3147 { "tlbsync", { Skip_MODRM }, 0 },
3148 { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3149 { Bad_Opcode },
3150 { "pvalidate", { Skip_MODRM }, 0 },
3151 },
3152
3153 /* PREFIX_0F09 */
3154 {
3155 { "wbinvd", { XX }, 0 },
3156 { "wbnoinvd", { XX }, 0 },
3157 },
3158
3159 /* PREFIX_0F10 */
3160 {
3161 { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 },
3162 { "%XEVmovs%XS", { XMScalar, VexScalarR, EXd }, 0 },
3163 { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 },
3164 { "%XEVmovs%XD", { XMScalar, VexScalarR, EXq }, 0 },
3165 },
3166
3167 /* PREFIX_0F11 */
3168 {
3169 { "%XEVmovupX", { EXxS, XM }, 0 },
3170 { "%XEVmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 },
3171 { "%XEVmovupX", { EXxS, XM }, 0 },
3172 { "%XEVmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 },
3173 },
3174
3175 /* PREFIX_0F12 */
3176 {
3177 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3178 { "movsldup", { XM, EXx }, 0 },
3179 { "%XEVmovlpYX", { XM, Vex, Mq }, 0 },
3180 { "movddup", { XM, EXq }, 0 },
3181 },
3182
3183 /* PREFIX_0F16 */
3184 {
3185 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3186 { "movshdup", { XM, EXx }, 0 },
3187 { "%XEVmovhpYX", { XM, Vex, Mq }, 0 },
3188 },
3189
3190 /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3191 {
3192 { "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 },
3193 { "nopQ", { Ev }, 0 },
3194 { "nopQ", { Ev }, 0 },
3195 { "nopQ", { Ev }, 0 },
3196 },
3197
3198 /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3199 {
3200 { "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 },
3201 { "nopQ", { Ev }, 0 },
3202 { "nopQ", { Ev }, 0 },
3203 { "nopQ", { Ev }, 0 },
3204 },
3205
3206 /* PREFIX_0F1A */
3207 {
3208 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3209 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3210 { "bndmov", { Gbnd, Ebnd }, 0 },
3211 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3212 },
3213
3214 /* PREFIX_0F1B */
3215 {
3216 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3217 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3218 { "bndmov", { EbndS, Gbnd }, 0 },
3219 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3220 },
3221
3222 /* PREFIX_0F1C */
3223 {
3224 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3225 { "nopQ", { Ev }, PREFIX_IGNORED },
3226 { "nopQ", { Ev }, 0 },
3227 { "nopQ", { Ev }, PREFIX_IGNORED },
3228 },
3229
3230 /* PREFIX_0F1E */
3231 {
3232 { "nopQ", { Ev }, 0 },
3233 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3234 { "nopQ", { Ev }, 0 },
3235 { NULL, { XX }, PREFIX_IGNORED },
3236 },
3237
3238 /* PREFIX_0F2A */
3239 {
3240 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3241 { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3242 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3243 { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3244 },
3245
3246 /* PREFIX_0F2B */
3247 {
3248 { "movntps", { Mx, XM }, 0 },
3249 { "movntss", { Md, XM }, 0 },
3250 { "movntpd", { Mx, XM }, 0 },
3251 { "movntsd", { Mq, XM }, 0 },
3252 },
3253
3254 /* PREFIX_0F2C */
3255 {
3256 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3257 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3258 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3259 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3260 },
3261
3262 /* PREFIX_0F2D */
3263 {
3264 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3265 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3266 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3267 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3268 },
3269
3270 /* PREFIX_0F2E */
3271 {
3272 { "%XEVucomisYX", { XMScalar, EXd, EXxEVexS }, 0 },
3273 { Bad_Opcode },
3274 { "%XEVucomisYX", { XMScalar, EXq, EXxEVexS }, 0 },
3275 },
3276
3277 /* PREFIX_0F2F */
3278 {
3279 { "%XEVcomisYX", { XMScalar, EXd, EXxEVexS }, 0 },
3280 { Bad_Opcode },
3281 { "%XEVcomisYX", { XMScalar, EXq, EXxEVexS }, 0 },
3282 },
3283
3284 /* PREFIX_0F51 */
3285 {
3286 { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3287 { "%XEVsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3288 { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 },
3289 { "%XEVsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3290 },
3291
3292 /* PREFIX_0F52 */
3293 {
3294 { "Vrsqrtps", { XM, EXx }, 0 },
3295 { "Vrsqrtss", { XMScalar, VexScalar, EXd }, 0 },
3296 },
3297
3298 /* PREFIX_0F53 */
3299 {
3300 { "Vrcpps", { XM, EXx }, 0 },
3301 { "Vrcpss", { XMScalar, VexScalar, EXd }, 0 },
3302 },
3303
3304 /* PREFIX_0F58 */
3305 {
3306 { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3307 { "%XEVadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3308 { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3309 { "%XEVadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3310 },
3311
3312 /* PREFIX_0F59 */
3313 {
3314 { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3315 { "%XEVmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3316 { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3317 { "%XEVmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3318 },
3319
3320 /* PREFIX_0F5A */
3321 {
3322 { "%XEVcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3323 { "%XEVcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3324 { "%XEVcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3325 { "%XEVcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3326 },
3327
3328 /* PREFIX_0F5B */
3329 {
3330 { "Vcvtdq2ps", { XM, EXx }, 0 },
3331 { "Vcvttps2dq", { XM, EXx }, 0 },
3332 { "Vcvtps2dq", { XM, EXx }, 0 },
3333 },
3334
3335 /* PREFIX_0F5C */
3336 {
3337 { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3338 { "%XEVsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3339 { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3340 { "%XEVsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3341 },
3342
3343 /* PREFIX_0F5D */
3344 {
3345 { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3346 { "%XEVmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3347 { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3348 { "%XEVmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3349 },
3350
3351 /* PREFIX_0F5E */
3352 {
3353 { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3354 { "%XEVdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3355 { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 },
3356 { "%XEVdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3357 },
3358
3359 /* PREFIX_0F5F */
3360 {
3361 { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3362 { "%XEVmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3363 { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 },
3364 { "%XEVmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3365 },
3366
3367 /* PREFIX_0F60 */
3368 {
3369 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3370 { Bad_Opcode },
3371 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3372 },
3373
3374 /* PREFIX_0F61 */
3375 {
3376 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3377 { Bad_Opcode },
3378 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3379 },
3380
3381 /* PREFIX_0F62 */
3382 {
3383 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3384 { Bad_Opcode },
3385 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3386 },
3387
3388 /* PREFIX_0F6F */
3389 {
3390 { "movq", { MX, EM }, PREFIX_OPCODE },
3391 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3392 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3393 },
3394
3395 /* PREFIX_0F70 */
3396 {
3397 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3398 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3399 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3400 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3401 },
3402
3403 /* PREFIX_0F78 */
3404 {
3405 {"vmread", { Em, Gm }, 0 },
3406 { Bad_Opcode },
3407 {"extrq", { Uxmm, Ib, Ib }, 0 },
3408 {"insertq", { XM, Uxmm, Ib, Ib }, 0 },
3409 },
3410
3411 /* PREFIX_0F79 */
3412 {
3413 {"vmwrite", { Gm, Em }, 0 },
3414 { Bad_Opcode },
3415 {"extrq", { XM, Uxmm }, 0 },
3416 {"insertq", { XM, Uxmm }, 0 },
3417 },
3418
3419 /* PREFIX_0F7C */
3420 {
3421 { Bad_Opcode },
3422 { Bad_Opcode },
3423 { "Vhaddpd", { XM, Vex, EXx }, 0 },
3424 { "Vhaddps", { XM, Vex, EXx }, 0 },
3425 },
3426
3427 /* PREFIX_0F7D */
3428 {
3429 { Bad_Opcode },
3430 { Bad_Opcode },
3431 { "Vhsubpd", { XM, Vex, EXx }, 0 },
3432 { "Vhsubps", { XM, Vex, EXx }, 0 },
3433 },
3434
3435 /* PREFIX_0F7E */
3436 {
3437 { "movK", { Edq, MX }, PREFIX_OPCODE },
3438 { "movq", { XM, EXq }, PREFIX_OPCODE },
3439 { "movK", { Edq, XM }, PREFIX_OPCODE },
3440 },
3441
3442 /* PREFIX_0F7F */
3443 {
3444 { "movq", { EMS, MX }, PREFIX_OPCODE },
3445 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3446 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3447 },
3448
3449 /* PREFIX_0FAE_REG_0_MOD_3 */
3450 {
3451 { Bad_Opcode },
3452 { "rdfsbase", { Ev }, 0 },
3453 },
3454
3455 /* PREFIX_0FAE_REG_1_MOD_3 */
3456 {
3457 { Bad_Opcode },
3458 { "rdgsbase", { Ev }, 0 },
3459 },
3460
3461 /* PREFIX_0FAE_REG_2_MOD_3 */
3462 {
3463 { Bad_Opcode },
3464 { "wrfsbase", { Ev }, 0 },
3465 },
3466
3467 /* PREFIX_0FAE_REG_3_MOD_3 */
3468 {
3469 { Bad_Opcode },
3470 { "wrgsbase", { Ev }, 0 },
3471 },
3472
3473 /* PREFIX_0FAE_REG_4_MOD_0 */
3474 {
3475 { "xsave", { FXSAVE }, PREFIX_REX2_ILLEGAL },
3476 { "ptwrite{%LQ|}", { Edq }, 0 },
3477 },
3478
3479 /* PREFIX_0FAE_REG_4_MOD_3 */
3480 {
3481 { Bad_Opcode },
3482 { "ptwrite{%LQ|}", { Edq }, 0 },
3483 },
3484
3485 /* PREFIX_0FAE_REG_5_MOD_3 */
3486 {
3487 { "lfence", { Skip_MODRM }, 0 },
3488 { "incsspK", { Edq }, PREFIX_OPCODE },
3489 },
3490
3491 /* PREFIX_0FAE_REG_6_MOD_0 */
3492 {
3493 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
3494 { "clrssbsy", { Mq }, PREFIX_OPCODE },
3495 { "clwb", { Mb }, PREFIX_OPCODE },
3496 },
3497
3498 /* PREFIX_0FAE_REG_6_MOD_3 */
3499 {
3500 { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3501 { "umonitor", { Eva }, PREFIX_OPCODE },
3502 { "tpause", { Edq }, PREFIX_OPCODE },
3503 { "umwait", { Edq }, PREFIX_OPCODE },
3504 },
3505
3506 /* PREFIX_0FAE_REG_7_MOD_0 */
3507 {
3508 { "clflush", { Mb }, 0 },
3509 { Bad_Opcode },
3510 { "clflushopt", { Mb }, 0 },
3511 },
3512
3513 /* PREFIX_0FB8 */
3514 {
3515 { Bad_Opcode },
3516 { "popcntS", { Gv, Ev }, 0 },
3517 },
3518
3519 /* PREFIX_0FBC */
3520 {
3521 { "bsfS", { Gv, Ev }, 0 },
3522 { "tzcntS", { Gv, Ev }, 0 },
3523 { "bsfS", { Gv, Ev }, 0 },
3524 },
3525
3526 /* PREFIX_0FBD */
3527 {
3528 { "bsrS", { Gv, Ev }, 0 },
3529 { "lzcntS", { Gv, Ev }, 0 },
3530 { "bsrS", { Gv, Ev }, 0 },
3531 },
3532
3533 /* PREFIX_0FC2 */
3534 {
3535 { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3536 { "Vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
3537 { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3538 { "Vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
3539 },
3540
3541 /* PREFIX_0FC7_REG_6_MOD_0 */
3542 {
3543 { "vmptrld",{ Mq }, 0 },
3544 { "vmxon", { Mq }, 0 },
3545 { "vmclear",{ Mq }, 0 },
3546 },
3547
3548 /* PREFIX_0FC7_REG_6_MOD_3 */
3549 {
3550 { "rdrand", { Ev }, 0 },
3551 { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3552 { "rdrand", { Ev }, 0 }
3553 },
3554
3555 /* PREFIX_0FC7_REG_7_MOD_3 */
3556 {
3557 { "rdseed", { Ev }, 0 },
3558 { "rdpid", { Em }, 0 },
3559 { "rdseed", { Ev }, 0 },
3560 },
3561
3562 /* PREFIX_0FD0 */
3563 {
3564 { Bad_Opcode },
3565 { Bad_Opcode },
3566 { "VaddsubpX", { XM, Vex, EXx }, 0 },
3567 { "VaddsubpX", { XM, Vex, EXx }, 0 },
3568 },
3569
3570 /* PREFIX_0FD6 */
3571 {
3572 { Bad_Opcode },
3573 { "movq2dq",{ XM, Nq }, 0 },
3574 { "movq", { EXqS, XM }, 0 },
3575 { "movdq2q",{ MX, Ux }, 0 },
3576 },
3577
3578 /* PREFIX_0FE6 */
3579 {
3580 { Bad_Opcode },
3581 { "Vcvtdq2pd", { XM, EXxmmq }, 0 },
3582 { "Vcvttpd2dq%XY", { XMM, EXx }, 0 },
3583 { "Vcvtpd2dq%XY", { XMM, EXx }, 0 },
3584 },
3585
3586 /* PREFIX_0FE7 */
3587 {
3588 { "movntq", { Mq, MX }, 0 },
3589 { Bad_Opcode },
3590 { "movntdq", { Mx, XM }, 0 },
3591 },
3592
3593 /* PREFIX_0FF0 */
3594 {
3595 { Bad_Opcode },
3596 { Bad_Opcode },
3597 { Bad_Opcode },
3598 { "Vlddqu", { XM, M }, 0 },
3599 },
3600
3601 /* PREFIX_0FF7 */
3602 {
3603 { "maskmovq", { MX, Nq }, PREFIX_OPCODE },
3604 { Bad_Opcode },
3605 { "maskmovdqu", { XM, Ux }, PREFIX_OPCODE },
3606 },
3607
3608 /* PREFIX_0F38D8 */
3609 {
3610 { Bad_Opcode },
3611 { REG_TABLE (REG_0F38D8_PREFIX_1) },
3612 },
3613
3614 /* PREFIX_0F38DC */
3615 {
3616 { Bad_Opcode },
3617 { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3618 { "aesenc", { XM, EXx }, 0 },
3619 },
3620
3621 /* PREFIX_0F38DD */
3622 {
3623 { Bad_Opcode },
3624 { "aesdec128kl", { XM, M }, 0 },
3625 { "aesenclast", { XM, EXx }, 0 },
3626 },
3627
3628 /* PREFIX_0F38DE */
3629 {
3630 { Bad_Opcode },
3631 { "aesenc256kl", { XM, M }, 0 },
3632 { "aesdec", { XM, EXx }, 0 },
3633 },
3634
3635 /* PREFIX_0F38DF */
3636 {
3637 { Bad_Opcode },
3638 { "aesdec256kl", { XM, M }, 0 },
3639 { "aesdeclast", { XM, EXx }, 0 },
3640 },
3641
3642 /* PREFIX_0F38F0 */
3643 {
3644 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3645 { Bad_Opcode },
3646 { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3647 { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3648 },
3649
3650 /* PREFIX_0F38F1 */
3651 {
3652 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3653 { Bad_Opcode },
3654 { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3655 { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3656 },
3657
3658 /* PREFIX_0F38F6 */
3659 {
3660 { "wrssK", { M, Gdq }, 0 },
3661 { "adoxL", { VexGdq, Gdq, Edq }, 0 },
3662 { "adcxL", { VexGdq, Gdq, Edq }, 0 },
3663 { Bad_Opcode },
3664 },
3665
3666 /* PREFIX_0F38F8_M_0 */
3667 {
3668 { Bad_Opcode },
3669 { "enqcmds", { Gva, M }, 0 },
3670 { "movdir64b", { Gva, M }, 0 },
3671 { "enqcmd", { Gva, M }, 0 },
3672 },
3673
3674 /* PREFIX_0F38F8_M_1_X86_64 */
3675 {
3676 { Bad_Opcode },
3677 { "uwrmsr", { Gq, Rq }, 0 },
3678 { Bad_Opcode },
3679 { "urdmsr", { Rq, Gq }, 0 },
3680 },
3681
3682 /* PREFIX_0F38FA */
3683 {
3684 { Bad_Opcode },
3685 { "encodekey128", { Gd, Rd }, 0 },
3686 },
3687
3688 /* PREFIX_0F38FB */
3689 {
3690 { Bad_Opcode },
3691 { "encodekey256", { Gd, Rd }, 0 },
3692 },
3693
3694 /* PREFIX_0F38FC */
3695 {
3696 { "aadd", { Mdq, Gdq }, 0 },
3697 { "axor", { Mdq, Gdq }, 0 },
3698 { "aand", { Mdq, Gdq }, 0 },
3699 { "aor", { Mdq, Gdq }, 0 },
3700 },
3701
3702 /* PREFIX_0F3A0F */
3703 {
3704 { Bad_Opcode },
3705 { REG_TABLE (REG_0F3A0F_P_1) },
3706 },
3707
3708 /* PREFIX_VEX_0F12 */
3709 {
3710 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0) },
3711 { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3712 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3713 { "%XEvmov%XDdup", { XM, EXymmq }, 0 },
3714 },
3715
3716 /* PREFIX_VEX_0F16 */
3717 {
3718 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0) },
3719 { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3720 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3721 },
3722
3723 /* PREFIX_VEX_0F2A */
3724 {
3725 { Bad_Opcode },
3726 { "%XEvcvtsi2ssY{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3727 { Bad_Opcode },
3728 { "%XEvcvtsi2sdY{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3729 },
3730
3731 /* PREFIX_VEX_0F2C */
3732 {
3733 { Bad_Opcode },
3734 { "%XEvcvttss2si", { Gdq, EXd, EXxEVexS }, 0 },
3735 { Bad_Opcode },
3736 { "%XEvcvttsd2si", { Gdq, EXq, EXxEVexS }, 0 },
3737 },
3738
3739 /* PREFIX_VEX_0F2D */
3740 {
3741 { Bad_Opcode },
3742 { "%XEvcvtss2si", { Gdq, EXd, EXxEVexR }, 0 },
3743 { Bad_Opcode },
3744 { "%XEvcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 },
3745 },
3746
3747 /* PREFIX_VEX_0F41_L_1_W_0 */
3748 {
3749 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
3750 { Bad_Opcode },
3751 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
3752 },
3753
3754 /* PREFIX_VEX_0F41_L_1_W_1 */
3755 {
3756 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
3757 { Bad_Opcode },
3758 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
3759 },
3760
3761 /* PREFIX_VEX_0F42_L_1_W_0 */
3762 {
3763 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
3764 { Bad_Opcode },
3765 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
3766 },
3767
3768 /* PREFIX_VEX_0F42_L_1_W_1 */
3769 {
3770 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
3771 { Bad_Opcode },
3772 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
3773 },
3774
3775 /* PREFIX_VEX_0F44_L_0_W_0 */
3776 {
3777 { "knotw", { MaskG, MaskR }, 0 },
3778 { Bad_Opcode },
3779 { "knotb", { MaskG, MaskR }, 0 },
3780 },
3781
3782 /* PREFIX_VEX_0F44_L_0_W_1 */
3783 {
3784 { "knotq", { MaskG, MaskR }, 0 },
3785 { Bad_Opcode },
3786 { "knotd", { MaskG, MaskR }, 0 },
3787 },
3788
3789 /* PREFIX_VEX_0F45_L_1_W_0 */
3790 {
3791 { "korw", { MaskG, MaskVex, MaskR }, 0 },
3792 { Bad_Opcode },
3793 { "korb", { MaskG, MaskVex, MaskR }, 0 },
3794 },
3795
3796 /* PREFIX_VEX_0F45_L_1_W_1 */
3797 {
3798 { "korq", { MaskG, MaskVex, MaskR }, 0 },
3799 { Bad_Opcode },
3800 { "kord", { MaskG, MaskVex, MaskR }, 0 },
3801 },
3802
3803 /* PREFIX_VEX_0F46_L_1_W_0 */
3804 {
3805 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
3806 { Bad_Opcode },
3807 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
3808 },
3809
3810 /* PREFIX_VEX_0F46_L_1_W_1 */
3811 {
3812 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
3813 { Bad_Opcode },
3814 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
3815 },
3816
3817 /* PREFIX_VEX_0F47_L_1_W_0 */
3818 {
3819 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
3820 { Bad_Opcode },
3821 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
3822 },
3823
3824 /* PREFIX_VEX_0F47_L_1_W_1 */
3825 {
3826 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
3827 { Bad_Opcode },
3828 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
3829 },
3830
3831 /* PREFIX_VEX_0F4A_L_1_W_0 */
3832 {
3833 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
3834 { Bad_Opcode },
3835 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
3836 },
3837
3838 /* PREFIX_VEX_0F4A_L_1_W_1 */
3839 {
3840 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
3841 { Bad_Opcode },
3842 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
3843 },
3844
3845 /* PREFIX_VEX_0F4B_L_1_W_0 */
3846 {
3847 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
3848 { Bad_Opcode },
3849 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
3850 },
3851
3852 /* PREFIX_VEX_0F4B_L_1_W_1 */
3853 {
3854 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
3855 },
3856
3857 /* PREFIX_VEX_0F6F */
3858 {
3859 { Bad_Opcode },
3860 { "vmovdqu", { XM, EXx }, 0 },
3861 { "vmovdqa", { XM, EXx }, 0 },
3862 },
3863
3864 /* PREFIX_VEX_0F70 */
3865 {
3866 { Bad_Opcode },
3867 { "vpshufhw", { XM, EXx, Ib }, 0 },
3868 { "vpshufd", { XM, EXx, Ib }, 0 },
3869 { "vpshuflw", { XM, EXx, Ib }, 0 },
3870 },
3871
3872 /* PREFIX_VEX_0F7E */
3873 {
3874 { Bad_Opcode },
3875 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3876 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3877 },
3878
3879 /* PREFIX_VEX_0F7F */
3880 {
3881 { Bad_Opcode },
3882 { "vmovdqu", { EXxS, XM }, 0 },
3883 { "vmovdqa", { EXxS, XM }, 0 },
3884 },
3885
3886 /* PREFIX_VEX_0F90_L_0_W_0 */
3887 {
3888 { "kmovw", { MaskG, MaskE }, 0 },
3889 { Bad_Opcode },
3890 { "kmovb", { MaskG, MaskBDE }, 0 },
3891 },
3892
3893 /* PREFIX_VEX_0F90_L_0_W_1 */
3894 {
3895 { "kmovq", { MaskG, MaskE }, 0 },
3896 { Bad_Opcode },
3897 { "kmovd", { MaskG, MaskBDE }, 0 },
3898 },
3899
3900 /* PREFIX_VEX_0F91_L_0_W_0 */
3901 {
3902 { "kmovw", { Mw, MaskG }, 0 },
3903 { Bad_Opcode },
3904 { "kmovb", { Mb, MaskG }, 0 },
3905 },
3906
3907 /* PREFIX_VEX_0F91_L_0_W_1 */
3908 {
3909 { "kmovq", { Mq, MaskG }, 0 },
3910 { Bad_Opcode },
3911 { "kmovd", { Md, MaskG }, 0 },
3912 },
3913
3914 /* PREFIX_VEX_0F92_L_0_W_0 */
3915 {
3916 { "kmovw", { MaskG, Rdq }, 0 },
3917 { Bad_Opcode },
3918 { "kmovb", { MaskG, Rdq }, 0 },
3919 { "kmovd", { MaskG, Rdq }, 0 },
3920 },
3921
3922 /* PREFIX_VEX_0F92_L_0_W_1 */
3923 {
3924 { Bad_Opcode },
3925 { Bad_Opcode },
3926 { Bad_Opcode },
3927 { "kmovK", { MaskG, Rdq }, 0 },
3928 },
3929
3930 /* PREFIX_VEX_0F93_L_0_W_0 */
3931 {
3932 { "kmovw", { Gdq, MaskR }, 0 },
3933 { Bad_Opcode },
3934 { "kmovb", { Gdq, MaskR }, 0 },
3935 { "kmovd", { Gdq, MaskR }, 0 },
3936 },
3937
3938 /* PREFIX_VEX_0F93_L_0_W_1 */
3939 {
3940 { Bad_Opcode },
3941 { Bad_Opcode },
3942 { Bad_Opcode },
3943 { "kmovK", { Gdq, MaskR }, 0 },
3944 },
3945
3946 /* PREFIX_VEX_0F98_L_0_W_0 */
3947 {
3948 { "kortestw", { MaskG, MaskR }, 0 },
3949 { Bad_Opcode },
3950 { "kortestb", { MaskG, MaskR }, 0 },
3951 },
3952
3953 /* PREFIX_VEX_0F98_L_0_W_1 */
3954 {
3955 { "kortestq", { MaskG, MaskR }, 0 },
3956 { Bad_Opcode },
3957 { "kortestd", { MaskG, MaskR }, 0 },
3958 },
3959
3960 /* PREFIX_VEX_0F99_L_0_W_0 */
3961 {
3962 { "ktestw", { MaskG, MaskR }, 0 },
3963 { Bad_Opcode },
3964 { "ktestb", { MaskG, MaskR }, 0 },
3965 },
3966
3967 /* PREFIX_VEX_0F99_L_0_W_1 */
3968 {
3969 { "ktestq", { MaskG, MaskR }, 0 },
3970 { Bad_Opcode },
3971 { "ktestd", { MaskG, MaskR }, 0 },
3972 },
3973
3974 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */
3975 {
3976 { "ldtilecfg", { M }, 0 },
3977 { Bad_Opcode },
3978 { "sttilecfg", { M }, 0 },
3979 },
3980
3981 /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1 */
3982 {
3983 { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0) },
3984 { Bad_Opcode },
3985 { Bad_Opcode },
3986 { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) },
3987 },
3988
3989 /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */
3990 {
3991 { Bad_Opcode },
3992 { "tilestored", { MVexSIBMEM, TMM }, 0 },
3993 { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
3994 { "tileloadd", { TMM, MVexSIBMEM }, 0 },
3995 },
3996
3997 /* PREFIX_VEX_0F3850_W_0 */
3998 {
3999 { "vpdpbuud", { XM, Vex, EXx }, 0 },
4000 { "vpdpbsud", { XM, Vex, EXx }, 0 },
4001 { "%XVvpdpbusd", { XM, Vex, EXx }, 0 },
4002 { "vpdpbssd", { XM, Vex, EXx }, 0 },
4003 },
4004
4005 /* PREFIX_VEX_0F3851_W_0 */
4006 {
4007 { "vpdpbuuds", { XM, Vex, EXx }, 0 },
4008 { "vpdpbsuds", { XM, Vex, EXx }, 0 },
4009 { "%XVvpdpbusds", { XM, Vex, EXx }, 0 },
4010 { "vpdpbssds", { XM, Vex, EXx }, 0 },
4011 },
4012 /* PREFIX_VEX_0F385C_X86_64_L_0_W_0 */
4013 {
4014 { Bad_Opcode },
4015 { "tdpbf16ps", { TMM, Rtmm, VexTmm }, 0 },
4016 { Bad_Opcode },
4017 { "tdpfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4018 },
4019
4020 /* PREFIX_VEX_0F385E_X86_64_L_0_W_0 */
4021 {
4022 { "tdpbuud", {TMM, Rtmm, VexTmm }, 0 },
4023 { "tdpbsud", {TMM, Rtmm, VexTmm }, 0 },
4024 { "tdpbusd", {TMM, Rtmm, VexTmm }, 0 },
4025 { "tdpbssd", {TMM, Rtmm, VexTmm }, 0 },
4026 },
4027
4028 /* PREFIX_VEX_0F386C_X86_64_L_0_W_0 */
4029 {
4030 { "tcmmrlfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4031 { Bad_Opcode },
4032 { "tcmmimfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4033 },
4034
4035 /* PREFIX_VEX_0F3872 */
4036 {
4037 { Bad_Opcode },
4038 { VEX_W_TABLE (VEX_W_0F3872_P_1) },
4039 },
4040
4041 /* PREFIX_VEX_0F38B0_W_0 */
4042 {
4043 { "vcvtneoph2ps", { XM, Mx }, 0 },
4044 { "vcvtneebf162ps", { XM, Mx }, 0 },
4045 { "vcvtneeph2ps", { XM, Mx }, 0 },
4046 { "vcvtneobf162ps", { XM, Mx }, 0 },
4047 },
4048
4049 /* PREFIX_VEX_0F38B1_W_0 */
4050 {
4051 { Bad_Opcode },
4052 { "vbcstnebf162ps", { XM, Mw }, 0 },
4053 { "vbcstnesh2ps", { XM, Mw }, 0 },
4054 },
4055
4056 /* PREFIX_VEX_0F38D2_W_0 */
4057 {
4058 { "vpdpwuud", { XM, Vex, EXx }, 0 },
4059 { "vpdpwsud", { XM, Vex, EXx }, 0 },
4060 { "vpdpwusd", { XM, Vex, EXx }, 0 },
4061 },
4062
4063 /* PREFIX_VEX_0F38D3_W_0 */
4064 {
4065 { "vpdpwuuds", { XM, Vex, EXx }, 0 },
4066 { "vpdpwsuds", { XM, Vex, EXx }, 0 },
4067 { "vpdpwusds", { XM, Vex, EXx }, 0 },
4068 },
4069
4070 /* PREFIX_VEX_0F38CB */
4071 {
4072 { Bad_Opcode },
4073 { Bad_Opcode },
4074 { Bad_Opcode },
4075 { VEX_W_TABLE (VEX_W_0F38CB_P_3) },
4076 },
4077
4078 /* PREFIX_VEX_0F38CC */
4079 {
4080 { Bad_Opcode },
4081 { Bad_Opcode },
4082 { Bad_Opcode },
4083 { VEX_W_TABLE (VEX_W_0F38CC_P_3) },
4084 },
4085
4086 /* PREFIX_VEX_0F38CD */
4087 {
4088 { Bad_Opcode },
4089 { Bad_Opcode },
4090 { Bad_Opcode },
4091 { VEX_W_TABLE (VEX_W_0F38CD_P_3) },
4092 },
4093
4094 /* PREFIX_VEX_0F38DA_W_0 */
4095 {
4096 { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0) },
4097 { "vsm4key4", { XM, Vex, EXx }, 0 },
4098 { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2) },
4099 { "vsm4rnds4", { XM, Vex, EXx }, 0 },
4100 },
4101
4102 /* PREFIX_VEX_0F38F2_L_0 */
4103 {
4104 { "andnS", { Gdq, VexGdq, Edq }, 0 },
4105 },
4106
4107 /* PREFIX_VEX_0F38F3_L_0 */
4108 {
4109 { REG_TABLE (REG_VEX_0F38F3_L_0_P_0) },
4110 },
4111
4112 /* PREFIX_VEX_0F38F5_L_0 */
4113 {
4114 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
4115 { "pextS", { Gdq, VexGdq, Edq }, 0 },
4116 { Bad_Opcode },
4117 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
4118 },
4119
4120 /* PREFIX_VEX_0F38F6_L_0 */
4121 {
4122 { Bad_Opcode },
4123 { Bad_Opcode },
4124 { Bad_Opcode },
4125 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
4126 },
4127
4128 /* PREFIX_VEX_0F38F7_L_0 */
4129 {
4130 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
4131 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
4132 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
4133 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
4134 },
4135
4136 /* PREFIX_VEX_0F3AF0_L_0 */
4137 {
4138 { Bad_Opcode },
4139 { Bad_Opcode },
4140 { Bad_Opcode },
4141 { "rorxS", { Gdq, Edq, Ib }, 0 },
4142 },
4143
4144 /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */
4145 {
4146 { Bad_Opcode },
4147 { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 },
4148 { Bad_Opcode },
4149 { "urdmsr", { Rq, Id }, 0 },
4150 },
4151
4152 #include "i386-dis-evex-prefix.h"
4153 };
4154
4155 static const struct dis386 x86_64_table[][2] = {
4156 /* X86_64_06 */
4157 {
4158 { "pushP", { es }, 0 },
4159 },
4160
4161 /* X86_64_07 */
4162 {
4163 { "popP", { es }, 0 },
4164 },
4165
4166 /* X86_64_0E */
4167 {
4168 { "pushP", { cs }, 0 },
4169 },
4170
4171 /* X86_64_16 */
4172 {
4173 { "pushP", { ss }, 0 },
4174 },
4175
4176 /* X86_64_17 */
4177 {
4178 { "popP", { ss }, 0 },
4179 },
4180
4181 /* X86_64_1E */
4182 {
4183 { "pushP", { ds }, 0 },
4184 },
4185
4186 /* X86_64_1F */
4187 {
4188 { "popP", { ds }, 0 },
4189 },
4190
4191 /* X86_64_27 */
4192 {
4193 { "daa", { XX }, 0 },
4194 },
4195
4196 /* X86_64_2F */
4197 {
4198 { "das", { XX }, 0 },
4199 },
4200
4201 /* X86_64_37 */
4202 {
4203 { "aaa", { XX }, 0 },
4204 },
4205
4206 /* X86_64_3F */
4207 {
4208 { "aas", { XX }, 0 },
4209 },
4210
4211 /* X86_64_60 */
4212 {
4213 { "pushaP", { XX }, 0 },
4214 },
4215
4216 /* X86_64_61 */
4217 {
4218 { "popaP", { XX }, 0 },
4219 },
4220
4221 /* X86_64_62 */
4222 {
4223 { MOD_TABLE (MOD_62_32BIT) },
4224 { EVEX_TABLE () },
4225 },
4226
4227 /* X86_64_63 */
4228 {
4229 { "arplS", { Sv, Gv }, 0 },
4230 { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4231 },
4232
4233 /* X86_64_6D */
4234 {
4235 { "ins{R|}", { Yzr, indirDX }, 0 },
4236 { "ins{G|}", { Yzr, indirDX }, 0 },
4237 },
4238
4239 /* X86_64_6F */
4240 {
4241 { "outs{R|}", { indirDXr, Xz }, 0 },
4242 { "outs{G|}", { indirDXr, Xz }, 0 },
4243 },
4244
4245 /* X86_64_82 */
4246 {
4247 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
4248 { REG_TABLE (REG_80) },
4249 },
4250
4251 /* X86_64_9A */
4252 {
4253 { "{l|}call{P|}", { Ap }, 0 },
4254 },
4255
4256 /* X86_64_C2 */
4257 {
4258 { "retP", { Iw, BND }, 0 },
4259 { "ret@", { Iw, BND }, 0 },
4260 },
4261
4262 /* X86_64_C3 */
4263 {
4264 { "retP", { BND }, 0 },
4265 { "ret@", { BND }, 0 },
4266 },
4267
4268 /* X86_64_C4 */
4269 {
4270 { MOD_TABLE (MOD_C4_32BIT) },
4271 { VEX_C4_TABLE () },
4272 },
4273
4274 /* X86_64_C5 */
4275 {
4276 { MOD_TABLE (MOD_C5_32BIT) },
4277 { VEX_C5_TABLE () },
4278 },
4279
4280 /* X86_64_CE */
4281 {
4282 { "into", { XX }, 0 },
4283 },
4284
4285 /* X86_64_D4 */
4286 {
4287 { "aam", { Ib }, 0 },
4288 },
4289
4290 /* X86_64_D5 */
4291 {
4292 { "aad", { Ib }, 0 },
4293 },
4294
4295 /* X86_64_E8 */
4296 {
4297 { "callP", { Jv, BND }, 0 },
4298 { "call@", { Jv, BND }, PREFIX_REX2_ILLEGAL }
4299 },
4300
4301 /* X86_64_E9 */
4302 {
4303 { "jmpP", { Jv, BND }, 0 },
4304 { "jmp@", { Jv, BND }, PREFIX_REX2_ILLEGAL }
4305 },
4306
4307 /* X86_64_EA */
4308 {
4309 { "{l|}jmp{P|}", { Ap }, 0 },
4310 },
4311
4312 /* X86_64_0F00_REG_6 */
4313 {
4314 { Bad_Opcode },
4315 { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) },
4316 },
4317
4318 /* X86_64_0F01_REG_0 */
4319 {
4320 { "sgdt{Q|Q}", { M }, 0 },
4321 { "sgdt", { M }, 0 },
4322 },
4323
4324 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4325 {
4326 { Bad_Opcode },
4327 { "wrmsrlist", { Skip_MODRM }, 0 },
4328 },
4329
4330 /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4331 {
4332 { Bad_Opcode },
4333 { "rdmsrlist", { Skip_MODRM }, 0 },
4334 },
4335
4336 /* X86_64_0F01_REG_0_MOD_3_RM_7_P_0 */
4337 {
4338 { Bad_Opcode },
4339 { "pbndkb", { Skip_MODRM }, 0 },
4340 },
4341
4342 /* X86_64_0F01_REG_1 */
4343 {
4344 { "sidt{Q|Q}", { M }, 0 },
4345 { "sidt", { M }, 0 },
4346 },
4347
4348 /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */
4349 {
4350 { Bad_Opcode },
4351 { "eretu", { Skip_MODRM }, 0 },
4352 },
4353
4354 /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */
4355 {
4356 { Bad_Opcode },
4357 { "erets", { Skip_MODRM }, 0 },
4358 },
4359
4360 /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4361 {
4362 { Bad_Opcode },
4363 { "seamret", { Skip_MODRM }, 0 },
4364 },
4365
4366 /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4367 {
4368 { Bad_Opcode },
4369 { "seamops", { Skip_MODRM }, 0 },
4370 },
4371
4372 /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4373 {
4374 { Bad_Opcode },
4375 { "seamcall", { Skip_MODRM }, 0 },
4376 },
4377
4378 /* X86_64_0F01_REG_2 */
4379 {
4380 { "lgdt{Q|Q}", { M }, 0 },
4381 { "lgdt", { M }, 0 },
4382 },
4383
4384 /* X86_64_0F01_REG_3 */
4385 {
4386 { "lidt{Q|Q}", { M }, 0 },
4387 { "lidt", { M }, 0 },
4388 },
4389
4390 /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4391 {
4392 { Bad_Opcode },
4393 { "uiret", { Skip_MODRM }, 0 },
4394 },
4395
4396 /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4397 {
4398 { Bad_Opcode },
4399 { "testui", { Skip_MODRM }, 0 },
4400 },
4401
4402 /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4403 {
4404 { Bad_Opcode },
4405 { "clui", { Skip_MODRM }, 0 },
4406 },
4407
4408 /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4409 {
4410 { Bad_Opcode },
4411 { "stui", { Skip_MODRM }, 0 },
4412 },
4413
4414 /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
4415 {
4416 { Bad_Opcode },
4417 { "rmpquery", { Skip_MODRM }, 0 },
4418 },
4419
4420 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4421 {
4422 { Bad_Opcode },
4423 { "rmpadjust", { Skip_MODRM }, 0 },
4424 },
4425
4426 /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4427 {
4428 { Bad_Opcode },
4429 { "rmpupdate", { Skip_MODRM }, 0 },
4430 },
4431
4432 /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4433 {
4434 { Bad_Opcode },
4435 { "psmash", { Skip_MODRM }, 0 },
4436 },
4437
4438 /* X86_64_0F18_REG_6_MOD_0 */
4439 {
4440 { "nopQ", { Ev }, 0 },
4441 { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
4442 },
4443
4444 /* X86_64_0F18_REG_7_MOD_0 */
4445 {
4446 { "nopQ", { Ev }, 0 },
4447 { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
4448 },
4449
4450 {
4451 /* X86_64_0F24 */
4452 { "movZ", { Em, Td }, 0 },
4453 },
4454
4455 {
4456 /* X86_64_0F26 */
4457 { "movZ", { Td, Em }, 0 },
4458 },
4459
4460 {
4461 /* X86_64_0F38F8_M_1 */
4462 { Bad_Opcode },
4463 { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) },
4464 },
4465
4466 /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4467 {
4468 { Bad_Opcode },
4469 { "senduipi", { Eq }, 0 },
4470 },
4471
4472 /* X86_64_VEX_0F3849 */
4473 {
4474 { Bad_Opcode },
4475 { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) },
4476 },
4477
4478 /* X86_64_VEX_0F384B */
4479 {
4480 { Bad_Opcode },
4481 { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) },
4482 },
4483
4484 /* X86_64_VEX_0F385C */
4485 {
4486 { Bad_Opcode },
4487 { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64) },
4488 },
4489
4490 /* X86_64_VEX_0F385E */
4491 {
4492 { Bad_Opcode },
4493 { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64) },
4494 },
4495
4496 /* X86_64_VEX_0F386C */
4497 {
4498 { Bad_Opcode },
4499 { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64) },
4500 },
4501
4502 /* X86_64_VEX_0F38E0 */
4503 {
4504 { Bad_Opcode },
4505 { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4506 },
4507
4508 /* X86_64_VEX_0F38E1 */
4509 {
4510 { Bad_Opcode },
4511 { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4512 },
4513
4514 /* X86_64_VEX_0F38E2 */
4515 {
4516 { Bad_Opcode },
4517 { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4518 },
4519
4520 /* X86_64_VEX_0F38E3 */
4521 {
4522 { Bad_Opcode },
4523 { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4524 },
4525
4526 /* X86_64_VEX_0F38E4 */
4527 {
4528 { Bad_Opcode },
4529 { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4530 },
4531
4532 /* X86_64_VEX_0F38E5 */
4533 {
4534 { Bad_Opcode },
4535 { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4536 },
4537
4538 /* X86_64_VEX_0F38E6 */
4539 {
4540 { Bad_Opcode },
4541 { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4542 },
4543
4544 /* X86_64_VEX_0F38E7 */
4545 {
4546 { Bad_Opcode },
4547 { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4548 },
4549
4550 /* X86_64_VEX_0F38E8 */
4551 {
4552 { Bad_Opcode },
4553 { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4554 },
4555
4556 /* X86_64_VEX_0F38E9 */
4557 {
4558 { Bad_Opcode },
4559 { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4560 },
4561
4562 /* X86_64_VEX_0F38EA */
4563 {
4564 { Bad_Opcode },
4565 { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4566 },
4567
4568 /* X86_64_VEX_0F38EB */
4569 {
4570 { Bad_Opcode },
4571 { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4572 },
4573
4574 /* X86_64_VEX_0F38EC */
4575 {
4576 { Bad_Opcode },
4577 { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4578 },
4579
4580 /* X86_64_VEX_0F38ED */
4581 {
4582 { Bad_Opcode },
4583 { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4584 },
4585
4586 /* X86_64_VEX_0F38EE */
4587 {
4588 { Bad_Opcode },
4589 { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4590 },
4591
4592 /* X86_64_VEX_0F38EF */
4593 {
4594 { Bad_Opcode },
4595 { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4596 },
4597
4598 /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */
4599 {
4600 { Bad_Opcode },
4601 { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) },
4602 },
4603
4604 #include "i386-dis-evex-x86-64.h"
4605 };
4606
4607 static const struct dis386 three_byte_table[][256] = {
4608
4609 /* THREE_BYTE_0F38 */
4610 {
4611 /* 00 */
4612 { "pshufb", { MX, EM }, PREFIX_OPCODE },
4613 { "phaddw", { MX, EM }, PREFIX_OPCODE },
4614 { "phaddd", { MX, EM }, PREFIX_OPCODE },
4615 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
4616 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
4617 { "phsubw", { MX, EM }, PREFIX_OPCODE },
4618 { "phsubd", { MX, EM }, PREFIX_OPCODE },
4619 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
4620 /* 08 */
4621 { "psignb", { MX, EM }, PREFIX_OPCODE },
4622 { "psignw", { MX, EM }, PREFIX_OPCODE },
4623 { "psignd", { MX, EM }, PREFIX_OPCODE },
4624 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
4625 { Bad_Opcode },
4626 { Bad_Opcode },
4627 { Bad_Opcode },
4628 { Bad_Opcode },
4629 /* 10 */
4630 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4631 { Bad_Opcode },
4632 { Bad_Opcode },
4633 { Bad_Opcode },
4634 { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4635 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4636 { Bad_Opcode },
4637 { "ptest", { XM, EXx }, PREFIX_DATA },
4638 /* 18 */
4639 { Bad_Opcode },
4640 { Bad_Opcode },
4641 { Bad_Opcode },
4642 { Bad_Opcode },
4643 { "pabsb", { MX, EM }, PREFIX_OPCODE },
4644 { "pabsw", { MX, EM }, PREFIX_OPCODE },
4645 { "pabsd", { MX, EM }, PREFIX_OPCODE },
4646 { Bad_Opcode },
4647 /* 20 */
4648 { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4649 { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4650 { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4651 { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4652 { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4653 { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4654 { Bad_Opcode },
4655 { Bad_Opcode },
4656 /* 28 */
4657 { "pmuldq", { XM, EXx }, PREFIX_DATA },
4658 { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4659 { "movntdqa", { XM, Mx }, PREFIX_DATA },
4660 { "packusdw", { XM, EXx }, PREFIX_DATA },
4661 { Bad_Opcode },
4662 { Bad_Opcode },
4663 { Bad_Opcode },
4664 { Bad_Opcode },
4665 /* 30 */
4666 { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4667 { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4668 { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4669 { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4670 { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4671 { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4672 { Bad_Opcode },
4673 { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4674 /* 38 */
4675 { "pminsb", { XM, EXx }, PREFIX_DATA },
4676 { "pminsd", { XM, EXx }, PREFIX_DATA },
4677 { "pminuw", { XM, EXx }, PREFIX_DATA },
4678 { "pminud", { XM, EXx }, PREFIX_DATA },
4679 { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4680 { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4681 { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4682 { "pmaxud", { XM, EXx }, PREFIX_DATA },
4683 /* 40 */
4684 { "pmulld", { XM, EXx }, PREFIX_DATA },
4685 { "phminposuw", { XM, EXx }, PREFIX_DATA },
4686 { Bad_Opcode },
4687 { Bad_Opcode },
4688 { Bad_Opcode },
4689 { Bad_Opcode },
4690 { Bad_Opcode },
4691 { Bad_Opcode },
4692 /* 48 */
4693 { Bad_Opcode },
4694 { Bad_Opcode },
4695 { Bad_Opcode },
4696 { Bad_Opcode },
4697 { Bad_Opcode },
4698 { Bad_Opcode },
4699 { Bad_Opcode },
4700 { Bad_Opcode },
4701 /* 50 */
4702 { Bad_Opcode },
4703 { Bad_Opcode },
4704 { Bad_Opcode },
4705 { Bad_Opcode },
4706 { Bad_Opcode },
4707 { Bad_Opcode },
4708 { Bad_Opcode },
4709 { Bad_Opcode },
4710 /* 58 */
4711 { Bad_Opcode },
4712 { Bad_Opcode },
4713 { Bad_Opcode },
4714 { Bad_Opcode },
4715 { Bad_Opcode },
4716 { Bad_Opcode },
4717 { Bad_Opcode },
4718 { Bad_Opcode },
4719 /* 60 */
4720 { Bad_Opcode },
4721 { Bad_Opcode },
4722 { Bad_Opcode },
4723 { Bad_Opcode },
4724 { Bad_Opcode },
4725 { Bad_Opcode },
4726 { Bad_Opcode },
4727 { Bad_Opcode },
4728 /* 68 */
4729 { Bad_Opcode },
4730 { Bad_Opcode },
4731 { Bad_Opcode },
4732 { Bad_Opcode },
4733 { Bad_Opcode },
4734 { Bad_Opcode },
4735 { Bad_Opcode },
4736 { Bad_Opcode },
4737 /* 70 */
4738 { Bad_Opcode },
4739 { Bad_Opcode },
4740 { Bad_Opcode },
4741 { Bad_Opcode },
4742 { Bad_Opcode },
4743 { Bad_Opcode },
4744 { Bad_Opcode },
4745 { Bad_Opcode },
4746 /* 78 */
4747 { Bad_Opcode },
4748 { Bad_Opcode },
4749 { Bad_Opcode },
4750 { Bad_Opcode },
4751 { Bad_Opcode },
4752 { Bad_Opcode },
4753 { Bad_Opcode },
4754 { Bad_Opcode },
4755 /* 80 */
4756 { "invept", { Gm, Mo }, PREFIX_DATA },
4757 { "invvpid", { Gm, Mo }, PREFIX_DATA },
4758 { "invpcid", { Gm, M }, PREFIX_DATA },
4759 { Bad_Opcode },
4760 { Bad_Opcode },
4761 { Bad_Opcode },
4762 { Bad_Opcode },
4763 { Bad_Opcode },
4764 /* 88 */
4765 { Bad_Opcode },
4766 { Bad_Opcode },
4767 { Bad_Opcode },
4768 { Bad_Opcode },
4769 { Bad_Opcode },
4770 { Bad_Opcode },
4771 { Bad_Opcode },
4772 { Bad_Opcode },
4773 /* 90 */
4774 { Bad_Opcode },
4775 { Bad_Opcode },
4776 { Bad_Opcode },
4777 { Bad_Opcode },
4778 { Bad_Opcode },
4779 { Bad_Opcode },
4780 { Bad_Opcode },
4781 { Bad_Opcode },
4782 /* 98 */
4783 { Bad_Opcode },
4784 { Bad_Opcode },
4785 { Bad_Opcode },
4786 { Bad_Opcode },
4787 { Bad_Opcode },
4788 { Bad_Opcode },
4789 { Bad_Opcode },
4790 { Bad_Opcode },
4791 /* a0 */
4792 { Bad_Opcode },
4793 { Bad_Opcode },
4794 { Bad_Opcode },
4795 { Bad_Opcode },
4796 { Bad_Opcode },
4797 { Bad_Opcode },
4798 { Bad_Opcode },
4799 { Bad_Opcode },
4800 /* a8 */
4801 { Bad_Opcode },
4802 { Bad_Opcode },
4803 { Bad_Opcode },
4804 { Bad_Opcode },
4805 { Bad_Opcode },
4806 { Bad_Opcode },
4807 { Bad_Opcode },
4808 { Bad_Opcode },
4809 /* b0 */
4810 { Bad_Opcode },
4811 { Bad_Opcode },
4812 { Bad_Opcode },
4813 { Bad_Opcode },
4814 { Bad_Opcode },
4815 { Bad_Opcode },
4816 { Bad_Opcode },
4817 { Bad_Opcode },
4818 /* b8 */
4819 { Bad_Opcode },
4820 { Bad_Opcode },
4821 { Bad_Opcode },
4822 { Bad_Opcode },
4823 { Bad_Opcode },
4824 { Bad_Opcode },
4825 { Bad_Opcode },
4826 { Bad_Opcode },
4827 /* c0 */
4828 { Bad_Opcode },
4829 { Bad_Opcode },
4830 { Bad_Opcode },
4831 { Bad_Opcode },
4832 { Bad_Opcode },
4833 { Bad_Opcode },
4834 { Bad_Opcode },
4835 { Bad_Opcode },
4836 /* c8 */
4837 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4838 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4839 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4840 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4841 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4842 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4843 { Bad_Opcode },
4844 { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4845 /* d0 */
4846 { Bad_Opcode },
4847 { Bad_Opcode },
4848 { Bad_Opcode },
4849 { Bad_Opcode },
4850 { Bad_Opcode },
4851 { Bad_Opcode },
4852 { Bad_Opcode },
4853 { Bad_Opcode },
4854 /* d8 */
4855 { PREFIX_TABLE (PREFIX_0F38D8) },
4856 { Bad_Opcode },
4857 { Bad_Opcode },
4858 { "aesimc", { XM, EXx }, PREFIX_DATA },
4859 { PREFIX_TABLE (PREFIX_0F38DC) },
4860 { PREFIX_TABLE (PREFIX_0F38DD) },
4861 { PREFIX_TABLE (PREFIX_0F38DE) },
4862 { PREFIX_TABLE (PREFIX_0F38DF) },
4863 /* e0 */
4864 { Bad_Opcode },
4865 { Bad_Opcode },
4866 { Bad_Opcode },
4867 { Bad_Opcode },
4868 { Bad_Opcode },
4869 { Bad_Opcode },
4870 { Bad_Opcode },
4871 { Bad_Opcode },
4872 /* e8 */
4873 { Bad_Opcode },
4874 { Bad_Opcode },
4875 { Bad_Opcode },
4876 { Bad_Opcode },
4877 { Bad_Opcode },
4878 { Bad_Opcode },
4879 { Bad_Opcode },
4880 { Bad_Opcode },
4881 /* f0 */
4882 { PREFIX_TABLE (PREFIX_0F38F0) },
4883 { PREFIX_TABLE (PREFIX_0F38F1) },
4884 { Bad_Opcode },
4885 { Bad_Opcode },
4886 { Bad_Opcode },
4887 { "wrussK", { M, Gdq }, PREFIX_DATA },
4888 { PREFIX_TABLE (PREFIX_0F38F6) },
4889 { Bad_Opcode },
4890 /* f8 */
4891 { MOD_TABLE (MOD_0F38F8) },
4892 { "movdiri", { Mdq, Gdq }, PREFIX_OPCODE },
4893 { PREFIX_TABLE (PREFIX_0F38FA) },
4894 { PREFIX_TABLE (PREFIX_0F38FB) },
4895 { PREFIX_TABLE (PREFIX_0F38FC) },
4896 { Bad_Opcode },
4897 { Bad_Opcode },
4898 { Bad_Opcode },
4899 },
4900 /* THREE_BYTE_0F3A */
4901 {
4902 /* 00 */
4903 { Bad_Opcode },
4904 { Bad_Opcode },
4905 { Bad_Opcode },
4906 { Bad_Opcode },
4907 { Bad_Opcode },
4908 { Bad_Opcode },
4909 { Bad_Opcode },
4910 { Bad_Opcode },
4911 /* 08 */
4912 { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4913 { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4914 { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4915 { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4916 { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4917 { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4918 { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4919 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
4920 /* 10 */
4921 { Bad_Opcode },
4922 { Bad_Opcode },
4923 { Bad_Opcode },
4924 { Bad_Opcode },
4925 { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4926 { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4927 { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4928 { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4929 /* 18 */
4930 { Bad_Opcode },
4931 { Bad_Opcode },
4932 { Bad_Opcode },
4933 { Bad_Opcode },
4934 { Bad_Opcode },
4935 { Bad_Opcode },
4936 { Bad_Opcode },
4937 { Bad_Opcode },
4938 /* 20 */
4939 { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4940 { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4941 { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4942 { Bad_Opcode },
4943 { Bad_Opcode },
4944 { Bad_Opcode },
4945 { Bad_Opcode },
4946 { Bad_Opcode },
4947 /* 28 */
4948 { Bad_Opcode },
4949 { Bad_Opcode },
4950 { Bad_Opcode },
4951 { Bad_Opcode },
4952 { Bad_Opcode },
4953 { Bad_Opcode },
4954 { Bad_Opcode },
4955 { Bad_Opcode },
4956 /* 30 */
4957 { Bad_Opcode },
4958 { Bad_Opcode },
4959 { Bad_Opcode },
4960 { Bad_Opcode },
4961 { Bad_Opcode },
4962 { Bad_Opcode },
4963 { Bad_Opcode },
4964 { Bad_Opcode },
4965 /* 38 */
4966 { Bad_Opcode },
4967 { Bad_Opcode },
4968 { Bad_Opcode },
4969 { Bad_Opcode },
4970 { Bad_Opcode },
4971 { Bad_Opcode },
4972 { Bad_Opcode },
4973 { Bad_Opcode },
4974 /* 40 */
4975 { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
4976 { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
4977 { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4978 { Bad_Opcode },
4979 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4980 { Bad_Opcode },
4981 { Bad_Opcode },
4982 { Bad_Opcode },
4983 /* 48 */
4984 { Bad_Opcode },
4985 { Bad_Opcode },
4986 { Bad_Opcode },
4987 { Bad_Opcode },
4988 { Bad_Opcode },
4989 { Bad_Opcode },
4990 { Bad_Opcode },
4991 { Bad_Opcode },
4992 /* 50 */
4993 { Bad_Opcode },
4994 { Bad_Opcode },
4995 { Bad_Opcode },
4996 { Bad_Opcode },
4997 { Bad_Opcode },
4998 { Bad_Opcode },
4999 { Bad_Opcode },
5000 { Bad_Opcode },
5001 /* 58 */
5002 { Bad_Opcode },
5003 { Bad_Opcode },
5004 { Bad_Opcode },
5005 { Bad_Opcode },
5006 { Bad_Opcode },
5007 { Bad_Opcode },
5008 { Bad_Opcode },
5009 { Bad_Opcode },
5010 /* 60 */
5011 { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5012 { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5013 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
5014 { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
5015 { Bad_Opcode },
5016 { Bad_Opcode },
5017 { Bad_Opcode },
5018 { Bad_Opcode },
5019 /* 68 */
5020 { Bad_Opcode },
5021 { Bad_Opcode },
5022 { Bad_Opcode },
5023 { Bad_Opcode },
5024 { Bad_Opcode },
5025 { Bad_Opcode },
5026 { Bad_Opcode },
5027 { Bad_Opcode },
5028 /* 70 */
5029 { Bad_Opcode },
5030 { Bad_Opcode },
5031 { Bad_Opcode },
5032 { Bad_Opcode },
5033 { Bad_Opcode },
5034 { Bad_Opcode },
5035 { Bad_Opcode },
5036 { Bad_Opcode },
5037 /* 78 */
5038 { Bad_Opcode },
5039 { Bad_Opcode },
5040 { Bad_Opcode },
5041 { Bad_Opcode },
5042 { Bad_Opcode },
5043 { Bad_Opcode },
5044 { Bad_Opcode },
5045 { Bad_Opcode },
5046 /* 80 */
5047 { Bad_Opcode },
5048 { Bad_Opcode },
5049 { Bad_Opcode },
5050 { Bad_Opcode },
5051 { Bad_Opcode },
5052 { Bad_Opcode },
5053 { Bad_Opcode },
5054 { Bad_Opcode },
5055 /* 88 */
5056 { Bad_Opcode },
5057 { Bad_Opcode },
5058 { Bad_Opcode },
5059 { Bad_Opcode },
5060 { Bad_Opcode },
5061 { Bad_Opcode },
5062 { Bad_Opcode },
5063 { Bad_Opcode },
5064 /* 90 */
5065 { Bad_Opcode },
5066 { Bad_Opcode },
5067 { Bad_Opcode },
5068 { Bad_Opcode },
5069 { Bad_Opcode },
5070 { Bad_Opcode },
5071 { Bad_Opcode },
5072 { Bad_Opcode },
5073 /* 98 */
5074 { Bad_Opcode },
5075 { Bad_Opcode },
5076 { Bad_Opcode },
5077 { Bad_Opcode },
5078 { Bad_Opcode },
5079 { Bad_Opcode },
5080 { Bad_Opcode },
5081 { Bad_Opcode },
5082 /* a0 */
5083 { Bad_Opcode },
5084 { Bad_Opcode },
5085 { Bad_Opcode },
5086 { Bad_Opcode },
5087 { Bad_Opcode },
5088 { Bad_Opcode },
5089 { Bad_Opcode },
5090 { Bad_Opcode },
5091 /* a8 */
5092 { Bad_Opcode },
5093 { Bad_Opcode },
5094 { Bad_Opcode },
5095 { Bad_Opcode },
5096 { Bad_Opcode },
5097 { Bad_Opcode },
5098 { Bad_Opcode },
5099 { Bad_Opcode },
5100 /* b0 */
5101 { Bad_Opcode },
5102 { Bad_Opcode },
5103 { Bad_Opcode },
5104 { Bad_Opcode },
5105 { Bad_Opcode },
5106 { Bad_Opcode },
5107 { Bad_Opcode },
5108 { Bad_Opcode },
5109 /* b8 */
5110 { Bad_Opcode },
5111 { Bad_Opcode },
5112 { Bad_Opcode },
5113 { Bad_Opcode },
5114 { Bad_Opcode },
5115 { Bad_Opcode },
5116 { Bad_Opcode },
5117 { Bad_Opcode },
5118 /* c0 */
5119 { Bad_Opcode },
5120 { Bad_Opcode },
5121 { Bad_Opcode },
5122 { Bad_Opcode },
5123 { Bad_Opcode },
5124 { Bad_Opcode },
5125 { Bad_Opcode },
5126 { Bad_Opcode },
5127 /* c8 */
5128 { Bad_Opcode },
5129 { Bad_Opcode },
5130 { Bad_Opcode },
5131 { Bad_Opcode },
5132 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
5133 { Bad_Opcode },
5134 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5135 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5136 /* d0 */
5137 { Bad_Opcode },
5138 { Bad_Opcode },
5139 { Bad_Opcode },
5140 { Bad_Opcode },
5141 { Bad_Opcode },
5142 { Bad_Opcode },
5143 { Bad_Opcode },
5144 { Bad_Opcode },
5145 /* d8 */
5146 { Bad_Opcode },
5147 { Bad_Opcode },
5148 { Bad_Opcode },
5149 { Bad_Opcode },
5150 { Bad_Opcode },
5151 { Bad_Opcode },
5152 { Bad_Opcode },
5153 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5154 /* e0 */
5155 { Bad_Opcode },
5156 { Bad_Opcode },
5157 { Bad_Opcode },
5158 { Bad_Opcode },
5159 { Bad_Opcode },
5160 { Bad_Opcode },
5161 { Bad_Opcode },
5162 { Bad_Opcode },
5163 /* e8 */
5164 { Bad_Opcode },
5165 { Bad_Opcode },
5166 { Bad_Opcode },
5167 { Bad_Opcode },
5168 { Bad_Opcode },
5169 { Bad_Opcode },
5170 { Bad_Opcode },
5171 { Bad_Opcode },
5172 /* f0 */
5173 { PREFIX_TABLE (PREFIX_0F3A0F) },
5174 { Bad_Opcode },
5175 { Bad_Opcode },
5176 { Bad_Opcode },
5177 { Bad_Opcode },
5178 { Bad_Opcode },
5179 { Bad_Opcode },
5180 { Bad_Opcode },
5181 /* f8 */
5182 { Bad_Opcode },
5183 { Bad_Opcode },
5184 { Bad_Opcode },
5185 { Bad_Opcode },
5186 { Bad_Opcode },
5187 { Bad_Opcode },
5188 { Bad_Opcode },
5189 { Bad_Opcode },
5190 },
5191 };
5192
5193 static const struct dis386 xop_table[][256] = {
5194 /* XOP_08 */
5195 {
5196 /* 00 */
5197 { Bad_Opcode },
5198 { Bad_Opcode },
5199 { Bad_Opcode },
5200 { Bad_Opcode },
5201 { Bad_Opcode },
5202 { Bad_Opcode },
5203 { Bad_Opcode },
5204 { Bad_Opcode },
5205 /* 08 */
5206 { Bad_Opcode },
5207 { Bad_Opcode },
5208 { Bad_Opcode },
5209 { Bad_Opcode },
5210 { Bad_Opcode },
5211 { Bad_Opcode },
5212 { Bad_Opcode },
5213 { Bad_Opcode },
5214 /* 10 */
5215 { Bad_Opcode },
5216 { Bad_Opcode },
5217 { Bad_Opcode },
5218 { Bad_Opcode },
5219 { Bad_Opcode },
5220 { Bad_Opcode },
5221 { Bad_Opcode },
5222 { Bad_Opcode },
5223 /* 18 */
5224 { Bad_Opcode },
5225 { Bad_Opcode },
5226 { Bad_Opcode },
5227 { Bad_Opcode },
5228 { Bad_Opcode },
5229 { Bad_Opcode },
5230 { Bad_Opcode },
5231 { Bad_Opcode },
5232 /* 20 */
5233 { Bad_Opcode },
5234 { Bad_Opcode },
5235 { Bad_Opcode },
5236 { Bad_Opcode },
5237 { Bad_Opcode },
5238 { Bad_Opcode },
5239 { Bad_Opcode },
5240 { Bad_Opcode },
5241 /* 28 */
5242 { Bad_Opcode },
5243 { Bad_Opcode },
5244 { Bad_Opcode },
5245 { Bad_Opcode },
5246 { Bad_Opcode },
5247 { Bad_Opcode },
5248 { Bad_Opcode },
5249 { Bad_Opcode },
5250 /* 30 */
5251 { Bad_Opcode },
5252 { Bad_Opcode },
5253 { Bad_Opcode },
5254 { Bad_Opcode },
5255 { Bad_Opcode },
5256 { Bad_Opcode },
5257 { Bad_Opcode },
5258 { Bad_Opcode },
5259 /* 38 */
5260 { Bad_Opcode },
5261 { Bad_Opcode },
5262 { Bad_Opcode },
5263 { Bad_Opcode },
5264 { Bad_Opcode },
5265 { Bad_Opcode },
5266 { Bad_Opcode },
5267 { Bad_Opcode },
5268 /* 40 */
5269 { Bad_Opcode },
5270 { Bad_Opcode },
5271 { Bad_Opcode },
5272 { Bad_Opcode },
5273 { Bad_Opcode },
5274 { Bad_Opcode },
5275 { Bad_Opcode },
5276 { Bad_Opcode },
5277 /* 48 */
5278 { Bad_Opcode },
5279 { Bad_Opcode },
5280 { Bad_Opcode },
5281 { Bad_Opcode },
5282 { Bad_Opcode },
5283 { Bad_Opcode },
5284 { Bad_Opcode },
5285 { Bad_Opcode },
5286 /* 50 */
5287 { Bad_Opcode },
5288 { Bad_Opcode },
5289 { Bad_Opcode },
5290 { Bad_Opcode },
5291 { Bad_Opcode },
5292 { Bad_Opcode },
5293 { Bad_Opcode },
5294 { Bad_Opcode },
5295 /* 58 */
5296 { Bad_Opcode },
5297 { Bad_Opcode },
5298 { Bad_Opcode },
5299 { Bad_Opcode },
5300 { Bad_Opcode },
5301 { Bad_Opcode },
5302 { Bad_Opcode },
5303 { Bad_Opcode },
5304 /* 60 */
5305 { Bad_Opcode },
5306 { Bad_Opcode },
5307 { Bad_Opcode },
5308 { Bad_Opcode },
5309 { Bad_Opcode },
5310 { Bad_Opcode },
5311 { Bad_Opcode },
5312 { Bad_Opcode },
5313 /* 68 */
5314 { Bad_Opcode },
5315 { Bad_Opcode },
5316 { Bad_Opcode },
5317 { Bad_Opcode },
5318 { Bad_Opcode },
5319 { Bad_Opcode },
5320 { Bad_Opcode },
5321 { Bad_Opcode },
5322 /* 70 */
5323 { Bad_Opcode },
5324 { Bad_Opcode },
5325 { Bad_Opcode },
5326 { Bad_Opcode },
5327 { Bad_Opcode },
5328 { Bad_Opcode },
5329 { Bad_Opcode },
5330 { Bad_Opcode },
5331 /* 78 */
5332 { Bad_Opcode },
5333 { Bad_Opcode },
5334 { Bad_Opcode },
5335 { Bad_Opcode },
5336 { Bad_Opcode },
5337 { Bad_Opcode },
5338 { Bad_Opcode },
5339 { Bad_Opcode },
5340 /* 80 */
5341 { Bad_Opcode },
5342 { Bad_Opcode },
5343 { Bad_Opcode },
5344 { Bad_Opcode },
5345 { Bad_Opcode },
5346 { VEX_LEN_TABLE (VEX_LEN_XOP_08_85) },
5347 { VEX_LEN_TABLE (VEX_LEN_XOP_08_86) },
5348 { VEX_LEN_TABLE (VEX_LEN_XOP_08_87) },
5349 /* 88 */
5350 { Bad_Opcode },
5351 { Bad_Opcode },
5352 { Bad_Opcode },
5353 { Bad_Opcode },
5354 { Bad_Opcode },
5355 { Bad_Opcode },
5356 { VEX_LEN_TABLE (VEX_LEN_XOP_08_8E) },
5357 { VEX_LEN_TABLE (VEX_LEN_XOP_08_8F) },
5358 /* 90 */
5359 { Bad_Opcode },
5360 { Bad_Opcode },
5361 { Bad_Opcode },
5362 { Bad_Opcode },
5363 { Bad_Opcode },
5364 { VEX_LEN_TABLE (VEX_LEN_XOP_08_95) },
5365 { VEX_LEN_TABLE (VEX_LEN_XOP_08_96) },
5366 { VEX_LEN_TABLE (VEX_LEN_XOP_08_97) },
5367 /* 98 */
5368 { Bad_Opcode },
5369 { Bad_Opcode },
5370 { Bad_Opcode },
5371 { Bad_Opcode },
5372 { Bad_Opcode },
5373 { Bad_Opcode },
5374 { VEX_LEN_TABLE (VEX_LEN_XOP_08_9E) },
5375 { VEX_LEN_TABLE (VEX_LEN_XOP_08_9F) },
5376 /* a0 */
5377 { Bad_Opcode },
5378 { Bad_Opcode },
5379 { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
5380 { VEX_LEN_TABLE (VEX_LEN_XOP_08_A3) },
5381 { Bad_Opcode },
5382 { Bad_Opcode },
5383 { VEX_LEN_TABLE (VEX_LEN_XOP_08_A6) },
5384 { Bad_Opcode },
5385 /* a8 */
5386 { Bad_Opcode },
5387 { Bad_Opcode },
5388 { Bad_Opcode },
5389 { Bad_Opcode },
5390 { Bad_Opcode },
5391 { Bad_Opcode },
5392 { Bad_Opcode },
5393 { Bad_Opcode },
5394 /* b0 */
5395 { Bad_Opcode },
5396 { Bad_Opcode },
5397 { Bad_Opcode },
5398 { Bad_Opcode },
5399 { Bad_Opcode },
5400 { Bad_Opcode },
5401 { VEX_LEN_TABLE (VEX_LEN_XOP_08_B6) },
5402 { Bad_Opcode },
5403 /* b8 */
5404 { Bad_Opcode },
5405 { Bad_Opcode },
5406 { Bad_Opcode },
5407 { Bad_Opcode },
5408 { Bad_Opcode },
5409 { Bad_Opcode },
5410 { Bad_Opcode },
5411 { Bad_Opcode },
5412 /* c0 */
5413 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C0) },
5414 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C1) },
5415 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C2) },
5416 { VEX_LEN_TABLE (VEX_LEN_XOP_08_C3) },
5417 { Bad_Opcode },
5418 { Bad_Opcode },
5419 { Bad_Opcode },
5420 { Bad_Opcode },
5421 /* c8 */
5422 { Bad_Opcode },
5423 { Bad_Opcode },
5424 { Bad_Opcode },
5425 { Bad_Opcode },
5426 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CC) },
5427 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CD) },
5428 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CE) },
5429 { VEX_LEN_TABLE (VEX_LEN_XOP_08_CF) },
5430 /* d0 */
5431 { Bad_Opcode },
5432 { Bad_Opcode },
5433 { Bad_Opcode },
5434 { Bad_Opcode },
5435 { Bad_Opcode },
5436 { Bad_Opcode },
5437 { Bad_Opcode },
5438 { Bad_Opcode },
5439 /* d8 */
5440 { Bad_Opcode },
5441 { Bad_Opcode },
5442 { Bad_Opcode },
5443 { Bad_Opcode },
5444 { Bad_Opcode },
5445 { Bad_Opcode },
5446 { Bad_Opcode },
5447 { Bad_Opcode },
5448 /* e0 */
5449 { Bad_Opcode },
5450 { Bad_Opcode },
5451 { Bad_Opcode },
5452 { Bad_Opcode },
5453 { Bad_Opcode },
5454 { Bad_Opcode },
5455 { Bad_Opcode },
5456 { Bad_Opcode },
5457 /* e8 */
5458 { Bad_Opcode },
5459 { Bad_Opcode },
5460 { Bad_Opcode },
5461 { Bad_Opcode },
5462 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EC) },
5463 { VEX_LEN_TABLE (VEX_LEN_XOP_08_ED) },
5464 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EE) },
5465 { VEX_LEN_TABLE (VEX_LEN_XOP_08_EF) },
5466 /* f0 */
5467 { Bad_Opcode },
5468 { Bad_Opcode },
5469 { Bad_Opcode },
5470 { Bad_Opcode },
5471 { Bad_Opcode },
5472 { Bad_Opcode },
5473 { Bad_Opcode },
5474 { Bad_Opcode },
5475 /* f8 */
5476 { Bad_Opcode },
5477 { Bad_Opcode },
5478 { Bad_Opcode },
5479 { Bad_Opcode },
5480 { Bad_Opcode },
5481 { Bad_Opcode },
5482 { Bad_Opcode },
5483 { Bad_Opcode },
5484 },
5485 /* XOP_09 */
5486 {
5487 /* 00 */
5488 { Bad_Opcode },
5489 { VEX_LEN_TABLE (VEX_LEN_XOP_09_01) },
5490 { VEX_LEN_TABLE (VEX_LEN_XOP_09_02) },
5491 { Bad_Opcode },
5492 { Bad_Opcode },
5493 { Bad_Opcode },
5494 { Bad_Opcode },
5495 { Bad_Opcode },
5496 /* 08 */
5497 { Bad_Opcode },
5498 { Bad_Opcode },
5499 { Bad_Opcode },
5500 { Bad_Opcode },
5501 { Bad_Opcode },
5502 { Bad_Opcode },
5503 { Bad_Opcode },
5504 { Bad_Opcode },
5505 /* 10 */
5506 { Bad_Opcode },
5507 { Bad_Opcode },
5508 { VEX_LEN_TABLE (VEX_LEN_XOP_09_12) },
5509 { Bad_Opcode },
5510 { Bad_Opcode },
5511 { Bad_Opcode },
5512 { Bad_Opcode },
5513 { Bad_Opcode },
5514 /* 18 */
5515 { Bad_Opcode },
5516 { Bad_Opcode },
5517 { Bad_Opcode },
5518 { Bad_Opcode },
5519 { Bad_Opcode },
5520 { Bad_Opcode },
5521 { Bad_Opcode },
5522 { Bad_Opcode },
5523 /* 20 */
5524 { Bad_Opcode },
5525 { Bad_Opcode },
5526 { Bad_Opcode },
5527 { Bad_Opcode },
5528 { Bad_Opcode },
5529 { Bad_Opcode },
5530 { Bad_Opcode },
5531 { Bad_Opcode },
5532 /* 28 */
5533 { Bad_Opcode },
5534 { Bad_Opcode },
5535 { Bad_Opcode },
5536 { Bad_Opcode },
5537 { Bad_Opcode },
5538 { Bad_Opcode },
5539 { Bad_Opcode },
5540 { Bad_Opcode },
5541 /* 30 */
5542 { Bad_Opcode },
5543 { Bad_Opcode },
5544 { Bad_Opcode },
5545 { Bad_Opcode },
5546 { Bad_Opcode },
5547 { Bad_Opcode },
5548 { Bad_Opcode },
5549 { Bad_Opcode },
5550 /* 38 */
5551 { Bad_Opcode },
5552 { Bad_Opcode },
5553 { Bad_Opcode },
5554 { Bad_Opcode },
5555 { Bad_Opcode },
5556 { Bad_Opcode },
5557 { Bad_Opcode },
5558 { Bad_Opcode },
5559 /* 40 */
5560 { Bad_Opcode },
5561 { Bad_Opcode },
5562 { Bad_Opcode },
5563 { Bad_Opcode },
5564 { Bad_Opcode },
5565 { Bad_Opcode },
5566 { Bad_Opcode },
5567 { Bad_Opcode },
5568 /* 48 */
5569 { Bad_Opcode },
5570 { Bad_Opcode },
5571 { Bad_Opcode },
5572 { Bad_Opcode },
5573 { Bad_Opcode },
5574 { Bad_Opcode },
5575 { Bad_Opcode },
5576 { Bad_Opcode },
5577 /* 50 */
5578 { Bad_Opcode },
5579 { Bad_Opcode },
5580 { Bad_Opcode },
5581 { Bad_Opcode },
5582 { Bad_Opcode },
5583 { Bad_Opcode },
5584 { Bad_Opcode },
5585 { Bad_Opcode },
5586 /* 58 */
5587 { Bad_Opcode },
5588 { Bad_Opcode },
5589 { Bad_Opcode },
5590 { Bad_Opcode },
5591 { Bad_Opcode },
5592 { Bad_Opcode },
5593 { Bad_Opcode },
5594 { Bad_Opcode },
5595 /* 60 */
5596 { Bad_Opcode },
5597 { Bad_Opcode },
5598 { Bad_Opcode },
5599 { Bad_Opcode },
5600 { Bad_Opcode },
5601 { Bad_Opcode },
5602 { Bad_Opcode },
5603 { Bad_Opcode },
5604 /* 68 */
5605 { Bad_Opcode },
5606 { Bad_Opcode },
5607 { Bad_Opcode },
5608 { Bad_Opcode },
5609 { Bad_Opcode },
5610 { Bad_Opcode },
5611 { Bad_Opcode },
5612 { Bad_Opcode },
5613 /* 70 */
5614 { Bad_Opcode },
5615 { Bad_Opcode },
5616 { Bad_Opcode },
5617 { Bad_Opcode },
5618 { Bad_Opcode },
5619 { Bad_Opcode },
5620 { Bad_Opcode },
5621 { Bad_Opcode },
5622 /* 78 */
5623 { Bad_Opcode },
5624 { Bad_Opcode },
5625 { Bad_Opcode },
5626 { Bad_Opcode },
5627 { Bad_Opcode },
5628 { Bad_Opcode },
5629 { Bad_Opcode },
5630 { Bad_Opcode },
5631 /* 80 */
5632 { VEX_W_TABLE (VEX_W_XOP_09_80) },
5633 { VEX_W_TABLE (VEX_W_XOP_09_81) },
5634 { VEX_W_TABLE (VEX_W_XOP_09_82) },
5635 { VEX_W_TABLE (VEX_W_XOP_09_83) },
5636 { Bad_Opcode },
5637 { Bad_Opcode },
5638 { Bad_Opcode },
5639 { Bad_Opcode },
5640 /* 88 */
5641 { Bad_Opcode },
5642 { Bad_Opcode },
5643 { Bad_Opcode },
5644 { Bad_Opcode },
5645 { Bad_Opcode },
5646 { Bad_Opcode },
5647 { Bad_Opcode },
5648 { Bad_Opcode },
5649 /* 90 */
5650 { VEX_LEN_TABLE (VEX_LEN_XOP_09_90) },
5651 { VEX_LEN_TABLE (VEX_LEN_XOP_09_91) },
5652 { VEX_LEN_TABLE (VEX_LEN_XOP_09_92) },
5653 { VEX_LEN_TABLE (VEX_LEN_XOP_09_93) },
5654 { VEX_LEN_TABLE (VEX_LEN_XOP_09_94) },
5655 { VEX_LEN_TABLE (VEX_LEN_XOP_09_95) },
5656 { VEX_LEN_TABLE (VEX_LEN_XOP_09_96) },
5657 { VEX_LEN_TABLE (VEX_LEN_XOP_09_97) },
5658 /* 98 */
5659 { VEX_LEN_TABLE (VEX_LEN_XOP_09_98) },
5660 { VEX_LEN_TABLE (VEX_LEN_XOP_09_99) },
5661 { VEX_LEN_TABLE (VEX_LEN_XOP_09_9A) },
5662 { VEX_LEN_TABLE (VEX_LEN_XOP_09_9B) },
5663 { Bad_Opcode },
5664 { Bad_Opcode },
5665 { Bad_Opcode },
5666 { Bad_Opcode },
5667 /* a0 */
5668 { Bad_Opcode },
5669 { Bad_Opcode },
5670 { Bad_Opcode },
5671 { Bad_Opcode },
5672 { Bad_Opcode },
5673 { Bad_Opcode },
5674 { Bad_Opcode },
5675 { Bad_Opcode },
5676 /* a8 */
5677 { Bad_Opcode },
5678 { Bad_Opcode },
5679 { Bad_Opcode },
5680 { Bad_Opcode },
5681 { Bad_Opcode },
5682 { Bad_Opcode },
5683 { Bad_Opcode },
5684 { Bad_Opcode },
5685 /* b0 */
5686 { Bad_Opcode },
5687 { Bad_Opcode },
5688 { Bad_Opcode },
5689 { Bad_Opcode },
5690 { Bad_Opcode },
5691 { Bad_Opcode },
5692 { Bad_Opcode },
5693 { Bad_Opcode },
5694 /* b8 */
5695 { Bad_Opcode },
5696 { Bad_Opcode },
5697 { Bad_Opcode },
5698 { Bad_Opcode },
5699 { Bad_Opcode },
5700 { Bad_Opcode },
5701 { Bad_Opcode },
5702 { Bad_Opcode },
5703 /* c0 */
5704 { Bad_Opcode },
5705 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C1) },
5706 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C2) },
5707 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C3) },
5708 { Bad_Opcode },
5709 { Bad_Opcode },
5710 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C6) },
5711 { VEX_LEN_TABLE (VEX_LEN_XOP_09_C7) },
5712 /* c8 */
5713 { Bad_Opcode },
5714 { Bad_Opcode },
5715 { Bad_Opcode },
5716 { VEX_LEN_TABLE (VEX_LEN_XOP_09_CB) },
5717 { Bad_Opcode },
5718 { Bad_Opcode },
5719 { Bad_Opcode },
5720 { Bad_Opcode },
5721 /* d0 */
5722 { Bad_Opcode },
5723 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D1) },
5724 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D2) },
5725 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D3) },
5726 { Bad_Opcode },
5727 { Bad_Opcode },
5728 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D6) },
5729 { VEX_LEN_TABLE (VEX_LEN_XOP_09_D7) },
5730 /* d8 */
5731 { Bad_Opcode },
5732 { Bad_Opcode },
5733 { Bad_Opcode },
5734 { VEX_LEN_TABLE (VEX_LEN_XOP_09_DB) },
5735 { Bad_Opcode },
5736 { Bad_Opcode },
5737 { Bad_Opcode },
5738 { Bad_Opcode },
5739 /* e0 */
5740 { Bad_Opcode },
5741 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E1) },
5742 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E2) },
5743 { VEX_LEN_TABLE (VEX_LEN_XOP_09_E3) },
5744 { Bad_Opcode },
5745 { Bad_Opcode },
5746 { Bad_Opcode },
5747 { Bad_Opcode },
5748 /* e8 */
5749 { Bad_Opcode },
5750 { Bad_Opcode },
5751 { Bad_Opcode },
5752 { Bad_Opcode },
5753 { Bad_Opcode },
5754 { Bad_Opcode },
5755 { Bad_Opcode },
5756 { Bad_Opcode },
5757 /* f0 */
5758 { Bad_Opcode },
5759 { Bad_Opcode },
5760 { Bad_Opcode },
5761 { Bad_Opcode },
5762 { Bad_Opcode },
5763 { Bad_Opcode },
5764 { Bad_Opcode },
5765 { Bad_Opcode },
5766 /* f8 */
5767 { Bad_Opcode },
5768 { Bad_Opcode },
5769 { Bad_Opcode },
5770 { Bad_Opcode },
5771 { Bad_Opcode },
5772 { Bad_Opcode },
5773 { Bad_Opcode },
5774 { Bad_Opcode },
5775 },
5776 /* XOP_0A */
5777 {
5778 /* 00 */
5779 { Bad_Opcode },
5780 { Bad_Opcode },
5781 { Bad_Opcode },
5782 { Bad_Opcode },
5783 { Bad_Opcode },
5784 { Bad_Opcode },
5785 { Bad_Opcode },
5786 { Bad_Opcode },
5787 /* 08 */
5788 { Bad_Opcode },
5789 { Bad_Opcode },
5790 { Bad_Opcode },
5791 { Bad_Opcode },
5792 { Bad_Opcode },
5793 { Bad_Opcode },
5794 { Bad_Opcode },
5795 { Bad_Opcode },
5796 /* 10 */
5797 { "bextrS", { Gdq, Edq, Id }, 0 },
5798 { Bad_Opcode },
5799 { VEX_LEN_TABLE (VEX_LEN_XOP_0A_12) },
5800 { Bad_Opcode },
5801 { Bad_Opcode },
5802 { Bad_Opcode },
5803 { Bad_Opcode },
5804 { Bad_Opcode },
5805 /* 18 */
5806 { Bad_Opcode },
5807 { Bad_Opcode },
5808 { Bad_Opcode },
5809 { Bad_Opcode },
5810 { Bad_Opcode },
5811 { Bad_Opcode },
5812 { Bad_Opcode },
5813 { Bad_Opcode },
5814 /* 20 */
5815 { Bad_Opcode },
5816 { Bad_Opcode },
5817 { Bad_Opcode },
5818 { Bad_Opcode },
5819 { Bad_Opcode },
5820 { Bad_Opcode },
5821 { Bad_Opcode },
5822 { Bad_Opcode },
5823 /* 28 */
5824 { Bad_Opcode },
5825 { Bad_Opcode },
5826 { Bad_Opcode },
5827 { Bad_Opcode },
5828 { Bad_Opcode },
5829 { Bad_Opcode },
5830 { Bad_Opcode },
5831 { Bad_Opcode },
5832 /* 30 */
5833 { Bad_Opcode },
5834 { Bad_Opcode },
5835 { Bad_Opcode },
5836 { Bad_Opcode },
5837 { Bad_Opcode },
5838 { Bad_Opcode },
5839 { Bad_Opcode },
5840 { Bad_Opcode },
5841 /* 38 */
5842 { Bad_Opcode },
5843 { Bad_Opcode },
5844 { Bad_Opcode },
5845 { Bad_Opcode },
5846 { Bad_Opcode },
5847 { Bad_Opcode },
5848 { Bad_Opcode },
5849 { Bad_Opcode },
5850 /* 40 */
5851 { Bad_Opcode },
5852 { Bad_Opcode },
5853 { Bad_Opcode },
5854 { Bad_Opcode },
5855 { Bad_Opcode },
5856 { Bad_Opcode },
5857 { Bad_Opcode },
5858 { Bad_Opcode },
5859 /* 48 */
5860 { Bad_Opcode },
5861 { Bad_Opcode },
5862 { Bad_Opcode },
5863 { Bad_Opcode },
5864 { Bad_Opcode },
5865 { Bad_Opcode },
5866 { Bad_Opcode },
5867 { Bad_Opcode },
5868 /* 50 */
5869 { Bad_Opcode },
5870 { Bad_Opcode },
5871 { Bad_Opcode },
5872 { Bad_Opcode },
5873 { Bad_Opcode },
5874 { Bad_Opcode },
5875 { Bad_Opcode },
5876 { Bad_Opcode },
5877 /* 58 */
5878 { Bad_Opcode },
5879 { Bad_Opcode },
5880 { Bad_Opcode },
5881 { Bad_Opcode },
5882 { Bad_Opcode },
5883 { Bad_Opcode },
5884 { Bad_Opcode },
5885 { Bad_Opcode },
5886 /* 60 */
5887 { Bad_Opcode },
5888 { Bad_Opcode },
5889 { Bad_Opcode },
5890 { Bad_Opcode },
5891 { Bad_Opcode },
5892 { Bad_Opcode },
5893 { Bad_Opcode },
5894 { Bad_Opcode },
5895 /* 68 */
5896 { Bad_Opcode },
5897 { Bad_Opcode },
5898 { Bad_Opcode },
5899 { Bad_Opcode },
5900 { Bad_Opcode },
5901 { Bad_Opcode },
5902 { Bad_Opcode },
5903 { Bad_Opcode },
5904 /* 70 */
5905 { Bad_Opcode },
5906 { Bad_Opcode },
5907 { Bad_Opcode },
5908 { Bad_Opcode },
5909 { Bad_Opcode },
5910 { Bad_Opcode },
5911 { Bad_Opcode },
5912 { Bad_Opcode },
5913 /* 78 */
5914 { Bad_Opcode },
5915 { Bad_Opcode },
5916 { Bad_Opcode },
5917 { Bad_Opcode },
5918 { Bad_Opcode },
5919 { Bad_Opcode },
5920 { Bad_Opcode },
5921 { Bad_Opcode },
5922 /* 80 */
5923 { Bad_Opcode },
5924 { Bad_Opcode },
5925 { Bad_Opcode },
5926 { Bad_Opcode },
5927 { Bad_Opcode },
5928 { Bad_Opcode },
5929 { Bad_Opcode },
5930 { Bad_Opcode },
5931 /* 88 */
5932 { Bad_Opcode },
5933 { Bad_Opcode },
5934 { Bad_Opcode },
5935 { Bad_Opcode },
5936 { Bad_Opcode },
5937 { Bad_Opcode },
5938 { Bad_Opcode },
5939 { Bad_Opcode },
5940 /* 90 */
5941 { Bad_Opcode },
5942 { Bad_Opcode },
5943 { Bad_Opcode },
5944 { Bad_Opcode },
5945 { Bad_Opcode },
5946 { Bad_Opcode },
5947 { Bad_Opcode },
5948 { Bad_Opcode },
5949 /* 98 */
5950 { Bad_Opcode },
5951 { Bad_Opcode },
5952 { Bad_Opcode },
5953 { Bad_Opcode },
5954 { Bad_Opcode },
5955 { Bad_Opcode },
5956 { Bad_Opcode },
5957 { Bad_Opcode },
5958 /* a0 */
5959 { Bad_Opcode },
5960 { Bad_Opcode },
5961 { Bad_Opcode },
5962 { Bad_Opcode },
5963 { Bad_Opcode },
5964 { Bad_Opcode },
5965 { Bad_Opcode },
5966 { Bad_Opcode },
5967 /* a8 */
5968 { Bad_Opcode },
5969 { Bad_Opcode },
5970 { Bad_Opcode },
5971 { Bad_Opcode },
5972 { Bad_Opcode },
5973 { Bad_Opcode },
5974 { Bad_Opcode },
5975 { Bad_Opcode },
5976 /* b0 */
5977 { Bad_Opcode },
5978 { Bad_Opcode },
5979 { Bad_Opcode },
5980 { Bad_Opcode },
5981 { Bad_Opcode },
5982 { Bad_Opcode },
5983 { Bad_Opcode },
5984 { Bad_Opcode },
5985 /* b8 */
5986 { Bad_Opcode },
5987 { Bad_Opcode },
5988 { Bad_Opcode },
5989 { Bad_Opcode },
5990 { Bad_Opcode },
5991 { Bad_Opcode },
5992 { Bad_Opcode },
5993 { Bad_Opcode },
5994 /* c0 */
5995 { Bad_Opcode },
5996 { Bad_Opcode },
5997 { Bad_Opcode },
5998 { Bad_Opcode },
5999 { Bad_Opcode },
6000 { Bad_Opcode },
6001 { Bad_Opcode },
6002 { Bad_Opcode },
6003 /* c8 */
6004 { Bad_Opcode },
6005 { Bad_Opcode },
6006 { Bad_Opcode },
6007 { Bad_Opcode },
6008 { Bad_Opcode },
6009 { Bad_Opcode },
6010 { Bad_Opcode },
6011 { Bad_Opcode },
6012 /* d0 */
6013 { Bad_Opcode },
6014 { Bad_Opcode },
6015 { Bad_Opcode },
6016 { Bad_Opcode },
6017 { Bad_Opcode },
6018 { Bad_Opcode },
6019 { Bad_Opcode },
6020 { Bad_Opcode },
6021 /* d8 */
6022 { Bad_Opcode },
6023 { Bad_Opcode },
6024 { Bad_Opcode },
6025 { Bad_Opcode },
6026 { Bad_Opcode },
6027 { Bad_Opcode },
6028 { Bad_Opcode },
6029 { Bad_Opcode },
6030 /* e0 */
6031 { Bad_Opcode },
6032 { Bad_Opcode },
6033 { Bad_Opcode },
6034 { Bad_Opcode },
6035 { Bad_Opcode },
6036 { Bad_Opcode },
6037 { Bad_Opcode },
6038 { Bad_Opcode },
6039 /* e8 */
6040 { Bad_Opcode },
6041 { Bad_Opcode },
6042 { Bad_Opcode },
6043 { Bad_Opcode },
6044 { Bad_Opcode },
6045 { Bad_Opcode },
6046 { Bad_Opcode },
6047 { Bad_Opcode },
6048 /* f0 */
6049 { Bad_Opcode },
6050 { Bad_Opcode },
6051 { Bad_Opcode },
6052 { Bad_Opcode },
6053 { Bad_Opcode },
6054 { Bad_Opcode },
6055 { Bad_Opcode },
6056 { Bad_Opcode },
6057 /* f8 */
6058 { Bad_Opcode },
6059 { Bad_Opcode },
6060 { Bad_Opcode },
6061 { Bad_Opcode },
6062 { Bad_Opcode },
6063 { Bad_Opcode },
6064 { Bad_Opcode },
6065 { Bad_Opcode },
6066 },
6067 };
6068
6069 static const struct dis386 vex_table[][256] = {
6070 /* VEX_0F */
6071 {
6072 /* 00 */
6073 { Bad_Opcode },
6074 { Bad_Opcode },
6075 { Bad_Opcode },
6076 { Bad_Opcode },
6077 { Bad_Opcode },
6078 { Bad_Opcode },
6079 { Bad_Opcode },
6080 { Bad_Opcode },
6081 /* 08 */
6082 { Bad_Opcode },
6083 { Bad_Opcode },
6084 { Bad_Opcode },
6085 { Bad_Opcode },
6086 { Bad_Opcode },
6087 { Bad_Opcode },
6088 { Bad_Opcode },
6089 { Bad_Opcode },
6090 /* 10 */
6091 { PREFIX_TABLE (PREFIX_0F10) },
6092 { PREFIX_TABLE (PREFIX_0F11) },
6093 { PREFIX_TABLE (PREFIX_VEX_0F12) },
6094 { VEX_LEN_TABLE (VEX_LEN_0F13) },
6095 { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6096 { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6097 { PREFIX_TABLE (PREFIX_VEX_0F16) },
6098 { VEX_LEN_TABLE (VEX_LEN_0F17) },
6099 /* 18 */
6100 { Bad_Opcode },
6101 { Bad_Opcode },
6102 { Bad_Opcode },
6103 { Bad_Opcode },
6104 { Bad_Opcode },
6105 { Bad_Opcode },
6106 { Bad_Opcode },
6107 { Bad_Opcode },
6108 /* 20 */
6109 { Bad_Opcode },
6110 { Bad_Opcode },
6111 { Bad_Opcode },
6112 { Bad_Opcode },
6113 { Bad_Opcode },
6114 { Bad_Opcode },
6115 { Bad_Opcode },
6116 { Bad_Opcode },
6117 /* 28 */
6118 { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
6119 { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
6120 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
6121 { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
6122 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
6123 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
6124 { PREFIX_TABLE (PREFIX_0F2E) },
6125 { PREFIX_TABLE (PREFIX_0F2F) },
6126 /* 30 */
6127 { Bad_Opcode },
6128 { Bad_Opcode },
6129 { Bad_Opcode },
6130 { Bad_Opcode },
6131 { Bad_Opcode },
6132 { Bad_Opcode },
6133 { Bad_Opcode },
6134 { Bad_Opcode },
6135 /* 38 */
6136 { Bad_Opcode },
6137 { Bad_Opcode },
6138 { Bad_Opcode },
6139 { Bad_Opcode },
6140 { Bad_Opcode },
6141 { Bad_Opcode },
6142 { Bad_Opcode },
6143 { Bad_Opcode },
6144 /* 40 */
6145 { Bad_Opcode },
6146 { VEX_LEN_TABLE (VEX_LEN_0F41) },
6147 { VEX_LEN_TABLE (VEX_LEN_0F42) },
6148 { Bad_Opcode },
6149 { VEX_LEN_TABLE (VEX_LEN_0F44) },
6150 { VEX_LEN_TABLE (VEX_LEN_0F45) },
6151 { VEX_LEN_TABLE (VEX_LEN_0F46) },
6152 { VEX_LEN_TABLE (VEX_LEN_0F47) },
6153 /* 48 */
6154 { Bad_Opcode },
6155 { Bad_Opcode },
6156 { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6157 { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6158 { Bad_Opcode },
6159 { Bad_Opcode },
6160 { Bad_Opcode },
6161 { Bad_Opcode },
6162 /* 50 */
6163 { "vmovmskpX", { Gdq, Ux }, PREFIX_OPCODE },
6164 { PREFIX_TABLE (PREFIX_0F51) },
6165 { PREFIX_TABLE (PREFIX_0F52) },
6166 { PREFIX_TABLE (PREFIX_0F53) },
6167 { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6168 { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6169 { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6170 { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
6171 /* 58 */
6172 { PREFIX_TABLE (PREFIX_0F58) },
6173 { PREFIX_TABLE (PREFIX_0F59) },
6174 { PREFIX_TABLE (PREFIX_0F5A) },
6175 { PREFIX_TABLE (PREFIX_0F5B) },
6176 { PREFIX_TABLE (PREFIX_0F5C) },
6177 { PREFIX_TABLE (PREFIX_0F5D) },
6178 { PREFIX_TABLE (PREFIX_0F5E) },
6179 { PREFIX_TABLE (PREFIX_0F5F) },
6180 /* 60 */
6181 { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
6182 { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
6183 { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
6184 { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
6185 { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
6186 { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
6187 { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
6188 { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
6189 /* 68 */
6190 { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
6191 { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
6192 { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
6193 { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
6194 { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
6195 { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
6196 { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6197 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6198 /* 70 */
6199 { PREFIX_TABLE (PREFIX_VEX_0F70) },
6200 { REG_TABLE (REG_VEX_0F71) },
6201 { REG_TABLE (REG_VEX_0F72) },
6202 { REG_TABLE (REG_VEX_0F73) },
6203 { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
6204 { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
6205 { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
6206 { VEX_LEN_TABLE (VEX_LEN_0F77) },
6207 /* 78 */
6208 { Bad_Opcode },
6209 { Bad_Opcode },
6210 { Bad_Opcode },
6211 { Bad_Opcode },
6212 { PREFIX_TABLE (PREFIX_0F7C) },
6213 { PREFIX_TABLE (PREFIX_0F7D) },
6214 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6215 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6216 /* 80 */
6217 { Bad_Opcode },
6218 { Bad_Opcode },
6219 { Bad_Opcode },
6220 { Bad_Opcode },
6221 { Bad_Opcode },
6222 { Bad_Opcode },
6223 { Bad_Opcode },
6224 { Bad_Opcode },
6225 /* 88 */
6226 { Bad_Opcode },
6227 { Bad_Opcode },
6228 { Bad_Opcode },
6229 { Bad_Opcode },
6230 { Bad_Opcode },
6231 { Bad_Opcode },
6232 { Bad_Opcode },
6233 { Bad_Opcode },
6234 /* 90 */
6235 { VEX_LEN_TABLE (VEX_LEN_0F90) },
6236 { VEX_LEN_TABLE (VEX_LEN_0F91) },
6237 { VEX_LEN_TABLE (VEX_LEN_0F92) },
6238 { VEX_LEN_TABLE (VEX_LEN_0F93) },
6239 { Bad_Opcode },
6240 { Bad_Opcode },
6241 { Bad_Opcode },
6242 { Bad_Opcode },
6243 /* 98 */
6244 { VEX_LEN_TABLE (VEX_LEN_0F98) },
6245 { VEX_LEN_TABLE (VEX_LEN_0F99) },
6246 { Bad_Opcode },
6247 { Bad_Opcode },
6248 { Bad_Opcode },
6249 { Bad_Opcode },
6250 { Bad_Opcode },
6251 { Bad_Opcode },
6252 /* a0 */
6253 { Bad_Opcode },
6254 { Bad_Opcode },
6255 { Bad_Opcode },
6256 { Bad_Opcode },
6257 { Bad_Opcode },
6258 { Bad_Opcode },
6259 { Bad_Opcode },
6260 { Bad_Opcode },
6261 /* a8 */
6262 { Bad_Opcode },
6263 { Bad_Opcode },
6264 { Bad_Opcode },
6265 { Bad_Opcode },
6266 { Bad_Opcode },
6267 { Bad_Opcode },
6268 { REG_TABLE (REG_VEX_0FAE) },
6269 { Bad_Opcode },
6270 /* b0 */
6271 { Bad_Opcode },
6272 { Bad_Opcode },
6273 { Bad_Opcode },
6274 { Bad_Opcode },
6275 { Bad_Opcode },
6276 { Bad_Opcode },
6277 { Bad_Opcode },
6278 { Bad_Opcode },
6279 /* b8 */
6280 { Bad_Opcode },
6281 { Bad_Opcode },
6282 { Bad_Opcode },
6283 { Bad_Opcode },
6284 { Bad_Opcode },
6285 { Bad_Opcode },
6286 { Bad_Opcode },
6287 { Bad_Opcode },
6288 /* c0 */
6289 { Bad_Opcode },
6290 { Bad_Opcode },
6291 { PREFIX_TABLE (PREFIX_0FC2) },
6292 { Bad_Opcode },
6293 { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6294 { "vpextrw", { Gd, Uxmm, Ib }, PREFIX_DATA },
6295 { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6296 { Bad_Opcode },
6297 /* c8 */
6298 { Bad_Opcode },
6299 { Bad_Opcode },
6300 { Bad_Opcode },
6301 { Bad_Opcode },
6302 { Bad_Opcode },
6303 { Bad_Opcode },
6304 { Bad_Opcode },
6305 { Bad_Opcode },
6306 /* d0 */
6307 { PREFIX_TABLE (PREFIX_0FD0) },
6308 { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
6309 { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
6310 { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
6311 { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
6312 { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
6313 { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6314 { "vpmovmskb", { Gdq, Ux }, PREFIX_DATA },
6315 /* d8 */
6316 { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
6317 { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
6318 { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
6319 { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
6320 { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
6321 { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
6322 { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
6323 { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
6324 /* e0 */
6325 { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
6326 { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
6327 { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
6328 { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
6329 { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
6330 { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
6331 { PREFIX_TABLE (PREFIX_0FE6) },
6332 { "vmovntdq", { Mx, XM }, PREFIX_DATA },
6333 /* e8 */
6334 { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
6335 { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6336 { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
6337 { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
6338 { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
6339 { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6340 { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
6341 { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
6342 /* f0 */
6343 { PREFIX_TABLE (PREFIX_0FF0) },
6344 { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
6345 { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
6346 { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
6347 { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
6348 { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
6349 { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
6350 { "vmaskmovdqu", { XM, Uxmm }, PREFIX_DATA },
6351 /* f8 */
6352 { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
6353 { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
6354 { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
6355 { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
6356 { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
6357 { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
6358 { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
6359 { Bad_Opcode },
6360 },
6361 /* VEX_0F38 */
6362 {
6363 /* 00 */
6364 { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
6365 { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
6366 { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
6367 { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
6368 { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
6369 { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
6370 { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
6371 { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
6372 /* 08 */
6373 { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
6374 { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
6375 { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
6376 { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
6377 { VEX_W_TABLE (VEX_W_0F380C) },
6378 { VEX_W_TABLE (VEX_W_0F380D) },
6379 { VEX_W_TABLE (VEX_W_0F380E) },
6380 { VEX_W_TABLE (VEX_W_0F380F) },
6381 /* 10 */
6382 { Bad_Opcode },
6383 { Bad_Opcode },
6384 { Bad_Opcode },
6385 { VEX_W_TABLE (VEX_W_0F3813) },
6386 { Bad_Opcode },
6387 { Bad_Opcode },
6388 { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6389 { "vptest", { XM, EXx }, PREFIX_DATA },
6390 /* 18 */
6391 { VEX_W_TABLE (VEX_W_0F3818) },
6392 { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6393 { VEX_LEN_TABLE (VEX_LEN_0F381A) },
6394 { Bad_Opcode },
6395 { "vpabsb", { XM, EXx }, PREFIX_DATA },
6396 { "vpabsw", { XM, EXx }, PREFIX_DATA },
6397 { "vpabsd", { XM, EXx }, PREFIX_DATA },
6398 { Bad_Opcode },
6399 /* 20 */
6400 { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
6401 { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
6402 { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
6403 { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
6404 { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
6405 { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
6406 { Bad_Opcode },
6407 { Bad_Opcode },
6408 /* 28 */
6409 { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
6410 { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
6411 { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
6412 { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
6413 { VEX_W_TABLE (VEX_W_0F382C) },
6414 { VEX_W_TABLE (VEX_W_0F382D) },
6415 { VEX_W_TABLE (VEX_W_0F382E) },
6416 { VEX_W_TABLE (VEX_W_0F382F) },
6417 /* 30 */
6418 { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
6419 { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
6420 { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
6421 { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
6422 { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
6423 { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
6424 { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6425 { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
6426 /* 38 */
6427 { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
6428 { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
6429 { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
6430 { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
6431 { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
6432 { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
6433 { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
6434 { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
6435 /* 40 */
6436 { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
6437 { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6438 { Bad_Opcode },
6439 { Bad_Opcode },
6440 { Bad_Opcode },
6441 { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6442 { VEX_W_TABLE (VEX_W_0F3846) },
6443 { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6444 /* 48 */
6445 { Bad_Opcode },
6446 { X86_64_TABLE (X86_64_VEX_0F3849) },
6447 { Bad_Opcode },
6448 { X86_64_TABLE (X86_64_VEX_0F384B) },
6449 { Bad_Opcode },
6450 { Bad_Opcode },
6451 { Bad_Opcode },
6452 { Bad_Opcode },
6453 /* 50 */
6454 { VEX_W_TABLE (VEX_W_0F3850) },
6455 { VEX_W_TABLE (VEX_W_0F3851) },
6456 { VEX_W_TABLE (VEX_W_0F3852) },
6457 { VEX_W_TABLE (VEX_W_0F3853) },
6458 { Bad_Opcode },
6459 { Bad_Opcode },
6460 { Bad_Opcode },
6461 { Bad_Opcode },
6462 /* 58 */
6463 { VEX_W_TABLE (VEX_W_0F3858) },
6464 { VEX_W_TABLE (VEX_W_0F3859) },
6465 { VEX_LEN_TABLE (VEX_LEN_0F385A) },
6466 { Bad_Opcode },
6467 { X86_64_TABLE (X86_64_VEX_0F385C) },
6468 { Bad_Opcode },
6469 { X86_64_TABLE (X86_64_VEX_0F385E) },
6470 { Bad_Opcode },
6471 /* 60 */
6472 { Bad_Opcode },
6473 { Bad_Opcode },
6474 { Bad_Opcode },
6475 { Bad_Opcode },
6476 { Bad_Opcode },
6477 { Bad_Opcode },
6478 { Bad_Opcode },
6479 { Bad_Opcode },
6480 /* 68 */
6481 { Bad_Opcode },
6482 { Bad_Opcode },
6483 { Bad_Opcode },
6484 { Bad_Opcode },
6485 { X86_64_TABLE (X86_64_VEX_0F386C) },
6486 { Bad_Opcode },
6487 { Bad_Opcode },
6488 { Bad_Opcode },
6489 /* 70 */
6490 { Bad_Opcode },
6491 { Bad_Opcode },
6492 { PREFIX_TABLE (PREFIX_VEX_0F3872) },
6493 { Bad_Opcode },
6494 { Bad_Opcode },
6495 { Bad_Opcode },
6496 { Bad_Opcode },
6497 { Bad_Opcode },
6498 /* 78 */
6499 { VEX_W_TABLE (VEX_W_0F3878) },
6500 { VEX_W_TABLE (VEX_W_0F3879) },
6501 { Bad_Opcode },
6502 { Bad_Opcode },
6503 { Bad_Opcode },
6504 { Bad_Opcode },
6505 { Bad_Opcode },
6506 { Bad_Opcode },
6507 /* 80 */
6508 { Bad_Opcode },
6509 { Bad_Opcode },
6510 { Bad_Opcode },
6511 { Bad_Opcode },
6512 { Bad_Opcode },
6513 { Bad_Opcode },
6514 { Bad_Opcode },
6515 { Bad_Opcode },
6516 /* 88 */
6517 { Bad_Opcode },
6518 { Bad_Opcode },
6519 { Bad_Opcode },
6520 { Bad_Opcode },
6521 { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
6522 { Bad_Opcode },
6523 { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
6524 { Bad_Opcode },
6525 /* 90 */
6526 { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6527 { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6528 { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6529 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6530 { Bad_Opcode },
6531 { Bad_Opcode },
6532 { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6533 { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6534 /* 98 */
6535 { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6536 { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6537 { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6538 { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6539 { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6540 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6541 { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6542 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6543 /* a0 */
6544 { Bad_Opcode },
6545 { Bad_Opcode },
6546 { Bad_Opcode },
6547 { Bad_Opcode },
6548 { Bad_Opcode },
6549 { Bad_Opcode },
6550 { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6551 { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6552 /* a8 */
6553 { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6554 { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6555 { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6556 { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6557 { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6558 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6559 { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6560 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6561 /* b0 */
6562 { VEX_W_TABLE (VEX_W_0F38B0) },
6563 { VEX_W_TABLE (VEX_W_0F38B1) },
6564 { Bad_Opcode },
6565 { Bad_Opcode },
6566 { VEX_W_TABLE (VEX_W_0F38B4) },
6567 { VEX_W_TABLE (VEX_W_0F38B5) },
6568 { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6569 { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6570 /* b8 */
6571 { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6572 { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6573 { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6574 { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6575 { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6576 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6577 { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6578 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6579 /* c0 */
6580 { Bad_Opcode },
6581 { Bad_Opcode },
6582 { Bad_Opcode },
6583 { Bad_Opcode },
6584 { Bad_Opcode },
6585 { Bad_Opcode },
6586 { Bad_Opcode },
6587 { Bad_Opcode },
6588 /* c8 */
6589 { Bad_Opcode },
6590 { Bad_Opcode },
6591 { Bad_Opcode },
6592 { PREFIX_TABLE (PREFIX_VEX_0F38CB) },
6593 { PREFIX_TABLE (PREFIX_VEX_0F38CC) },
6594 { PREFIX_TABLE (PREFIX_VEX_0F38CD) },
6595 { Bad_Opcode },
6596 { VEX_W_TABLE (VEX_W_0F38CF) },
6597 /* d0 */
6598 { Bad_Opcode },
6599 { Bad_Opcode },
6600 { VEX_W_TABLE (VEX_W_0F38D2) },
6601 { VEX_W_TABLE (VEX_W_0F38D3) },
6602 { Bad_Opcode },
6603 { Bad_Opcode },
6604 { Bad_Opcode },
6605 { Bad_Opcode },
6606 /* d8 */
6607 { Bad_Opcode },
6608 { Bad_Opcode },
6609 { VEX_W_TABLE (VEX_W_0F38DA) },
6610 { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6611 { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
6612 { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
6613 { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
6614 { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
6615 /* e0 */
6616 { X86_64_TABLE (X86_64_VEX_0F38E0) },
6617 { X86_64_TABLE (X86_64_VEX_0F38E1) },
6618 { X86_64_TABLE (X86_64_VEX_0F38E2) },
6619 { X86_64_TABLE (X86_64_VEX_0F38E3) },
6620 { X86_64_TABLE (X86_64_VEX_0F38E4) },
6621 { X86_64_TABLE (X86_64_VEX_0F38E5) },
6622 { X86_64_TABLE (X86_64_VEX_0F38E6) },
6623 { X86_64_TABLE (X86_64_VEX_0F38E7) },
6624 /* e8 */
6625 { X86_64_TABLE (X86_64_VEX_0F38E8) },
6626 { X86_64_TABLE (X86_64_VEX_0F38E9) },
6627 { X86_64_TABLE (X86_64_VEX_0F38EA) },
6628 { X86_64_TABLE (X86_64_VEX_0F38EB) },
6629 { X86_64_TABLE (X86_64_VEX_0F38EC) },
6630 { X86_64_TABLE (X86_64_VEX_0F38ED) },
6631 { X86_64_TABLE (X86_64_VEX_0F38EE) },
6632 { X86_64_TABLE (X86_64_VEX_0F38EF) },
6633 /* f0 */
6634 { Bad_Opcode },
6635 { Bad_Opcode },
6636 { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6637 { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6638 { Bad_Opcode },
6639 { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6640 { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6641 { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6642 /* f8 */
6643 { Bad_Opcode },
6644 { Bad_Opcode },
6645 { Bad_Opcode },
6646 { Bad_Opcode },
6647 { Bad_Opcode },
6648 { Bad_Opcode },
6649 { Bad_Opcode },
6650 { Bad_Opcode },
6651 },
6652 /* VEX_0F3A */
6653 {
6654 /* 00 */
6655 { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6656 { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6657 { VEX_W_TABLE (VEX_W_0F3A02) },
6658 { Bad_Opcode },
6659 { VEX_W_TABLE (VEX_W_0F3A04) },
6660 { VEX_W_TABLE (VEX_W_0F3A05) },
6661 { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6662 { Bad_Opcode },
6663 /* 08 */
6664 { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
6665 { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
6666 { "vroundss", { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6667 { "vroundsd", { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6668 { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6669 { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6670 { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6671 { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6672 /* 10 */
6673 { Bad_Opcode },
6674 { Bad_Opcode },
6675 { Bad_Opcode },
6676 { Bad_Opcode },
6677 { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6678 { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6679 { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6680 { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6681 /* 18 */
6682 { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6683 { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6684 { Bad_Opcode },
6685 { Bad_Opcode },
6686 { Bad_Opcode },
6687 { VEX_W_TABLE (VEX_W_0F3A1D) },
6688 { Bad_Opcode },
6689 { Bad_Opcode },
6690 /* 20 */
6691 { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6692 { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6693 { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6694 { Bad_Opcode },
6695 { Bad_Opcode },
6696 { Bad_Opcode },
6697 { Bad_Opcode },
6698 { Bad_Opcode },
6699 /* 28 */
6700 { Bad_Opcode },
6701 { Bad_Opcode },
6702 { Bad_Opcode },
6703 { Bad_Opcode },
6704 { Bad_Opcode },
6705 { Bad_Opcode },
6706 { Bad_Opcode },
6707 { Bad_Opcode },
6708 /* 30 */
6709 { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6710 { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6711 { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6712 { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6713 { Bad_Opcode },
6714 { Bad_Opcode },
6715 { Bad_Opcode },
6716 { Bad_Opcode },
6717 /* 38 */
6718 { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6719 { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6720 { Bad_Opcode },
6721 { Bad_Opcode },
6722 { Bad_Opcode },
6723 { Bad_Opcode },
6724 { Bad_Opcode },
6725 { Bad_Opcode },
6726 /* 40 */
6727 { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6728 { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6729 { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
6730 { Bad_Opcode },
6731 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6732 { Bad_Opcode },
6733 { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6734 { Bad_Opcode },
6735 /* 48 */
6736 { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6737 { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6738 { VEX_W_TABLE (VEX_W_0F3A4A) },
6739 { VEX_W_TABLE (VEX_W_0F3A4B) },
6740 { VEX_W_TABLE (VEX_W_0F3A4C) },
6741 { Bad_Opcode },
6742 { Bad_Opcode },
6743 { Bad_Opcode },
6744 /* 50 */
6745 { Bad_Opcode },
6746 { Bad_Opcode },
6747 { Bad_Opcode },
6748 { Bad_Opcode },
6749 { Bad_Opcode },
6750 { Bad_Opcode },
6751 { Bad_Opcode },
6752 { Bad_Opcode },
6753 /* 58 */
6754 { Bad_Opcode },
6755 { Bad_Opcode },
6756 { Bad_Opcode },
6757 { Bad_Opcode },
6758 { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6759 { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6760 { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6761 { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6762 /* 60 */
6763 { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6764 { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6765 { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6766 { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6767 { Bad_Opcode },
6768 { Bad_Opcode },
6769 { Bad_Opcode },
6770 { Bad_Opcode },
6771 /* 68 */
6772 { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6773 { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6774 { "vfmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6775 { "vfmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6776 { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6777 { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6778 { "vfmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6779 { "vfmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6780 /* 70 */
6781 { Bad_Opcode },
6782 { Bad_Opcode },
6783 { Bad_Opcode },
6784 { Bad_Opcode },
6785 { Bad_Opcode },
6786 { Bad_Opcode },
6787 { Bad_Opcode },
6788 { Bad_Opcode },
6789 /* 78 */
6790 { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6791 { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6792 { "vfnmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6793 { "vfnmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6794 { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6795 { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6796 { "vfnmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6797 { "vfnmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6798 /* 80 */
6799 { Bad_Opcode },
6800 { Bad_Opcode },
6801 { Bad_Opcode },
6802 { Bad_Opcode },
6803 { Bad_Opcode },
6804 { Bad_Opcode },
6805 { Bad_Opcode },
6806 { Bad_Opcode },
6807 /* 88 */
6808 { Bad_Opcode },
6809 { Bad_Opcode },
6810 { Bad_Opcode },
6811 { Bad_Opcode },
6812 { Bad_Opcode },
6813 { Bad_Opcode },
6814 { Bad_Opcode },
6815 { Bad_Opcode },
6816 /* 90 */
6817 { Bad_Opcode },
6818 { Bad_Opcode },
6819 { Bad_Opcode },
6820 { Bad_Opcode },
6821 { Bad_Opcode },
6822 { Bad_Opcode },
6823 { Bad_Opcode },
6824 { Bad_Opcode },
6825 /* 98 */
6826 { Bad_Opcode },
6827 { Bad_Opcode },
6828 { Bad_Opcode },
6829 { Bad_Opcode },
6830 { Bad_Opcode },
6831 { Bad_Opcode },
6832 { Bad_Opcode },
6833 { Bad_Opcode },
6834 /* a0 */
6835 { Bad_Opcode },
6836 { Bad_Opcode },
6837 { Bad_Opcode },
6838 { Bad_Opcode },
6839 { Bad_Opcode },
6840 { Bad_Opcode },
6841 { Bad_Opcode },
6842 { Bad_Opcode },
6843 /* a8 */
6844 { Bad_Opcode },
6845 { Bad_Opcode },
6846 { Bad_Opcode },
6847 { Bad_Opcode },
6848 { Bad_Opcode },
6849 { Bad_Opcode },
6850 { Bad_Opcode },
6851 { Bad_Opcode },
6852 /* b0 */
6853 { Bad_Opcode },
6854 { Bad_Opcode },
6855 { Bad_Opcode },
6856 { Bad_Opcode },
6857 { Bad_Opcode },
6858 { Bad_Opcode },
6859 { Bad_Opcode },
6860 { Bad_Opcode },
6861 /* b8 */
6862 { Bad_Opcode },
6863 { Bad_Opcode },
6864 { Bad_Opcode },
6865 { Bad_Opcode },
6866 { Bad_Opcode },
6867 { Bad_Opcode },
6868 { Bad_Opcode },
6869 { Bad_Opcode },
6870 /* c0 */
6871 { Bad_Opcode },
6872 { Bad_Opcode },
6873 { Bad_Opcode },
6874 { Bad_Opcode },
6875 { Bad_Opcode },
6876 { Bad_Opcode },
6877 { Bad_Opcode },
6878 { Bad_Opcode },
6879 /* c8 */
6880 { Bad_Opcode },
6881 { Bad_Opcode },
6882 { Bad_Opcode },
6883 { Bad_Opcode },
6884 { Bad_Opcode },
6885 { Bad_Opcode },
6886 { VEX_W_TABLE (VEX_W_0F3ACE) },
6887 { VEX_W_TABLE (VEX_W_0F3ACF) },
6888 /* d0 */
6889 { Bad_Opcode },
6890 { Bad_Opcode },
6891 { Bad_Opcode },
6892 { Bad_Opcode },
6893 { Bad_Opcode },
6894 { Bad_Opcode },
6895 { Bad_Opcode },
6896 { Bad_Opcode },
6897 /* d8 */
6898 { Bad_Opcode },
6899 { Bad_Opcode },
6900 { Bad_Opcode },
6901 { Bad_Opcode },
6902 { Bad_Opcode },
6903 { Bad_Opcode },
6904 { VEX_W_TABLE (VEX_W_0F3ADE) },
6905 { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6906 /* e0 */
6907 { Bad_Opcode },
6908 { Bad_Opcode },
6909 { Bad_Opcode },
6910 { Bad_Opcode },
6911 { Bad_Opcode },
6912 { Bad_Opcode },
6913 { Bad_Opcode },
6914 { Bad_Opcode },
6915 /* e8 */
6916 { Bad_Opcode },
6917 { Bad_Opcode },
6918 { Bad_Opcode },
6919 { Bad_Opcode },
6920 { Bad_Opcode },
6921 { Bad_Opcode },
6922 { Bad_Opcode },
6923 { Bad_Opcode },
6924 /* f0 */
6925 { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6926 { Bad_Opcode },
6927 { Bad_Opcode },
6928 { Bad_Opcode },
6929 { Bad_Opcode },
6930 { Bad_Opcode },
6931 { Bad_Opcode },
6932 { Bad_Opcode },
6933 /* f8 */
6934 { Bad_Opcode },
6935 { Bad_Opcode },
6936 { Bad_Opcode },
6937 { Bad_Opcode },
6938 { Bad_Opcode },
6939 { Bad_Opcode },
6940 { Bad_Opcode },
6941 { Bad_Opcode },
6942 },
6943 };
6944
6945 #include "i386-dis-evex.h"
6946
6947 static const struct dis386 vex_len_table[][2] = {
6948 /* VEX_LEN_0F12_P_0 */
6949 {
6950 { MOD_TABLE (MOD_0F12_PREFIX_0) },
6951 },
6952
6953 /* VEX_LEN_0F12_P_2 */
6954 {
6955 { "%XEVmovlpYX", { XM, Vex, Mq }, 0 },
6956 },
6957
6958 /* VEX_LEN_0F13 */
6959 {
6960 { "%XEVmovlpYX", { Mq, XM }, PREFIX_OPCODE },
6961 },
6962
6963 /* VEX_LEN_0F16_P_0 */
6964 {
6965 { MOD_TABLE (MOD_0F16_PREFIX_0) },
6966 },
6967
6968 /* VEX_LEN_0F16_P_2 */
6969 {
6970 { "%XEVmovhpYX", { XM, Vex, Mq }, 0 },
6971 },
6972
6973 /* VEX_LEN_0F17 */
6974 {
6975 { "%XEVmovhpYX", { Mq, XM }, PREFIX_OPCODE },
6976 },
6977
6978 /* VEX_LEN_0F41 */
6979 {
6980 { Bad_Opcode },
6981 { VEX_W_TABLE (VEX_W_0F41_L_1) },
6982 },
6983
6984 /* VEX_LEN_0F42 */
6985 {
6986 { Bad_Opcode },
6987 { VEX_W_TABLE (VEX_W_0F42_L_1) },
6988 },
6989
6990 /* VEX_LEN_0F44 */
6991 {
6992 { VEX_W_TABLE (VEX_W_0F44_L_0) },
6993 },
6994
6995 /* VEX_LEN_0F45 */
6996 {
6997 { Bad_Opcode },
6998 { VEX_W_TABLE (VEX_W_0F45_L_1) },
6999 },
7000
7001 /* VEX_LEN_0F46 */
7002 {
7003 { Bad_Opcode },
7004 { VEX_W_TABLE (VEX_W_0F46_L_1) },
7005 },
7006
7007 /* VEX_LEN_0F47 */
7008 {
7009 { Bad_Opcode },
7010 { VEX_W_TABLE (VEX_W_0F47_L_1) },
7011 },
7012
7013 /* VEX_LEN_0F4A */
7014 {
7015 { Bad_Opcode },
7016 { VEX_W_TABLE (VEX_W_0F4A_L_1) },
7017 },
7018
7019 /* VEX_LEN_0F4B */
7020 {
7021 { Bad_Opcode },
7022 { VEX_W_TABLE (VEX_W_0F4B_L_1) },
7023 },
7024
7025 /* VEX_LEN_0F6E */
7026 {
7027 { "%XEvmovYK", { XMScalar, Edq }, PREFIX_DATA },
7028 },
7029
7030 /* VEX_LEN_0F77 */
7031 {
7032 { "vzeroupper", { XX }, 0 },
7033 { "vzeroall", { XX }, 0 },
7034 },
7035
7036 /* VEX_LEN_0F7E_P_1 */
7037 {
7038 { "%XEvmovqY", { XMScalar, EXq }, 0 },
7039 },
7040
7041 /* VEX_LEN_0F7E_P_2 */
7042 {
7043 { "%XEvmovK", { Edq, XMScalar }, 0 },
7044 },
7045
7046 /* VEX_LEN_0F90 */
7047 {
7048 { VEX_W_TABLE (VEX_W_0F90_L_0) },
7049 },
7050
7051 /* VEX_LEN_0F91 */
7052 {
7053 { VEX_W_TABLE (VEX_W_0F91_L_0) },
7054 },
7055
7056 /* VEX_LEN_0F92 */
7057 {
7058 { VEX_W_TABLE (VEX_W_0F92_L_0) },
7059 },
7060
7061 /* VEX_LEN_0F93 */
7062 {
7063 { VEX_W_TABLE (VEX_W_0F93_L_0) },
7064 },
7065
7066 /* VEX_LEN_0F98 */
7067 {
7068 { VEX_W_TABLE (VEX_W_0F98_L_0) },
7069 },
7070
7071 /* VEX_LEN_0F99 */
7072 {
7073 { VEX_W_TABLE (VEX_W_0F99_L_0) },
7074 },
7075
7076 /* VEX_LEN_0FAE_R_2 */
7077 {
7078 { "vldmxcsr", { Md }, 0 },
7079 },
7080
7081 /* VEX_LEN_0FAE_R_3 */
7082 {
7083 { "vstmxcsr", { Md }, 0 },
7084 },
7085
7086 /* VEX_LEN_0FC4 */
7087 {
7088 { "%XEvpinsrwY", { XM, Vex, Edw, Ib }, PREFIX_DATA },
7089 },
7090
7091 /* VEX_LEN_0FD6 */
7092 {
7093 { "%XEvmovqY", { EXqS, XMScalar }, PREFIX_DATA },
7094 },
7095
7096 /* VEX_LEN_0F3816 */
7097 {
7098 { Bad_Opcode },
7099 { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7100 },
7101
7102 /* VEX_LEN_0F3819 */
7103 {
7104 { Bad_Opcode },
7105 { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7106 },
7107
7108 /* VEX_LEN_0F381A */
7109 {
7110 { Bad_Opcode },
7111 { VEX_W_TABLE (VEX_W_0F381A_L_1) },
7112 },
7113
7114 /* VEX_LEN_0F3836 */
7115 {
7116 { Bad_Opcode },
7117 { VEX_W_TABLE (VEX_W_0F3836) },
7118 },
7119
7120 /* VEX_LEN_0F3841 */
7121 {
7122 { "vphminposuw", { XM, EXx }, PREFIX_DATA },
7123 },
7124
7125 /* VEX_LEN_0F3849_X86_64 */
7126 {
7127 { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
7128 },
7129
7130 /* VEX_LEN_0F384B_X86_64 */
7131 {
7132 { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
7133 },
7134
7135 /* VEX_LEN_0F385A */
7136 {
7137 { Bad_Opcode },
7138 { VEX_W_TABLE (VEX_W_0F385A_L_0) },
7139 },
7140
7141 /* VEX_LEN_0F385C_X86_64 */
7142 {
7143 { VEX_W_TABLE (VEX_W_0F385C_X86_64_L_0) },
7144 },
7145
7146 /* VEX_LEN_0F385E_X86_64 */
7147 {
7148 { VEX_W_TABLE (VEX_W_0F385E_X86_64_L_0) },
7149 },
7150
7151 /* VEX_LEN_0F386C_X86_64 */
7152 {
7153 { VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0) },
7154 },
7155
7156 /* VEX_LEN_0F38CB_P_3_W_0 */
7157 {
7158 { Bad_Opcode },
7159 { "vsha512rnds2", { XM, Vex, Rxmmq }, 0 },
7160 },
7161
7162 /* VEX_LEN_0F38CC_P_3_W_0 */
7163 {
7164 { Bad_Opcode },
7165 { "vsha512msg1", { XM, Rxmmq }, 0 },
7166 },
7167
7168 /* VEX_LEN_0F38CD_P_3_W_0 */
7169 {
7170 { Bad_Opcode },
7171 { "vsha512msg2", { XM, Rymm }, 0 },
7172 },
7173
7174 /* VEX_LEN_0F38DA_W_0_P_0 */
7175 {
7176 { "vsm3msg1", { XM, Vex, EXxmm }, 0 },
7177 },
7178
7179 /* VEX_LEN_0F38DA_W_0_P_2 */
7180 {
7181 { "vsm3msg2", { XM, Vex, EXxmm }, 0 },
7182 },
7183
7184 /* VEX_LEN_0F38DB */
7185 {
7186 { "vaesimc", { XM, EXx }, PREFIX_DATA },
7187 },
7188
7189 /* VEX_LEN_0F38F2 */
7190 {
7191 { PREFIX_TABLE (PREFIX_VEX_0F38F2_L_0) },
7192 },
7193
7194 /* VEX_LEN_0F38F3 */
7195 {
7196 { PREFIX_TABLE (PREFIX_VEX_0F38F3_L_0) },
7197 },
7198
7199 /* VEX_LEN_0F38F5 */
7200 {
7201 { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7202 },
7203
7204 /* VEX_LEN_0F38F6 */
7205 {
7206 { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7207 },
7208
7209 /* VEX_LEN_0F38F7 */
7210 {
7211 { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7212 },
7213
7214 /* VEX_LEN_0F3A00 */
7215 {
7216 { Bad_Opcode },
7217 { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7218 },
7219
7220 /* VEX_LEN_0F3A01 */
7221 {
7222 { Bad_Opcode },
7223 { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7224 },
7225
7226 /* VEX_LEN_0F3A06 */
7227 {
7228 { Bad_Opcode },
7229 { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7230 },
7231
7232 /* VEX_LEN_0F3A14 */
7233 {
7234 { "%XEvpextrb", { Edb, XM, Ib }, PREFIX_DATA },
7235 },
7236
7237 /* VEX_LEN_0F3A15 */
7238 {
7239 { "%XEvpextrw", { Edw, XM, Ib }, PREFIX_DATA },
7240 },
7241
7242 /* VEX_LEN_0F3A16 */
7243 {
7244 { "%XEvpextrK", { Edq, XM, Ib }, PREFIX_DATA },
7245 },
7246
7247 /* VEX_LEN_0F3A17 */
7248 {
7249 { "%XEvextractps", { Ed, XM, Ib }, PREFIX_DATA },
7250 },
7251
7252 /* VEX_LEN_0F3A18 */
7253 {
7254 { Bad_Opcode },
7255 { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7256 },
7257
7258 /* VEX_LEN_0F3A19 */
7259 {
7260 { Bad_Opcode },
7261 { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7262 },
7263
7264 /* VEX_LEN_0F3A20 */
7265 {
7266 { "%XEvpinsrbY", { XM, Vex, Edb, Ib }, PREFIX_DATA },
7267 },
7268
7269 /* VEX_LEN_0F3A21 */
7270 {
7271 { "%XEvinsertpsY", { XM, Vex, EXd, Ib }, PREFIX_DATA },
7272 },
7273
7274 /* VEX_LEN_0F3A22 */
7275 {
7276 { "%XEvpinsrYK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
7277 },
7278
7279 /* VEX_LEN_0F3A30 */
7280 {
7281 { "kshiftr%BW", { MaskG, MaskR, Ib }, PREFIX_DATA },
7282 },
7283
7284 /* VEX_LEN_0F3A31 */
7285 {
7286 { "kshiftr%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA },
7287 },
7288
7289 /* VEX_LEN_0F3A32 */
7290 {
7291 { "kshiftl%BW", { MaskG, MaskR, Ib }, PREFIX_DATA },
7292 },
7293
7294 /* VEX_LEN_0F3A33 */
7295 {
7296 { "kshiftl%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA },
7297 },
7298
7299 /* VEX_LEN_0F3A38 */
7300 {
7301 { Bad_Opcode },
7302 { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7303 },
7304
7305 /* VEX_LEN_0F3A39 */
7306 {
7307 { Bad_Opcode },
7308 { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7309 },
7310
7311 /* VEX_LEN_0F3A41 */
7312 {
7313 { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7314 },
7315
7316 /* VEX_LEN_0F3A46 */
7317 {
7318 { Bad_Opcode },
7319 { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7320 },
7321
7322 /* VEX_LEN_0F3A60 */
7323 {
7324 { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7325 },
7326
7327 /* VEX_LEN_0F3A61 */
7328 {
7329 { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7330 },
7331
7332 /* VEX_LEN_0F3A62 */
7333 {
7334 { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
7335 },
7336
7337 /* VEX_LEN_0F3A63 */
7338 {
7339 { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
7340 },
7341
7342 /* VEX_LEN_0F3ADE_W_0 */
7343 {
7344 { "vsm3rnds2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7345 },
7346
7347 /* VEX_LEN_0F3ADF */
7348 {
7349 { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7350 },
7351
7352 /* VEX_LEN_0F3AF0 */
7353 {
7354 { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7355 },
7356
7357 /* VEX_LEN_MAP7_F8 */
7358 {
7359 { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) },
7360 },
7361
7362 /* VEX_LEN_XOP_08_85 */
7363 {
7364 { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) },
7365 },
7366
7367 /* VEX_LEN_XOP_08_86 */
7368 {
7369 { VEX_W_TABLE (VEX_W_XOP_08_86_L_0) },
7370 },
7371
7372 /* VEX_LEN_XOP_08_87 */
7373 {
7374 { VEX_W_TABLE (VEX_W_XOP_08_87_L_0) },
7375 },
7376
7377 /* VEX_LEN_XOP_08_8E */
7378 {
7379 { VEX_W_TABLE (VEX_W_XOP_08_8E_L_0) },
7380 },
7381
7382 /* VEX_LEN_XOP_08_8F */
7383 {
7384 { VEX_W_TABLE (VEX_W_XOP_08_8F_L_0) },
7385 },
7386
7387 /* VEX_LEN_XOP_08_95 */
7388 {
7389 { VEX_W_TABLE (VEX_W_XOP_08_95_L_0) },
7390 },
7391
7392 /* VEX_LEN_XOP_08_96 */
7393 {
7394 { VEX_W_TABLE (VEX_W_XOP_08_96_L_0) },
7395 },
7396
7397 /* VEX_LEN_XOP_08_97 */
7398 {
7399 { VEX_W_TABLE (VEX_W_XOP_08_97_L_0) },
7400 },
7401
7402 /* VEX_LEN_XOP_08_9E */
7403 {
7404 { VEX_W_TABLE (VEX_W_XOP_08_9E_L_0) },
7405 },
7406
7407 /* VEX_LEN_XOP_08_9F */
7408 {
7409 { VEX_W_TABLE (VEX_W_XOP_08_9F_L_0) },
7410 },
7411
7412 /* VEX_LEN_XOP_08_A3 */
7413 {
7414 { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
7415 },
7416
7417 /* VEX_LEN_XOP_08_A6 */
7418 {
7419 { VEX_W_TABLE (VEX_W_XOP_08_A6_L_0) },
7420 },
7421
7422 /* VEX_LEN_XOP_08_B6 */
7423 {
7424 { VEX_W_TABLE (VEX_W_XOP_08_B6_L_0) },
7425 },
7426
7427 /* VEX_LEN_XOP_08_C0 */
7428 {
7429 { VEX_W_TABLE (VEX_W_XOP_08_C0_L_0) },
7430 },
7431
7432 /* VEX_LEN_XOP_08_C1 */
7433 {
7434 { VEX_W_TABLE (VEX_W_XOP_08_C1_L_0) },
7435 },
7436
7437 /* VEX_LEN_XOP_08_C2 */
7438 {
7439 { VEX_W_TABLE (VEX_W_XOP_08_C2_L_0) },
7440 },
7441
7442 /* VEX_LEN_XOP_08_C3 */
7443 {
7444 { VEX_W_TABLE (VEX_W_XOP_08_C3_L_0) },
7445 },
7446
7447 /* VEX_LEN_XOP_08_CC */
7448 {
7449 { VEX_W_TABLE (VEX_W_XOP_08_CC_L_0) },
7450 },
7451
7452 /* VEX_LEN_XOP_08_CD */
7453 {
7454 { VEX_W_TABLE (VEX_W_XOP_08_CD_L_0) },
7455 },
7456
7457 /* VEX_LEN_XOP_08_CE */
7458 {
7459 { VEX_W_TABLE (VEX_W_XOP_08_CE_L_0) },
7460 },
7461
7462 /* VEX_LEN_XOP_08_CF */
7463 {
7464 { VEX_W_TABLE (VEX_W_XOP_08_CF_L_0) },
7465 },
7466
7467 /* VEX_LEN_XOP_08_EC */
7468 {
7469 { VEX_W_TABLE (VEX_W_XOP_08_EC_L_0) },
7470 },
7471
7472 /* VEX_LEN_XOP_08_ED */
7473 {
7474 { VEX_W_TABLE (VEX_W_XOP_08_ED_L_0) },
7475 },
7476
7477 /* VEX_LEN_XOP_08_EE */
7478 {
7479 { VEX_W_TABLE (VEX_W_XOP_08_EE_L_0) },
7480 },
7481
7482 /* VEX_LEN_XOP_08_EF */
7483 {
7484 { VEX_W_TABLE (VEX_W_XOP_08_EF_L_0) },
7485 },
7486
7487 /* VEX_LEN_XOP_09_01 */
7488 {
7489 { REG_TABLE (REG_XOP_09_01_L_0) },
7490 },
7491
7492 /* VEX_LEN_XOP_09_02 */
7493 {
7494 { REG_TABLE (REG_XOP_09_02_L_0) },
7495 },
7496
7497 /* VEX_LEN_XOP_09_12 */
7498 {
7499 { REG_TABLE (REG_XOP_09_12_L_0) },
7500 },
7501
7502 /* VEX_LEN_XOP_09_82_W_0 */
7503 {
7504 { "vfrczss", { XM, EXd }, 0 },
7505 },
7506
7507 /* VEX_LEN_XOP_09_83_W_0 */
7508 {
7509 { "vfrczsd", { XM, EXq }, 0 },
7510 },
7511
7512 /* VEX_LEN_XOP_09_90 */
7513 {
7514 { "vprotb", { XM, EXx, VexW }, 0 },
7515 },
7516
7517 /* VEX_LEN_XOP_09_91 */
7518 {
7519 { "vprotw", { XM, EXx, VexW }, 0 },
7520 },
7521
7522 /* VEX_LEN_XOP_09_92 */
7523 {
7524 { "vprotd", { XM, EXx, VexW }, 0 },
7525 },
7526
7527 /* VEX_LEN_XOP_09_93 */
7528 {
7529 { "vprotq", { XM, EXx, VexW }, 0 },
7530 },
7531
7532 /* VEX_LEN_XOP_09_94 */
7533 {
7534 { "vpshlb", { XM, EXx, VexW }, 0 },
7535 },
7536
7537 /* VEX_LEN_XOP_09_95 */
7538 {
7539 { "vpshlw", { XM, EXx, VexW }, 0 },
7540 },
7541
7542 /* VEX_LEN_XOP_09_96 */
7543 {
7544 { "vpshld", { XM, EXx, VexW }, 0 },
7545 },
7546
7547 /* VEX_LEN_XOP_09_97 */
7548 {
7549 { "vpshlq", { XM, EXx, VexW }, 0 },
7550 },
7551
7552 /* VEX_LEN_XOP_09_98 */
7553 {
7554 { "vpshab", { XM, EXx, VexW }, 0 },
7555 },
7556
7557 /* VEX_LEN_XOP_09_99 */
7558 {
7559 { "vpshaw", { XM, EXx, VexW }, 0 },
7560 },
7561
7562 /* VEX_LEN_XOP_09_9A */
7563 {
7564 { "vpshad", { XM, EXx, VexW }, 0 },
7565 },
7566
7567 /* VEX_LEN_XOP_09_9B */
7568 {
7569 { "vpshaq", { XM, EXx, VexW }, 0 },
7570 },
7571
7572 /* VEX_LEN_XOP_09_C1 */
7573 {
7574 { VEX_W_TABLE (VEX_W_XOP_09_C1_L_0) },
7575 },
7576
7577 /* VEX_LEN_XOP_09_C2 */
7578 {
7579 { VEX_W_TABLE (VEX_W_XOP_09_C2_L_0) },
7580 },
7581
7582 /* VEX_LEN_XOP_09_C3 */
7583 {
7584 { VEX_W_TABLE (VEX_W_XOP_09_C3_L_0) },
7585 },
7586
7587 /* VEX_LEN_XOP_09_C6 */
7588 {
7589 { VEX_W_TABLE (VEX_W_XOP_09_C6_L_0) },
7590 },
7591
7592 /* VEX_LEN_XOP_09_C7 */
7593 {
7594 { VEX_W_TABLE (VEX_W_XOP_09_C7_L_0) },
7595 },
7596
7597 /* VEX_LEN_XOP_09_CB */
7598 {
7599 { VEX_W_TABLE (VEX_W_XOP_09_CB_L_0) },
7600 },
7601
7602 /* VEX_LEN_XOP_09_D1 */
7603 {
7604 { VEX_W_TABLE (VEX_W_XOP_09_D1_L_0) },
7605 },
7606
7607 /* VEX_LEN_XOP_09_D2 */
7608 {
7609 { VEX_W_TABLE (VEX_W_XOP_09_D2_L_0) },
7610 },
7611
7612 /* VEX_LEN_XOP_09_D3 */
7613 {
7614 { VEX_W_TABLE (VEX_W_XOP_09_D3_L_0) },
7615 },
7616
7617 /* VEX_LEN_XOP_09_D6 */
7618 {
7619 { VEX_W_TABLE (VEX_W_XOP_09_D6_L_0) },
7620 },
7621
7622 /* VEX_LEN_XOP_09_D7 */
7623 {
7624 { VEX_W_TABLE (VEX_W_XOP_09_D7_L_0) },
7625 },
7626
7627 /* VEX_LEN_XOP_09_DB */
7628 {
7629 { VEX_W_TABLE (VEX_W_XOP_09_DB_L_0) },
7630 },
7631
7632 /* VEX_LEN_XOP_09_E1 */
7633 {
7634 { VEX_W_TABLE (VEX_W_XOP_09_E1_L_0) },
7635 },
7636
7637 /* VEX_LEN_XOP_09_E2 */
7638 {
7639 { VEX_W_TABLE (VEX_W_XOP_09_E2_L_0) },
7640 },
7641
7642 /* VEX_LEN_XOP_09_E3 */
7643 {
7644 { VEX_W_TABLE (VEX_W_XOP_09_E3_L_0) },
7645 },
7646
7647 /* VEX_LEN_XOP_0A_12 */
7648 {
7649 { REG_TABLE (REG_XOP_0A_12_L_0) },
7650 },
7651 };
7652
7653 #include "i386-dis-evex-len.h"
7654
7655 static const struct dis386 vex_w_table[][2] = {
7656 {
7657 /* VEX_W_0F41_L_1_M_1 */
7658 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_0) },
7659 { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_1) },
7660 },
7661 {
7662 /* VEX_W_0F42_L_1_M_1 */
7663 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_0) },
7664 { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_1) },
7665 },
7666 {
7667 /* VEX_W_0F44_L_0_M_1 */
7668 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_0) },
7669 { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_1) },
7670 },
7671 {
7672 /* VEX_W_0F45_L_1_M_1 */
7673 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_0) },
7674 { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_1) },
7675 },
7676 {
7677 /* VEX_W_0F46_L_1_M_1 */
7678 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_0) },
7679 { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_1) },
7680 },
7681 {
7682 /* VEX_W_0F47_L_1_M_1 */
7683 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_0) },
7684 { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_1) },
7685 },
7686 {
7687 /* VEX_W_0F4A_L_1_M_1 */
7688 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_0) },
7689 { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_1) },
7690 },
7691 {
7692 /* VEX_W_0F4B_L_1_M_1 */
7693 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_0) },
7694 { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_1) },
7695 },
7696 {
7697 /* VEX_W_0F90_L_0 */
7698 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7699 { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7700 },
7701 {
7702 /* VEX_W_0F91_L_0_M_0 */
7703 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_0) },
7704 { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_1) },
7705 },
7706 {
7707 /* VEX_W_0F92_L_0_M_1 */
7708 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_0) },
7709 { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_1) },
7710 },
7711 {
7712 /* VEX_W_0F93_L_0_M_1 */
7713 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_0) },
7714 { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_1) },
7715 },
7716 {
7717 /* VEX_W_0F98_L_0_M_1 */
7718 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_0) },
7719 { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_1) },
7720 },
7721 {
7722 /* VEX_W_0F99_L_0_M_1 */
7723 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_0) },
7724 { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_1) },
7725 },
7726 {
7727 /* VEX_W_0F380C */
7728 { "%XEvpermilps", { XM, Vex, EXx }, PREFIX_DATA },
7729 },
7730 {
7731 /* VEX_W_0F380D */
7732 { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
7733 },
7734 {
7735 /* VEX_W_0F380E */
7736 { "vtestps", { XM, EXx }, PREFIX_DATA },
7737 },
7738 {
7739 /* VEX_W_0F380F */
7740 { "vtestpd", { XM, EXx }, PREFIX_DATA },
7741 },
7742 {
7743 /* VEX_W_0F3813 */
7744 { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7745 },
7746 {
7747 /* VEX_W_0F3816_L_1 */
7748 { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
7749 },
7750 {
7751 /* VEX_W_0F3818 */
7752 { "%XEvbroadcastss", { XM, EXd }, PREFIX_DATA },
7753 },
7754 {
7755 /* VEX_W_0F3819_L_1 */
7756 { "vbroadcastsd", { XM, EXq }, PREFIX_DATA },
7757 },
7758 {
7759 /* VEX_W_0F381A_L_1 */
7760 { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7761 },
7762 {
7763 /* VEX_W_0F382C */
7764 { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
7765 },
7766 {
7767 /* VEX_W_0F382D */
7768 { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
7769 },
7770 {
7771 /* VEX_W_0F382E */
7772 { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
7773 },
7774 {
7775 /* VEX_W_0F382F */
7776 { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
7777 },
7778 {
7779 /* VEX_W_0F3836 */
7780 { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
7781 },
7782 {
7783 /* VEX_W_0F3846 */
7784 { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
7785 },
7786 {
7787 /* VEX_W_0F3849_X86_64_L_0 */
7788 { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) },
7789 },
7790 {
7791 /* VEX_W_0F384B_X86_64_L_0 */
7792 { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0) },
7793 },
7794 {
7795 /* VEX_W_0F3850 */
7796 { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
7797 },
7798 {
7799 /* VEX_W_0F3851 */
7800 { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
7801 },
7802 {
7803 /* VEX_W_0F3852 */
7804 { "%XVvpdpwssd", { XM, Vex, EXx }, PREFIX_DATA },
7805 },
7806 {
7807 /* VEX_W_0F3853 */
7808 { "%XVvpdpwssds", { XM, Vex, EXx }, PREFIX_DATA },
7809 },
7810 {
7811 /* VEX_W_0F3858 */
7812 { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
7813 },
7814 {
7815 /* VEX_W_0F3859 */
7816 { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7817 },
7818 {
7819 /* VEX_W_0F385A_L_0 */
7820 { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7821 },
7822 {
7823 /* VEX_W_0F385C_X86_64_L_0 */
7824 { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_L_0_W_0) },
7825 },
7826 {
7827 /* VEX_W_0F385E_X86_64_L_0 */
7828 { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_L_0_W_0) },
7829 },
7830 {
7831 /* VEX_W_0F386C_X86_64_L_0 */
7832 { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_L_0_W_0) },
7833 },
7834 {
7835 /* VEX_W_0F3872_P_1 */
7836 { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
7837 },
7838 {
7839 /* VEX_W_0F3878 */
7840 { "%XEvpbroadcastb", { XM, EXb }, PREFIX_DATA },
7841 },
7842 {
7843 /* VEX_W_0F3879 */
7844 { "%XEvpbroadcastw", { XM, EXw }, PREFIX_DATA },
7845 },
7846 {
7847 /* VEX_W_0F38B0 */
7848 { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) },
7849 },
7850 {
7851 /* VEX_W_0F38B1 */
7852 { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) },
7853 },
7854 {
7855 /* VEX_W_0F38B4 */
7856 { Bad_Opcode },
7857 { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
7858 },
7859 {
7860 /* VEX_W_0F38B5 */
7861 { Bad_Opcode },
7862 { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
7863 },
7864 {
7865 /* VEX_W_0F38CB_P_3 */
7866 { VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0) },
7867 },
7868 {
7869 /* VEX_W_0F38CC_P_3 */
7870 { VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0) },
7871 },
7872 {
7873 /* VEX_W_0F38CD_P_3 */
7874 { VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0) },
7875 },
7876 {
7877 /* VEX_W_0F38CF */
7878 { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7879 },
7880 {
7881 /* VEX_W_0F38D2 */
7882 { PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0) },
7883 },
7884 {
7885 /* VEX_W_0F38D3 */
7886 { PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) },
7887 },
7888 {
7889 /* VEX_W_0F38DA */
7890 { PREFIX_TABLE (PREFIX_VEX_0F38DA_W_0) },
7891 },
7892 {
7893 /* VEX_W_0F3A00_L_1 */
7894 { Bad_Opcode },
7895 { "%XEvpermq", { XM, EXx, Ib }, PREFIX_DATA },
7896 },
7897 {
7898 /* VEX_W_0F3A01_L_1 */
7899 { Bad_Opcode },
7900 { "%XEvpermpd", { XM, EXx, Ib }, PREFIX_DATA },
7901 },
7902 {
7903 /* VEX_W_0F3A02 */
7904 { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7905 },
7906 {
7907 /* VEX_W_0F3A04 */
7908 { "%XEvpermilps", { XM, EXx, Ib }, PREFIX_DATA },
7909 },
7910 {
7911 /* VEX_W_0F3A05 */
7912 { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
7913 },
7914 {
7915 /* VEX_W_0F3A06_L_1 */
7916 { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7917 },
7918 {
7919 /* VEX_W_0F3A18_L_1 */
7920 { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7921 },
7922 {
7923 /* VEX_W_0F3A19_L_1 */
7924 { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
7925 },
7926 {
7927 /* VEX_W_0F3A1D */
7928 { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7929 },
7930 {
7931 /* VEX_W_0F3A38_L_1 */
7932 { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7933 },
7934 {
7935 /* VEX_W_0F3A39_L_1 */
7936 { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
7937 },
7938 {
7939 /* VEX_W_0F3A46_L_1 */
7940 { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7941 },
7942 {
7943 /* VEX_W_0F3A4A */
7944 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7945 },
7946 {
7947 /* VEX_W_0F3A4B */
7948 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7949 },
7950 {
7951 /* VEX_W_0F3A4C */
7952 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7953 },
7954 {
7955 /* VEX_W_0F3ACE */
7956 { Bad_Opcode },
7957 { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7958 },
7959 {
7960 /* VEX_W_0F3ACF */
7961 { Bad_Opcode },
7962 { "%XEvgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7963 },
7964 {
7965 /* VEX_W_0F3ADE */
7966 { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) },
7967 },
7968 {
7969 /* VEX_W_MAP7_F8_L_0 */
7970 { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) },
7971 },
7972 /* VEX_W_XOP_08_85_L_0 */
7973 {
7974 { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
7975 },
7976 /* VEX_W_XOP_08_86_L_0 */
7977 {
7978 { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7979 },
7980 /* VEX_W_XOP_08_87_L_0 */
7981 {
7982 { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
7983 },
7984 /* VEX_W_XOP_08_8E_L_0 */
7985 {
7986 { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
7987 },
7988 /* VEX_W_XOP_08_8F_L_0 */
7989 {
7990 { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
7991 },
7992 /* VEX_W_XOP_08_95_L_0 */
7993 {
7994 { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
7995 },
7996 /* VEX_W_XOP_08_96_L_0 */
7997 {
7998 { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
7999 },
8000 /* VEX_W_XOP_08_97_L_0 */
8001 {
8002 { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
8003 },
8004 /* VEX_W_XOP_08_9E_L_0 */
8005 {
8006 { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
8007 },
8008 /* VEX_W_XOP_08_9F_L_0 */
8009 {
8010 { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
8011 },
8012 /* VEX_W_XOP_08_A6_L_0 */
8013 {
8014 { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
8015 },
8016 /* VEX_W_XOP_08_B6_L_0 */
8017 {
8018 { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
8019 },
8020 /* VEX_W_XOP_08_C0_L_0 */
8021 {
8022 { "vprotb", { XM, EXx, Ib }, 0 },
8023 },
8024 /* VEX_W_XOP_08_C1_L_0 */
8025 {
8026 { "vprotw", { XM, EXx, Ib }, 0 },
8027 },
8028 /* VEX_W_XOP_08_C2_L_0 */
8029 {
8030 { "vprotd", { XM, EXx, Ib }, 0 },
8031 },
8032 /* VEX_W_XOP_08_C3_L_0 */
8033 {
8034 { "vprotq", { XM, EXx, Ib }, 0 },
8035 },
8036 /* VEX_W_XOP_08_CC_L_0 */
8037 {
8038 { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
8039 },
8040 /* VEX_W_XOP_08_CD_L_0 */
8041 {
8042 { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
8043 },
8044 /* VEX_W_XOP_08_CE_L_0 */
8045 {
8046 { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
8047 },
8048 /* VEX_W_XOP_08_CF_L_0 */
8049 {
8050 { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
8051 },
8052 /* VEX_W_XOP_08_EC_L_0 */
8053 {
8054 { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
8055 },
8056 /* VEX_W_XOP_08_ED_L_0 */
8057 {
8058 { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
8059 },
8060 /* VEX_W_XOP_08_EE_L_0 */
8061 {
8062 { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
8063 },
8064 /* VEX_W_XOP_08_EF_L_0 */
8065 {
8066 { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
8067 },
8068 /* VEX_W_XOP_09_80 */
8069 {
8070 { "vfrczps", { XM, EXx }, 0 },
8071 },
8072 /* VEX_W_XOP_09_81 */
8073 {
8074 { "vfrczpd", { XM, EXx }, 0 },
8075 },
8076 /* VEX_W_XOP_09_82 */
8077 {
8078 { VEX_LEN_TABLE (VEX_LEN_XOP_09_82_W_0) },
8079 },
8080 /* VEX_W_XOP_09_83 */
8081 {
8082 { VEX_LEN_TABLE (VEX_LEN_XOP_09_83_W_0) },
8083 },
8084 /* VEX_W_XOP_09_C1_L_0 */
8085 {
8086 { "vphaddbw", { XM, EXxmm }, 0 },
8087 },
8088 /* VEX_W_XOP_09_C2_L_0 */
8089 {
8090 { "vphaddbd", { XM, EXxmm }, 0 },
8091 },
8092 /* VEX_W_XOP_09_C3_L_0 */
8093 {
8094 { "vphaddbq", { XM, EXxmm }, 0 },
8095 },
8096 /* VEX_W_XOP_09_C6_L_0 */
8097 {
8098 { "vphaddwd", { XM, EXxmm }, 0 },
8099 },
8100 /* VEX_W_XOP_09_C7_L_0 */
8101 {
8102 { "vphaddwq", { XM, EXxmm }, 0 },
8103 },
8104 /* VEX_W_XOP_09_CB_L_0 */
8105 {
8106 { "vphadddq", { XM, EXxmm }, 0 },
8107 },
8108 /* VEX_W_XOP_09_D1_L_0 */
8109 {
8110 { "vphaddubw", { XM, EXxmm }, 0 },
8111 },
8112 /* VEX_W_XOP_09_D2_L_0 */
8113 {
8114 { "vphaddubd", { XM, EXxmm }, 0 },
8115 },
8116 /* VEX_W_XOP_09_D3_L_0 */
8117 {
8118 { "vphaddubq", { XM, EXxmm }, 0 },
8119 },
8120 /* VEX_W_XOP_09_D6_L_0 */
8121 {
8122 { "vphadduwd", { XM, EXxmm }, 0 },
8123 },
8124 /* VEX_W_XOP_09_D7_L_0 */
8125 {
8126 { "vphadduwq", { XM, EXxmm }, 0 },
8127 },
8128 /* VEX_W_XOP_09_DB_L_0 */
8129 {
8130 { "vphaddudq", { XM, EXxmm }, 0 },
8131 },
8132 /* VEX_W_XOP_09_E1_L_0 */
8133 {
8134 { "vphsubbw", { XM, EXxmm }, 0 },
8135 },
8136 /* VEX_W_XOP_09_E2_L_0 */
8137 {
8138 { "vphsubwd", { XM, EXxmm }, 0 },
8139 },
8140 /* VEX_W_XOP_09_E3_L_0 */
8141 {
8142 { "vphsubdq", { XM, EXxmm }, 0 },
8143 },
8144
8145 #include "i386-dis-evex-w.h"
8146 };
8147
8148 static const struct dis386 mod_table[][2] = {
8149 {
8150 /* MOD_62_32BIT */
8151 { "bound{S|}", { Gv, Ma }, 0 },
8152 { EVEX_TABLE () },
8153 },
8154 {
8155 /* MOD_C4_32BIT */
8156 { "lesS", { Gv, Mp }, 0 },
8157 { VEX_C4_TABLE () },
8158 },
8159 {
8160 /* MOD_C5_32BIT */
8161 { "ldsS", { Gv, Mp }, 0 },
8162 { VEX_C5_TABLE () },
8163 },
8164 {
8165 /* MOD_0F01_REG_0 */
8166 { X86_64_TABLE (X86_64_0F01_REG_0) },
8167 { RM_TABLE (RM_0F01_REG_0) },
8168 },
8169 {
8170 /* MOD_0F01_REG_1 */
8171 { X86_64_TABLE (X86_64_0F01_REG_1) },
8172 { RM_TABLE (RM_0F01_REG_1) },
8173 },
8174 {
8175 /* MOD_0F01_REG_2 */
8176 { X86_64_TABLE (X86_64_0F01_REG_2) },
8177 { RM_TABLE (RM_0F01_REG_2) },
8178 },
8179 {
8180 /* MOD_0F01_REG_3 */
8181 { X86_64_TABLE (X86_64_0F01_REG_3) },
8182 { RM_TABLE (RM_0F01_REG_3) },
8183 },
8184 {
8185 /* MOD_0F01_REG_5 */
8186 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8187 { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8188 },
8189 {
8190 /* MOD_0F01_REG_7 */
8191 { "invlpg", { Mb }, 0 },
8192 { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8193 },
8194 {
8195 /* MOD_0F12_PREFIX_0 */
8196 { "%XEVmovlpYX", { XM, Vex, EXq }, 0 },
8197 { "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 },
8198 },
8199 {
8200 /* MOD_0F16_PREFIX_0 */
8201 { "%XEVmovhpYX", { XM, Vex, EXq }, 0 },
8202 { "%XEVmovlhpY%XS", { XM, Vex, EXq }, 0 },
8203 },
8204 {
8205 /* MOD_0F18_REG_0 */
8206 { "prefetchnta", { Mb }, 0 },
8207 { "nopQ", { Ev }, 0 },
8208 },
8209 {
8210 /* MOD_0F18_REG_1 */
8211 { "prefetcht0", { Mb }, 0 },
8212 { "nopQ", { Ev }, 0 },
8213 },
8214 {
8215 /* MOD_0F18_REG_2 */
8216 { "prefetcht1", { Mb }, 0 },
8217 { "nopQ", { Ev }, 0 },
8218 },
8219 {
8220 /* MOD_0F18_REG_3 */
8221 { "prefetcht2", { Mb }, 0 },
8222 { "nopQ", { Ev }, 0 },
8223 },
8224 {
8225 /* MOD_0F18_REG_6 */
8226 { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
8227 { "nopQ", { Ev }, 0 },
8228 },
8229 {
8230 /* MOD_0F18_REG_7 */
8231 { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
8232 { "nopQ", { Ev }, 0 },
8233 },
8234 {
8235 /* MOD_0F1A_PREFIX_0 */
8236 { "bndldx", { Gbnd, Mv_bnd }, 0 },
8237 { "nopQ", { Ev }, 0 },
8238 },
8239 {
8240 /* MOD_0F1B_PREFIX_0 */
8241 { "bndstx", { Mv_bnd, Gbnd }, 0 },
8242 { "nopQ", { Ev }, 0 },
8243 },
8244 {
8245 /* MOD_0F1B_PREFIX_1 */
8246 { "bndmk", { Gbnd, Mv_bnd }, 0 },
8247 { "nopQ", { Ev }, PREFIX_IGNORED },
8248 },
8249 {
8250 /* MOD_0F1C_PREFIX_0 */
8251 { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8252 { "nopQ", { Ev }, 0 },
8253 },
8254 {
8255 /* MOD_0F1E_PREFIX_1 */
8256 { "nopQ", { Ev }, PREFIX_IGNORED },
8257 { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8258 },
8259 {
8260 /* MOD_0FAE_REG_0 */
8261 { "fxsave", { FXSAVE }, 0 },
8262 { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8263 },
8264 {
8265 /* MOD_0FAE_REG_1 */
8266 { "fxrstor", { FXSAVE }, 0 },
8267 { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8268 },
8269 {
8270 /* MOD_0FAE_REG_2 */
8271 { "ldmxcsr", { Md }, 0 },
8272 { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8273 },
8274 {
8275 /* MOD_0FAE_REG_3 */
8276 { "stmxcsr", { Md }, 0 },
8277 { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8278 },
8279 {
8280 /* MOD_0FAE_REG_4 */
8281 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8282 { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8283 },
8284 {
8285 /* MOD_0FAE_REG_5 */
8286 { "xrstor", { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
8287 { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8288 },
8289 {
8290 /* MOD_0FAE_REG_6 */
8291 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8292 { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8293 },
8294 {
8295 /* MOD_0FAE_REG_7 */
8296 { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8297 { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8298 },
8299 {
8300 /* MOD_0FC7_REG_6 */
8301 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8302 { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8303 },
8304 {
8305 /* MOD_0FC7_REG_7 */
8306 { "vmptrst", { Mq }, 0 },
8307 { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8308 },
8309 {
8310 /* MOD_0F38DC_PREFIX_1 */
8311 { "aesenc128kl", { XM, M }, 0 },
8312 { "loadiwkey", { XM, EXx }, 0 },
8313 },
8314 /* MOD_0F38F8 */
8315 {
8316 { PREFIX_TABLE (PREFIX_0F38F8_M_0) },
8317 { X86_64_TABLE (X86_64_0F38F8_M_1) },
8318 },
8319 {
8320 /* MOD_VEX_0F3849_X86_64_L_0_W_0 */
8321 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
8322 { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
8323 },
8324
8325 #include "i386-dis-evex-mod.h"
8326 };
8327
8328 static const struct dis386 rm_table[][8] = {
8329 {
8330 /* RM_C6_REG_7 */
8331 { "xabort", { Skip_MODRM, Ib }, 0 },
8332 },
8333 {
8334 /* RM_C7_REG_7 */
8335 { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
8336 },
8337 {
8338 /* RM_0F01_REG_0 */
8339 { "enclv", { Skip_MODRM }, 0 },
8340 { "vmcall", { Skip_MODRM }, 0 },
8341 { "vmlaunch", { Skip_MODRM }, 0 },
8342 { "vmresume", { Skip_MODRM }, 0 },
8343 { "vmxoff", { Skip_MODRM }, 0 },
8344 { "pconfig", { Skip_MODRM }, 0 },
8345 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
8346 { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_7) },
8347 },
8348 {
8349 /* RM_0F01_REG_1 */
8350 { "monitor", { { OP_Monitor, 0 } }, 0 },
8351 { "mwait", { { OP_Mwait, 0 } }, 0 },
8352 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) },
8353 { "stac", { Skip_MODRM }, 0 },
8354 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8355 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8356 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8357 { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8358 },
8359 {
8360 /* RM_0F01_REG_2 */
8361 { "xgetbv", { Skip_MODRM }, 0 },
8362 { "xsetbv", { Skip_MODRM }, 0 },
8363 { Bad_Opcode },
8364 { Bad_Opcode },
8365 { "vmfunc", { Skip_MODRM }, 0 },
8366 { "xend", { Skip_MODRM }, 0 },
8367 { "xtest", { Skip_MODRM }, 0 },
8368 { "enclu", { Skip_MODRM }, 0 },
8369 },
8370 {
8371 /* RM_0F01_REG_3 */
8372 { "vmrun", { Skip_MODRM }, 0 },
8373 { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8374 { "vmload", { Skip_MODRM }, 0 },
8375 { "vmsave", { Skip_MODRM }, 0 },
8376 { "stgi", { Skip_MODRM }, 0 },
8377 { "clgi", { Skip_MODRM }, 0 },
8378 { "skinit", { Skip_MODRM }, 0 },
8379 { "invlpga", { Skip_MODRM }, 0 },
8380 },
8381 {
8382 /* RM_0F01_REG_5_MOD_3 */
8383 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8384 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8385 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8386 { Bad_Opcode },
8387 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8388 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8389 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8390 { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8391 },
8392 {
8393 /* RM_0F01_REG_7_MOD_3 */
8394 { "swapgs", { Skip_MODRM }, 0 },
8395 { "rdtscp", { Skip_MODRM }, 0 },
8396 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8397 { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8398 { "clzero", { Skip_MODRM }, 0 },
8399 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) },
8400 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8401 { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8402 },
8403 {
8404 /* RM_0F1E_P_1_MOD_3_REG_7 */
8405 { "nopQ", { Ev }, PREFIX_IGNORED },
8406 { "nopQ", { Ev }, PREFIX_IGNORED },
8407 { "endbr64", { Skip_MODRM }, 0 },
8408 { "endbr32", { Skip_MODRM }, 0 },
8409 { "nopQ", { Ev }, PREFIX_IGNORED },
8410 { "nopQ", { Ev }, PREFIX_IGNORED },
8411 { "nopQ", { Ev }, PREFIX_IGNORED },
8412 { "nopQ", { Ev }, PREFIX_IGNORED },
8413 },
8414 {
8415 /* RM_0FAE_REG_6_MOD_3 */
8416 { "mfence", { Skip_MODRM }, 0 },
8417 },
8418 {
8419 /* RM_0FAE_REG_7_MOD_3 */
8420 { "sfence", { Skip_MODRM }, 0 },
8421 },
8422 {
8423 /* RM_0F3A0F_P_1_R_0 */
8424 { "hreset", { Skip_MODRM, Ib }, 0 },
8425 },
8426 {
8427 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0 */
8428 { "tilerelease", { Skip_MODRM }, 0 },
8429 },
8430 {
8431 /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
8432 { "tilezero", { TMM, Skip_MODRM }, 0 },
8433 },
8434 };
8435
8436 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8437
8438 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8439 in conflict with actual prefix opcodes. */
8440 #define REP_PREFIX 0x01
8441 #define XACQUIRE_PREFIX 0x02
8442 #define XRELEASE_PREFIX 0x03
8443 #define BND_PREFIX 0x04
8444 #define NOTRACK_PREFIX 0x05
8445
8446 static enum {
8447 ckp_okay,
8448 ckp_bogus,
8449 ckp_fetch_error,
8450 }
ckprefix(instr_info * ins)8451 ckprefix (instr_info *ins)
8452 {
8453 int i, length;
8454 uint8_t newrex;
8455
8456 i = 0;
8457 length = 0;
8458 /* The maximum instruction length is 15bytes. */
8459 while (length < MAX_CODE_LENGTH - 1)
8460 {
8461 if (!fetch_code (ins->info, ins->codep + 1))
8462 return ckp_fetch_error;
8463 newrex = 0;
8464 switch (*ins->codep)
8465 {
8466 /* REX prefixes family. */
8467 case 0x40:
8468 case 0x41:
8469 case 0x42:
8470 case 0x43:
8471 case 0x44:
8472 case 0x45:
8473 case 0x46:
8474 case 0x47:
8475 case 0x48:
8476 case 0x49:
8477 case 0x4a:
8478 case 0x4b:
8479 case 0x4c:
8480 case 0x4d:
8481 case 0x4e:
8482 case 0x4f:
8483 if (ins->address_mode == mode_64bit)
8484 newrex = *ins->codep;
8485 else
8486 return ckp_okay;
8487 ins->last_rex_prefix = i;
8488 break;
8489 /* REX2 must be the last prefix. */
8490 case REX2_OPCODE:
8491 if (ins->address_mode == mode_64bit)
8492 {
8493 if (ins->last_rex_prefix >= 0)
8494 return ckp_bogus;
8495
8496 ins->codep++;
8497 if (!fetch_code (ins->info, ins->codep + 1))
8498 return ckp_fetch_error;
8499 ins->rex2_payload = *ins->codep;
8500 ins->rex2 = ins->rex2_payload >> 4;
8501 ins->rex = (ins->rex2_payload & 0xf) | REX_OPCODE;
8502 ins->codep++;
8503 ins->last_rex2_prefix = i;
8504 ins->all_prefixes[i] = REX2_OPCODE;
8505 }
8506 return ckp_okay;
8507 case 0xf3:
8508 ins->prefixes |= PREFIX_REPZ;
8509 ins->last_repz_prefix = i;
8510 break;
8511 case 0xf2:
8512 ins->prefixes |= PREFIX_REPNZ;
8513 ins->last_repnz_prefix = i;
8514 break;
8515 case 0xf0:
8516 ins->prefixes |= PREFIX_LOCK;
8517 ins->last_lock_prefix = i;
8518 break;
8519 case 0x2e:
8520 ins->prefixes |= PREFIX_CS;
8521 ins->last_seg_prefix = i;
8522 if (ins->address_mode != mode_64bit)
8523 ins->active_seg_prefix = PREFIX_CS;
8524 break;
8525 case 0x36:
8526 ins->prefixes |= PREFIX_SS;
8527 ins->last_seg_prefix = i;
8528 if (ins->address_mode != mode_64bit)
8529 ins->active_seg_prefix = PREFIX_SS;
8530 break;
8531 case 0x3e:
8532 ins->prefixes |= PREFIX_DS;
8533 ins->last_seg_prefix = i;
8534 if (ins->address_mode != mode_64bit)
8535 ins->active_seg_prefix = PREFIX_DS;
8536 break;
8537 case 0x26:
8538 ins->prefixes |= PREFIX_ES;
8539 ins->last_seg_prefix = i;
8540 if (ins->address_mode != mode_64bit)
8541 ins->active_seg_prefix = PREFIX_ES;
8542 break;
8543 case 0x64:
8544 ins->prefixes |= PREFIX_FS;
8545 ins->last_seg_prefix = i;
8546 ins->active_seg_prefix = PREFIX_FS;
8547 break;
8548 case 0x65:
8549 ins->prefixes |= PREFIX_GS;
8550 ins->last_seg_prefix = i;
8551 ins->active_seg_prefix = PREFIX_GS;
8552 break;
8553 case 0x66:
8554 ins->prefixes |= PREFIX_DATA;
8555 ins->last_data_prefix = i;
8556 break;
8557 case 0x67:
8558 ins->prefixes |= PREFIX_ADDR;
8559 ins->last_addr_prefix = i;
8560 break;
8561 case FWAIT_OPCODE:
8562 /* fwait is really an instruction. If there are prefixes
8563 before the fwait, they belong to the fwait, *not* to the
8564 following instruction. */
8565 ins->fwait_prefix = i;
8566 if (ins->prefixes || ins->rex)
8567 {
8568 ins->prefixes |= PREFIX_FWAIT;
8569 ins->codep++;
8570 /* This ensures that the previous REX prefixes are noticed
8571 as unused prefixes, as in the return case below. */
8572 return ins->rex ? ckp_bogus : ckp_okay;
8573 }
8574 ins->prefixes = PREFIX_FWAIT;
8575 break;
8576 default:
8577 return ckp_okay;
8578 }
8579 /* Rex is ignored when followed by another prefix. */
8580 if (ins->rex)
8581 return ckp_bogus;
8582 if (*ins->codep != FWAIT_OPCODE)
8583 ins->all_prefixes[i++] = *ins->codep;
8584 ins->rex = newrex;
8585 ins->codep++;
8586 length++;
8587 }
8588 return ckp_bogus;
8589 }
8590
8591 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8592 prefix byte. */
8593
8594 static const char *
prefix_name(enum address_mode mode,uint8_t pref,int sizeflag)8595 prefix_name (enum address_mode mode, uint8_t pref, int sizeflag)
8596 {
8597 static const char *rexes [16] =
8598 {
8599 "rex", /* 0x40 */
8600 "rex.B", /* 0x41 */
8601 "rex.X", /* 0x42 */
8602 "rex.XB", /* 0x43 */
8603 "rex.R", /* 0x44 */
8604 "rex.RB", /* 0x45 */
8605 "rex.RX", /* 0x46 */
8606 "rex.RXB", /* 0x47 */
8607 "rex.W", /* 0x48 */
8608 "rex.WB", /* 0x49 */
8609 "rex.WX", /* 0x4a */
8610 "rex.WXB", /* 0x4b */
8611 "rex.WR", /* 0x4c */
8612 "rex.WRB", /* 0x4d */
8613 "rex.WRX", /* 0x4e */
8614 "rex.WRXB", /* 0x4f */
8615 };
8616
8617 switch (pref)
8618 {
8619 /* REX prefixes family. */
8620 case 0x40:
8621 case 0x41:
8622 case 0x42:
8623 case 0x43:
8624 case 0x44:
8625 case 0x45:
8626 case 0x46:
8627 case 0x47:
8628 case 0x48:
8629 case 0x49:
8630 case 0x4a:
8631 case 0x4b:
8632 case 0x4c:
8633 case 0x4d:
8634 case 0x4e:
8635 case 0x4f:
8636 return rexes [pref - 0x40];
8637 case 0xf3:
8638 return "repz";
8639 case 0xf2:
8640 return "repnz";
8641 case 0xf0:
8642 return "lock";
8643 case 0x2e:
8644 return "cs";
8645 case 0x36:
8646 return "ss";
8647 case 0x3e:
8648 return "ds";
8649 case 0x26:
8650 return "es";
8651 case 0x64:
8652 return "fs";
8653 case 0x65:
8654 return "gs";
8655 case 0x66:
8656 return (sizeflag & DFLAG) ? "data16" : "data32";
8657 case 0x67:
8658 if (mode == mode_64bit)
8659 return (sizeflag & AFLAG) ? "addr32" : "addr64";
8660 else
8661 return (sizeflag & AFLAG) ? "addr16" : "addr32";
8662 case FWAIT_OPCODE:
8663 return "fwait";
8664 case REP_PREFIX:
8665 return "rep";
8666 case XACQUIRE_PREFIX:
8667 return "xacquire";
8668 case XRELEASE_PREFIX:
8669 return "xrelease";
8670 case BND_PREFIX:
8671 return "bnd";
8672 case NOTRACK_PREFIX:
8673 return "notrack";
8674 case REX2_OPCODE:
8675 return "rex2";
8676 default:
8677 return NULL;
8678 }
8679 }
8680
8681 void
print_i386_disassembler_options(FILE * stream)8682 print_i386_disassembler_options (FILE *stream)
8683 {
8684 fprintf (stream, _("\n\
8685 The following i386/x86-64 specific disassembler options are supported for use\n\
8686 with the -M switch (multiple options should be separated by commas):\n"));
8687
8688 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
8689 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
8690 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
8691 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
8692 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
8693 fprintf (stream, _(" att-mnemonic (AT&T syntax only)\n"
8694 " Display instruction with AT&T mnemonic\n"));
8695 fprintf (stream, _(" intel-mnemonic (AT&T syntax only)\n"
8696 " Display instruction with Intel mnemonic\n"));
8697 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
8698 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
8699 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
8700 fprintf (stream, _(" data32 Assume 32bit data size\n"));
8701 fprintf (stream, _(" data16 Assume 16bit data size\n"));
8702 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
8703 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
8704 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
8705 }
8706
8707 /* Bad opcode. */
8708 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8709
8710 /* Fetch error indicator. */
8711 static const struct dis386 err_opcode = { NULL, { XX }, 0 };
8712
8713 static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) };
8714
8715 /* Get a pointer to struct dis386 with a valid name. */
8716
8717 static const struct dis386 *
get_valid_dis386(const struct dis386 * dp,instr_info * ins)8718 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
8719 {
8720 int vindex, vex_table_index;
8721
8722 if (dp->name != NULL)
8723 return dp;
8724
8725 switch (dp->op[0].bytemode)
8726 {
8727 case USE_REG_TABLE:
8728 dp = ®_table[dp->op[1].bytemode][ins->modrm.reg];
8729 break;
8730
8731 case USE_MOD_TABLE:
8732 vindex = ins->modrm.mod == 0x3 ? 1 : 0;
8733 dp = &mod_table[dp->op[1].bytemode][vindex];
8734 break;
8735
8736 case USE_RM_TABLE:
8737 dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
8738 break;
8739
8740 case USE_PREFIX_TABLE:
8741 if (ins->need_vex)
8742 {
8743 /* The prefix in VEX is implicit. */
8744 switch (ins->vex.prefix)
8745 {
8746 case 0:
8747 vindex = 0;
8748 break;
8749 case REPE_PREFIX_OPCODE:
8750 vindex = 1;
8751 break;
8752 case DATA_PREFIX_OPCODE:
8753 vindex = 2;
8754 break;
8755 case REPNE_PREFIX_OPCODE:
8756 vindex = 3;
8757 break;
8758 default:
8759 abort ();
8760 break;
8761 }
8762 }
8763 else
8764 {
8765 int last_prefix = -1;
8766 int prefix = 0;
8767 vindex = 0;
8768 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8769 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8770 last one wins. */
8771 if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8772 {
8773 if (ins->last_repz_prefix > ins->last_repnz_prefix)
8774 {
8775 vindex = 1;
8776 prefix = PREFIX_REPZ;
8777 last_prefix = ins->last_repz_prefix;
8778 }
8779 else
8780 {
8781 vindex = 3;
8782 prefix = PREFIX_REPNZ;
8783 last_prefix = ins->last_repnz_prefix;
8784 }
8785
8786 /* Check if prefix should be ignored. */
8787 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8788 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8789 & prefix) != 0
8790 && !prefix_table[dp->op[1].bytemode][vindex].name)
8791 vindex = 0;
8792 }
8793
8794 if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
8795 {
8796 vindex = 2;
8797 prefix = PREFIX_DATA;
8798 last_prefix = ins->last_data_prefix;
8799 }
8800
8801 if (vindex != 0)
8802 {
8803 ins->used_prefixes |= prefix;
8804 ins->all_prefixes[last_prefix] = 0;
8805 }
8806 }
8807 dp = &prefix_table[dp->op[1].bytemode][vindex];
8808 break;
8809
8810 case USE_X86_64_EVEX_FROM_VEX_TABLE:
8811 ins->evex_type = evex_from_vex;
8812 /* EVEX from VEX instrucions require that EVEX.z, EVEX.L’L, EVEX.b and
8813 the lower 2 bits of EVEX.aaa must be 0. */
8814 if ((ins->vex.mask_register_specifier & 0x3) != 0
8815 || ins->vex.ll != 0
8816 || ins->vex.zeroing != 0
8817 || ins->vex.b)
8818 return &bad_opcode;
8819
8820 /* Fall through. */
8821 case USE_X86_64_TABLE:
8822 vindex = ins->address_mode == mode_64bit ? 1 : 0;
8823 dp = &x86_64_table[dp->op[1].bytemode][vindex];
8824 break;
8825
8826 case USE_3BYTE_TABLE:
8827 if (!fetch_code (ins->info, ins->codep + 2))
8828 return &err_opcode;
8829 vindex = *ins->codep++;
8830 dp = &three_byte_table[dp->op[1].bytemode][vindex];
8831 ins->end_codep = ins->codep;
8832 if (!fetch_modrm (ins))
8833 return &err_opcode;
8834 break;
8835
8836 case USE_VEX_LEN_TABLE:
8837 if (!ins->need_vex)
8838 abort ();
8839
8840 switch (ins->vex.length)
8841 {
8842 case 128:
8843 vindex = 0;
8844 break;
8845 case 512:
8846 /* This allows re-using in particular table entries where only
8847 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */
8848 if (ins->vex.evex)
8849 {
8850 case 256:
8851 vindex = 1;
8852 break;
8853 }
8854 /* Fall through. */
8855 default:
8856 abort ();
8857 break;
8858 }
8859
8860 dp = &vex_len_table[dp->op[1].bytemode][vindex];
8861 break;
8862
8863 case USE_EVEX_LEN_TABLE:
8864 if (!ins->vex.evex)
8865 abort ();
8866
8867 switch (ins->vex.length)
8868 {
8869 case 128:
8870 vindex = 0;
8871 break;
8872 case 256:
8873 vindex = 1;
8874 break;
8875 case 512:
8876 vindex = 2;
8877 break;
8878 default:
8879 abort ();
8880 break;
8881 }
8882
8883 dp = &evex_len_table[dp->op[1].bytemode][vindex];
8884 break;
8885
8886 case USE_XOP_8F_TABLE:
8887 if (!fetch_code (ins->info, ins->codep + 3))
8888 return &err_opcode;
8889 ins->rex = ~(*ins->codep >> 5) & 0x7;
8890
8891 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
8892 switch ((*ins->codep & 0x1f))
8893 {
8894 default:
8895 dp = &bad_opcode;
8896 return dp;
8897 case 0x8:
8898 vex_table_index = XOP_08;
8899 break;
8900 case 0x9:
8901 vex_table_index = XOP_09;
8902 break;
8903 case 0xa:
8904 vex_table_index = XOP_0A;
8905 break;
8906 }
8907 ins->codep++;
8908 ins->vex.w = *ins->codep & 0x80;
8909 if (ins->vex.w && ins->address_mode == mode_64bit)
8910 ins->rex |= REX_W;
8911
8912 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8913 if (ins->address_mode != mode_64bit)
8914 {
8915 /* In 16/32-bit mode REX_B is silently ignored. */
8916 ins->rex &= ~REX_B;
8917 }
8918
8919 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8920 switch ((*ins->codep & 0x3))
8921 {
8922 case 0:
8923 break;
8924 case 1:
8925 ins->vex.prefix = DATA_PREFIX_OPCODE;
8926 break;
8927 case 2:
8928 ins->vex.prefix = REPE_PREFIX_OPCODE;
8929 break;
8930 case 3:
8931 ins->vex.prefix = REPNE_PREFIX_OPCODE;
8932 break;
8933 }
8934 ins->need_vex = 3;
8935 ins->codep++;
8936 vindex = *ins->codep++;
8937 dp = &xop_table[vex_table_index][vindex];
8938
8939 ins->end_codep = ins->codep;
8940 if (!fetch_modrm (ins))
8941 return &err_opcode;
8942
8943 /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
8944 having to decode the bits for every otherwise valid encoding. */
8945 if (ins->vex.prefix)
8946 return &bad_opcode;
8947 break;
8948
8949 case USE_VEX_C4_TABLE:
8950 /* VEX prefix. */
8951 if (!fetch_code (ins->info, ins->codep + 3))
8952 return &err_opcode;
8953 ins->rex = ~(*ins->codep >> 5) & 0x7;
8954 switch ((*ins->codep & 0x1f))
8955 {
8956 default:
8957 dp = &bad_opcode;
8958 return dp;
8959 case 0x1:
8960 vex_table_index = VEX_0F;
8961 break;
8962 case 0x2:
8963 vex_table_index = VEX_0F38;
8964 break;
8965 case 0x3:
8966 vex_table_index = VEX_0F3A;
8967 break;
8968 case 0x7:
8969 vex_table_index = VEX_MAP7;
8970 break;
8971 }
8972 ins->codep++;
8973 ins->vex.w = *ins->codep & 0x80;
8974 if (ins->address_mode == mode_64bit)
8975 {
8976 if (ins->vex.w)
8977 ins->rex |= REX_W;
8978 }
8979 else
8980 {
8981 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
8982 is ignored, other REX bits are 0 and the highest bit in
8983 VEX.vvvv is also ignored (but we mustn't clear it here). */
8984 ins->rex = 0;
8985 }
8986 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8987 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8988 switch ((*ins->codep & 0x3))
8989 {
8990 case 0:
8991 break;
8992 case 1:
8993 ins->vex.prefix = DATA_PREFIX_OPCODE;
8994 break;
8995 case 2:
8996 ins->vex.prefix = REPE_PREFIX_OPCODE;
8997 break;
8998 case 3:
8999 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9000 break;
9001 }
9002 ins->need_vex = 3;
9003 ins->codep++;
9004 vindex = *ins->codep++;
9005 if (vex_table_index != VEX_MAP7)
9006 dp = &vex_table[vex_table_index][vindex];
9007 else if (vindex == 0xf8)
9008 dp = &map7_f8_opcode;
9009 else
9010 dp = &bad_opcode;
9011 ins->end_codep = ins->codep;
9012 /* There is no MODRM byte for VEX0F 77. */
9013 if ((vex_table_index != VEX_0F || vindex != 0x77)
9014 && !fetch_modrm (ins))
9015 return &err_opcode;
9016 break;
9017
9018 case USE_VEX_C5_TABLE:
9019 /* VEX prefix. */
9020 if (!fetch_code (ins->info, ins->codep + 2))
9021 return &err_opcode;
9022 ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9023
9024 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9025 VEX.vvvv is 1. */
9026 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9027 ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9028 switch ((*ins->codep & 0x3))
9029 {
9030 case 0:
9031 break;
9032 case 1:
9033 ins->vex.prefix = DATA_PREFIX_OPCODE;
9034 break;
9035 case 2:
9036 ins->vex.prefix = REPE_PREFIX_OPCODE;
9037 break;
9038 case 3:
9039 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9040 break;
9041 }
9042 ins->need_vex = 2;
9043 ins->codep++;
9044 vindex = *ins->codep++;
9045 dp = &vex_table[VEX_0F][vindex];
9046 ins->end_codep = ins->codep;
9047 /* There is no MODRM byte for VEX 77. */
9048 if (vindex != 0x77 && !fetch_modrm (ins))
9049 return &err_opcode;
9050 break;
9051
9052 case USE_VEX_W_TABLE:
9053 if (!ins->need_vex)
9054 abort ();
9055
9056 dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9057 break;
9058
9059 case USE_EVEX_TABLE:
9060 ins->two_source_ops = false;
9061 /* EVEX prefix. */
9062 ins->vex.evex = true;
9063 if (!fetch_code (ins->info, ins->codep + 4))
9064 return &err_opcode;
9065 /* The first byte after 0x62. */
9066 if (*ins->codep & 0x8)
9067 ins->rex2 |= REX_B;
9068 if (!(*ins->codep & 0x10))
9069 ins->rex2 |= REX_R;
9070
9071 ins->rex = ~(*ins->codep >> 5) & 0x7;
9072 switch (*ins->codep & 0x7)
9073 {
9074 default:
9075 return &bad_opcode;
9076 case 0x1:
9077 vex_table_index = EVEX_0F;
9078 break;
9079 case 0x2:
9080 vex_table_index = EVEX_0F38;
9081 break;
9082 case 0x3:
9083 vex_table_index = EVEX_0F3A;
9084 break;
9085 case 0x4:
9086 vex_table_index = EVEX_MAP4;
9087 ins->evex_type = evex_from_legacy;
9088 if (ins->address_mode != mode_64bit)
9089 return &bad_opcode;
9090 break;
9091 case 0x5:
9092 vex_table_index = EVEX_MAP5;
9093 break;
9094 case 0x6:
9095 vex_table_index = EVEX_MAP6;
9096 break;
9097 case 0x7:
9098 vex_table_index = EVEX_MAP7;
9099 break;
9100 }
9101
9102 /* The second byte after 0x62. */
9103 ins->codep++;
9104 ins->vex.w = *ins->codep & 0x80;
9105 if (ins->vex.w && ins->address_mode == mode_64bit)
9106 ins->rex |= REX_W;
9107
9108 ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9109
9110 if (!(*ins->codep & 0x4))
9111 ins->rex2 |= REX_X;
9112
9113 switch ((*ins->codep & 0x3))
9114 {
9115 case 0:
9116 break;
9117 case 1:
9118 ins->vex.prefix = DATA_PREFIX_OPCODE;
9119 break;
9120 case 2:
9121 ins->vex.prefix = REPE_PREFIX_OPCODE;
9122 break;
9123 case 3:
9124 ins->vex.prefix = REPNE_PREFIX_OPCODE;
9125 break;
9126 }
9127
9128 /* The third byte after 0x62. */
9129 ins->codep++;
9130
9131 /* Remember the static rounding bits. */
9132 ins->vex.ll = (*ins->codep >> 5) & 3;
9133 ins->vex.b = *ins->codep & 0x10;
9134
9135 ins->vex.v = *ins->codep & 0x8;
9136 ins->vex.mask_register_specifier = *ins->codep & 0x7;
9137 ins->vex.zeroing = *ins->codep & 0x80;
9138
9139 if (ins->address_mode != mode_64bit)
9140 {
9141 /* Report bad for !evex_default and when two fixed values of evex
9142 change.. */
9143 if (ins->evex_type != evex_default
9144 || (ins->rex2 & (REX_B | REX_X)))
9145 return &bad_opcode;
9146 /* In 16/32-bit mode silently ignore following bits. */
9147 ins->rex &= ~REX_B;
9148 ins->rex2 &= ~REX_R;
9149 }
9150
9151 /* EVEX from legacy instructions, when the EVEX.ND bit is 0,
9152 all bits of EVEX.vvvv and EVEX.V' must be 1. */
9153 if (ins->evex_type == evex_from_legacy && !ins->vex.nd
9154 && (ins->vex.register_specifier || !ins->vex.v))
9155 return &bad_opcode;
9156
9157 ins->need_vex = 4;
9158
9159 /* EVEX from legacy instructions require that EVEX.z, EVEX.L’L and the
9160 lower 2 bits of EVEX.aaa must be 0. */
9161 if (ins->evex_type == evex_from_legacy
9162 && ((ins->vex.mask_register_specifier & 0x3) != 0
9163 || ins->vex.ll != 0
9164 || ins->vex.zeroing != 0))
9165 return &bad_opcode;
9166
9167 ins->codep++;
9168 vindex = *ins->codep++;
9169 if (vex_table_index != EVEX_MAP7)
9170 dp = &evex_table[vex_table_index][vindex];
9171 else if (vindex == 0xf8)
9172 dp = &map7_f8_opcode;
9173 else
9174 dp = &bad_opcode;
9175 ins->end_codep = ins->codep;
9176 if (!fetch_modrm (ins))
9177 return &err_opcode;
9178
9179 /* Set vector length. For EVEX-promoted instructions, evex.ll == 0b00,
9180 which has the same encoding as vex.length == 128 and they can share
9181 the same processing with vex.length in OP_VEX. */
9182 if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type != evex_from_legacy)
9183 ins->vex.length = 512;
9184 else
9185 {
9186 switch (ins->vex.ll)
9187 {
9188 case 0x0:
9189 ins->vex.length = 128;
9190 break;
9191 case 0x1:
9192 ins->vex.length = 256;
9193 break;
9194 case 0x2:
9195 ins->vex.length = 512;
9196 break;
9197 default:
9198 return &bad_opcode;
9199 }
9200 }
9201 break;
9202
9203 case 0:
9204 dp = &bad_opcode;
9205 break;
9206
9207 default:
9208 abort ();
9209 }
9210
9211 if (dp->name != NULL)
9212 return dp;
9213 else
9214 return get_valid_dis386 (dp, ins);
9215 }
9216
9217 static bool
get_sib(instr_info * ins,int sizeflag)9218 get_sib (instr_info *ins, int sizeflag)
9219 {
9220 /* If modrm.mod == 3, operand must be register. */
9221 if (ins->need_modrm
9222 && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9223 && ins->modrm.mod != 3
9224 && ins->modrm.rm == 4)
9225 {
9226 if (!fetch_code (ins->info, ins->codep + 2))
9227 return false;
9228 ins->sib.index = (ins->codep[1] >> 3) & 7;
9229 ins->sib.scale = (ins->codep[1] >> 6) & 3;
9230 ins->sib.base = ins->codep[1] & 7;
9231 ins->has_sib = true;
9232 }
9233 else
9234 ins->has_sib = false;
9235
9236 return true;
9237 }
9238
9239 /* Like oappend_with_style (below) but always with text style. */
9240
9241 static void
oappend(instr_info * ins,const char * s)9242 oappend (instr_info *ins, const char *s)
9243 {
9244 oappend_with_style (ins, s, dis_style_text);
9245 }
9246
9247 /* Like oappend (above), but S is a string starting with '%'. In
9248 Intel syntax, the '%' is elided. */
9249
9250 static void
oappend_register(instr_info * ins,const char * s)9251 oappend_register (instr_info *ins, const char *s)
9252 {
9253 oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9254 }
9255
9256 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9257 STYLE is the default style to use in the fprintf_styled_func calls,
9258 however, FMT might include embedded style markers (see oappend_style),
9259 these embedded markers are not printed, but instead change the style
9260 used in the next fprintf_styled_func call. */
9261
9262 static void ATTRIBUTE_PRINTF_3
i386_dis_printf(const disassemble_info * info,enum disassembler_style style,const char * fmt,...)9263 i386_dis_printf (const disassemble_info *info, enum disassembler_style style,
9264 const char *fmt, ...)
9265 {
9266 va_list ap;
9267 enum disassembler_style curr_style = style;
9268 const char *start, *curr;
9269 char staging_area[40];
9270
9271 va_start (ap, fmt);
9272 /* In particular print_insn()'s processing of op_txt[] can hand rather long
9273 strings here. Bypass vsnprintf() in such cases to avoid capacity issues
9274 with the staging area. */
9275 if (strcmp (fmt, "%s"))
9276 {
9277 int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9278
9279 va_end (ap);
9280
9281 if (res < 0)
9282 return;
9283
9284 if ((size_t) res >= sizeof (staging_area))
9285 abort ();
9286
9287 start = curr = staging_area;
9288 }
9289 else
9290 {
9291 start = curr = va_arg (ap, const char *);
9292 va_end (ap);
9293 }
9294
9295 do
9296 {
9297 if (*curr == '\0'
9298 || (*curr == STYLE_MARKER_CHAR
9299 && ISXDIGIT (*(curr + 1))
9300 && *(curr + 2) == STYLE_MARKER_CHAR))
9301 {
9302 /* Output content between our START position and CURR. */
9303 int len = curr - start;
9304 int n = (*info->fprintf_styled_func) (info->stream, curr_style,
9305 "%.*s", len, start);
9306 if (n < 0)
9307 break;
9308
9309 if (*curr == '\0')
9310 break;
9311
9312 /* Skip over the initial STYLE_MARKER_CHAR. */
9313 ++curr;
9314
9315 /* Update the CURR_STYLE. As there are less than 16 styles, it
9316 is possible, that if the input is corrupted in some way, that
9317 we might set CURR_STYLE to an invalid value. Don't worry
9318 though, we check for this situation. */
9319 if (*curr >= '0' && *curr <= '9')
9320 curr_style = (enum disassembler_style) (*curr - '0');
9321 else if (*curr >= 'a' && *curr <= 'f')
9322 curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9323 else
9324 curr_style = dis_style_text;
9325
9326 /* Check for an invalid style having been selected. This should
9327 never happen, but it doesn't hurt to be a little paranoid. */
9328 if (curr_style > dis_style_comment_start)
9329 curr_style = dis_style_text;
9330
9331 /* Skip the hex character, and the closing STYLE_MARKER_CHAR. */
9332 curr += 2;
9333
9334 /* Reset the START to after the style marker. */
9335 start = curr;
9336 }
9337 else
9338 ++curr;
9339 }
9340 while (true);
9341 }
9342
9343 static int
print_insn(bfd_vma pc,disassemble_info * info,int intel_syntax)9344 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9345 {
9346 const struct dis386 *dp;
9347 int i;
9348 int ret;
9349 char *op_txt[MAX_OPERANDS];
9350 int needcomma;
9351 bool intel_swap_2_3;
9352 int sizeflag, orig_sizeflag;
9353 const char *p;
9354 struct dis_private priv;
9355 int prefix_length;
9356 int op_count;
9357 instr_info ins = {
9358 .info = info,
9359 .intel_syntax = intel_syntax >= 0
9360 ? intel_syntax
9361 : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9362 .intel_mnemonic = !SYSV386_COMPAT,
9363 .op_index[0 ... MAX_OPERANDS - 1] = -1,
9364 .start_pc = pc,
9365 .start_codep = priv.the_buffer,
9366 .codep = priv.the_buffer,
9367 .obufp = ins.obuf,
9368 .last_lock_prefix = -1,
9369 .last_repz_prefix = -1,
9370 .last_repnz_prefix = -1,
9371 .last_data_prefix = -1,
9372 .last_addr_prefix = -1,
9373 .last_rex_prefix = -1,
9374 .last_rex2_prefix = -1,
9375 .last_seg_prefix = -1,
9376 .fwait_prefix = -1,
9377 };
9378 char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9379
9380 priv.orig_sizeflag = AFLAG | DFLAG;
9381 if ((info->mach & bfd_mach_i386_i386) != 0)
9382 ins.address_mode = mode_32bit;
9383 else if (info->mach == bfd_mach_i386_i8086)
9384 {
9385 ins.address_mode = mode_16bit;
9386 priv.orig_sizeflag = 0;
9387 }
9388 else
9389 ins.address_mode = mode_64bit;
9390
9391 for (p = info->disassembler_options; p != NULL;)
9392 {
9393 if (startswith (p, "amd64"))
9394 ins.isa64 = amd64;
9395 else if (startswith (p, "intel64"))
9396 ins.isa64 = intel64;
9397 else if (startswith (p, "x86-64"))
9398 {
9399 ins.address_mode = mode_64bit;
9400 priv.orig_sizeflag |= AFLAG | DFLAG;
9401 }
9402 else if (startswith (p, "i386"))
9403 {
9404 ins.address_mode = mode_32bit;
9405 priv.orig_sizeflag |= AFLAG | DFLAG;
9406 }
9407 else if (startswith (p, "i8086"))
9408 {
9409 ins.address_mode = mode_16bit;
9410 priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9411 }
9412 else if (startswith (p, "intel"))
9413 {
9414 if (startswith (p + 5, "-mnemonic"))
9415 ins.intel_mnemonic = true;
9416 else
9417 ins.intel_syntax = 1;
9418 }
9419 else if (startswith (p, "att"))
9420 {
9421 ins.intel_syntax = 0;
9422 if (startswith (p + 3, "-mnemonic"))
9423 ins.intel_mnemonic = false;
9424 }
9425 else if (startswith (p, "addr"))
9426 {
9427 if (ins.address_mode == mode_64bit)
9428 {
9429 if (p[4] == '3' && p[5] == '2')
9430 priv.orig_sizeflag &= ~AFLAG;
9431 else if (p[4] == '6' && p[5] == '4')
9432 priv.orig_sizeflag |= AFLAG;
9433 }
9434 else
9435 {
9436 if (p[4] == '1' && p[5] == '6')
9437 priv.orig_sizeflag &= ~AFLAG;
9438 else if (p[4] == '3' && p[5] == '2')
9439 priv.orig_sizeflag |= AFLAG;
9440 }
9441 }
9442 else if (startswith (p, "data"))
9443 {
9444 if (p[4] == '1' && p[5] == '6')
9445 priv.orig_sizeflag &= ~DFLAG;
9446 else if (p[4] == '3' && p[5] == '2')
9447 priv.orig_sizeflag |= DFLAG;
9448 }
9449 else if (startswith (p, "suffix"))
9450 priv.orig_sizeflag |= SUFFIX_ALWAYS;
9451
9452 p = strchr (p, ',');
9453 if (p != NULL)
9454 p++;
9455 }
9456
9457 if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9458 {
9459 i386_dis_printf (info, dis_style_text, _("64-bit address is disabled"));
9460 return -1;
9461 }
9462
9463 if (ins.intel_syntax)
9464 {
9465 ins.open_char = '[';
9466 ins.close_char = ']';
9467 ins.separator_char = '+';
9468 ins.scale_char = '*';
9469 }
9470 else
9471 {
9472 ins.open_char = '(';
9473 ins.close_char = ')';
9474 ins.separator_char = ',';
9475 ins.scale_char = ',';
9476 }
9477
9478 /* The output looks better if we put 7 bytes on a line, since that
9479 puts most long word instructions on a single line. */
9480 info->bytes_per_line = 7;
9481
9482 info->private_data = &priv;
9483 priv.fetched = 0;
9484 priv.insn_start = pc;
9485
9486 for (i = 0; i < MAX_OPERANDS; ++i)
9487 {
9488 op_out[i][0] = 0;
9489 ins.op_out[i] = op_out[i];
9490 }
9491
9492 sizeflag = priv.orig_sizeflag;
9493
9494 switch (ckprefix (&ins))
9495 {
9496 case ckp_okay:
9497 break;
9498
9499 case ckp_bogus:
9500 /* Too many prefixes or unused REX prefixes. */
9501 for (i = 0;
9502 i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9503 i++)
9504 i386_dis_printf (info, dis_style_mnemonic, "%s%s",
9505 (i == 0 ? "" : " "),
9506 prefix_name (ins.address_mode, ins.all_prefixes[i],
9507 sizeflag));
9508 ret = i;
9509 goto out;
9510
9511 case ckp_fetch_error:
9512 goto fetch_error_out;
9513 }
9514
9515 ins.nr_prefixes = ins.codep - ins.start_codep;
9516
9517 if (!fetch_code (info, ins.codep + 1))
9518 {
9519 fetch_error_out:
9520 ret = fetch_error (&ins);
9521 goto out;
9522 }
9523
9524 ins.two_source_ops = (*ins.codep == 0x62 || *ins.codep == 0xc8);
9525
9526 if ((ins.prefixes & PREFIX_FWAIT)
9527 && (*ins.codep < 0xd8 || *ins.codep > 0xdf))
9528 {
9529 /* Handle ins.prefixes before fwait. */
9530 for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9531 i++)
9532 i386_dis_printf (info, dis_style_mnemonic, "%s ",
9533 prefix_name (ins.address_mode, ins.all_prefixes[i],
9534 sizeflag));
9535 i386_dis_printf (info, dis_style_mnemonic, "fwait");
9536 ret = i + 1;
9537 goto out;
9538 }
9539
9540 /* REX2.M in rex2 prefix represents map0 or map1. */
9541 if (ins.last_rex2_prefix < 0 ? *ins.codep == 0x0f : (ins.rex2 & REX2_M))
9542 {
9543 unsigned char threebyte;
9544
9545 if (!ins.rex2)
9546 {
9547 ins.codep++;
9548 if (!fetch_code (info, ins.codep + 1))
9549 goto fetch_error_out;
9550 }
9551
9552 threebyte = *ins.codep;
9553 dp = &dis386_twobyte[threebyte];
9554 ins.need_modrm = twobyte_has_modrm[threebyte];
9555 ins.codep++;
9556 }
9557 else
9558 {
9559 dp = &dis386[*ins.codep];
9560 ins.need_modrm = onebyte_has_modrm[*ins.codep];
9561 ins.codep++;
9562 }
9563
9564 /* Save sizeflag for printing the extra ins.prefixes later before updating
9565 it for mnemonic and operand processing. The prefix names depend
9566 only on the address mode. */
9567 orig_sizeflag = sizeflag;
9568 if (ins.prefixes & PREFIX_ADDR)
9569 sizeflag ^= AFLAG;
9570 if ((ins.prefixes & PREFIX_DATA))
9571 sizeflag ^= DFLAG;
9572
9573 ins.end_codep = ins.codep;
9574 if (ins.need_modrm && !fetch_modrm (&ins))
9575 goto fetch_error_out;
9576
9577 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9578 {
9579 if (!get_sib (&ins, sizeflag)
9580 || !dofloat (&ins, sizeflag))
9581 goto fetch_error_out;
9582 }
9583 else
9584 {
9585 dp = get_valid_dis386 (dp, &ins);
9586 if (dp == &err_opcode)
9587 goto fetch_error_out;
9588
9589 /* For APX instructions promoted from legacy maps 0/1, embedded prefix
9590 is interpreted as the operand size override. */
9591 if (ins.evex_type == evex_from_legacy
9592 && ins.vex.prefix == DATA_PREFIX_OPCODE)
9593 sizeflag ^= DFLAG;
9594
9595 if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9596 {
9597 if (!get_sib (&ins, sizeflag))
9598 goto fetch_error_out;
9599 for (i = 0; i < MAX_OPERANDS; ++i)
9600 {
9601 ins.obufp = ins.op_out[i];
9602 ins.op_ad = MAX_OPERANDS - 1 - i;
9603 if (dp->op[i].rtn
9604 && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag))
9605 goto fetch_error_out;
9606 /* For EVEX instruction after the last operand masking
9607 should be printed. */
9608 if (i == 0 && ins.vex.evex)
9609 {
9610 /* Don't print {%k0}. */
9611 if (ins.vex.mask_register_specifier)
9612 {
9613 const char *reg_name
9614 = att_names_mask[ins.vex.mask_register_specifier];
9615
9616 oappend (&ins, "{");
9617 oappend_register (&ins, reg_name);
9618 oappend (&ins, "}");
9619
9620 if (ins.vex.zeroing)
9621 oappend (&ins, "{z}");
9622 }
9623 else if (ins.vex.zeroing)
9624 {
9625 oappend (&ins, "{bad}");
9626 continue;
9627 }
9628
9629 /* Instructions with a mask register destination allow for
9630 zeroing-masking only (if any masking at all), which is
9631 _not_ expressed by EVEX.z. */
9632 if (ins.vex.zeroing && dp->op[0].bytemode == mask_mode)
9633 ins.illegal_masking = true;
9634
9635 /* S/G insns require a mask and don't allow
9636 zeroing-masking. */
9637 if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9638 || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9639 && (ins.vex.mask_register_specifier == 0
9640 || ins.vex.zeroing))
9641 ins.illegal_masking = true;
9642
9643 if (ins.illegal_masking)
9644 oappend (&ins, "/(bad)");
9645 }
9646 }
9647
9648 /* Check whether rounding control was enabled for an insn not
9649 supporting it, when evex.b is not treated as evex.nd. */
9650 if (ins.modrm.mod == 3 && ins.vex.b && ins.evex_type == evex_default
9651 && !(ins.evex_used & EVEX_b_used))
9652 {
9653 for (i = 0; i < MAX_OPERANDS; ++i)
9654 {
9655 ins.obufp = ins.op_out[i];
9656 if (*ins.obufp)
9657 continue;
9658 oappend (&ins, names_rounding[ins.vex.ll]);
9659 oappend (&ins, "bad}");
9660 break;
9661 }
9662 }
9663 }
9664 }
9665
9666 /* Clear instruction information. */
9667 info->insn_info_valid = 0;
9668 info->branch_delay_insns = 0;
9669 info->data_size = 0;
9670 info->insn_type = dis_noninsn;
9671 info->target = 0;
9672 info->target2 = 0;
9673
9674 /* Reset jump operation indicator. */
9675 ins.op_is_jump = false;
9676 {
9677 int jump_detection = 0;
9678
9679 /* Extract flags. */
9680 for (i = 0; i < MAX_OPERANDS; ++i)
9681 {
9682 if ((dp->op[i].rtn == OP_J)
9683 || (dp->op[i].rtn == OP_indirE))
9684 jump_detection |= 1;
9685 else if ((dp->op[i].rtn == BND_Fixup)
9686 || (!dp->op[i].rtn && !dp->op[i].bytemode))
9687 jump_detection |= 2;
9688 else if ((dp->op[i].bytemode == cond_jump_mode)
9689 || (dp->op[i].bytemode == loop_jcxz_mode))
9690 jump_detection |= 4;
9691 }
9692
9693 /* Determine if this is a jump or branch. */
9694 if ((jump_detection & 0x3) == 0x3)
9695 {
9696 ins.op_is_jump = true;
9697 if (jump_detection & 0x4)
9698 info->insn_type = dis_condbranch;
9699 else
9700 info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9701 ? dis_jsr : dis_branch;
9702 }
9703 }
9704
9705 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9706 are all 0s in inverted form. */
9707 if (ins.need_vex && ins.vex.register_specifier != 0)
9708 {
9709 i386_dis_printf (info, dis_style_text, "(bad)");
9710 ret = ins.end_codep - priv.the_buffer;
9711 goto out;
9712 }
9713
9714 if ((dp->prefix_requirement & PREFIX_REX2_ILLEGAL)
9715 && ins.last_rex2_prefix >= 0 && (ins.rex2 & REX2_SPECIAL) == 0)
9716 {
9717 i386_dis_printf (info, dis_style_text, "(bad)");
9718 ret = ins.end_codep - priv.the_buffer;
9719 goto out;
9720 }
9721
9722 switch (dp->prefix_requirement & ~PREFIX_REX2_ILLEGAL)
9723 {
9724 case PREFIX_DATA:
9725 /* If only the data prefix is marked as mandatory, its absence renders
9726 the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
9727 if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
9728 {
9729 i386_dis_printf (info, dis_style_text, "(bad)");
9730 ret = ins.end_codep - priv.the_buffer;
9731 goto out;
9732 }
9733 ins.used_prefixes |= PREFIX_DATA;
9734 /* Fall through. */
9735 case PREFIX_OPCODE:
9736 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9737 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
9738 used by putop and MMX/SSE operand and may be overridden by the
9739 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9740 separately. */
9741 if (((ins.need_vex
9742 ? ins.vex.prefix == REPE_PREFIX_OPCODE
9743 || ins.vex.prefix == REPNE_PREFIX_OPCODE
9744 : (ins.prefixes
9745 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9746 && (ins.used_prefixes
9747 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9748 || (((ins.need_vex
9749 ? ins.vex.prefix == DATA_PREFIX_OPCODE
9750 : ((ins.prefixes
9751 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9752 == PREFIX_DATA))
9753 && (ins.used_prefixes & PREFIX_DATA) == 0))
9754 || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
9755 && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
9756 {
9757 i386_dis_printf (info, dis_style_text, "(bad)");
9758 ret = ins.end_codep - priv.the_buffer;
9759 goto out;
9760 }
9761 break;
9762
9763 case PREFIX_IGNORED:
9764 /* Zap data size and rep prefixes from used_prefixes and reinstate their
9765 origins in all_prefixes. */
9766 ins.used_prefixes &= ~PREFIX_OPCODE;
9767 if (ins.last_data_prefix >= 0)
9768 ins.all_prefixes[ins.last_data_prefix] = 0x66;
9769 if (ins.last_repz_prefix >= 0)
9770 ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
9771 if (ins.last_repnz_prefix >= 0)
9772 ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
9773 break;
9774
9775 case PREFIX_NP_OR_DATA:
9776 if (ins.vex.prefix == REPE_PREFIX_OPCODE
9777 || ins.vex.prefix == REPNE_PREFIX_OPCODE)
9778 {
9779 i386_dis_printf (info, dis_style_text, "(bad)");
9780 ret = ins.end_codep - priv.the_buffer;
9781 goto out;
9782 }
9783 break;
9784
9785 case NO_PREFIX:
9786 if (ins.vex.prefix)
9787 {
9788 i386_dis_printf (info, dis_style_text, "(bad)");
9789 ret = ins.end_codep - priv.the_buffer;
9790 goto out;
9791 }
9792 break;
9793 }
9794
9795 /* Check if the REX prefix is used. */
9796 if ((ins.rex ^ ins.rex_used) == 0
9797 && !ins.need_vex && ins.last_rex_prefix >= 0)
9798 ins.all_prefixes[ins.last_rex_prefix] = 0;
9799
9800 /* Check if the REX2 prefix is used. */
9801 if (ins.last_rex2_prefix >= 0
9802 && ((ins.rex2 & REX2_SPECIAL)
9803 || (((ins.rex2 & 7) ^ (ins.rex2_used & 7)) == 0
9804 && (ins.rex ^ ins.rex_used) == 0
9805 && (ins.rex2 & 7))))
9806 ins.all_prefixes[ins.last_rex2_prefix] = 0;
9807
9808 /* Check if the SEG prefix is used. */
9809 if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9810 | PREFIX_FS | PREFIX_GS)) != 0
9811 && (ins.used_prefixes & ins.active_seg_prefix) != 0)
9812 ins.all_prefixes[ins.last_seg_prefix] = 0;
9813
9814 /* Check if the ADDR prefix is used. */
9815 if ((ins.prefixes & PREFIX_ADDR) != 0
9816 && (ins.used_prefixes & PREFIX_ADDR) != 0)
9817 ins.all_prefixes[ins.last_addr_prefix] = 0;
9818
9819 /* Check if the DATA prefix is used. */
9820 if ((ins.prefixes & PREFIX_DATA) != 0
9821 && (ins.used_prefixes & PREFIX_DATA) != 0
9822 && !ins.need_vex)
9823 ins.all_prefixes[ins.last_data_prefix] = 0;
9824
9825 /* Print the extra ins.prefixes. */
9826 prefix_length = 0;
9827 for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
9828 if (ins.all_prefixes[i])
9829 {
9830 const char *name = prefix_name (ins.address_mode, ins.all_prefixes[i],
9831 orig_sizeflag);
9832
9833 if (name == NULL)
9834 abort ();
9835 prefix_length += strlen (name) + 1;
9836 if (ins.all_prefixes[i] == REX2_OPCODE)
9837 i386_dis_printf (info, dis_style_mnemonic, "{%s 0x%x} ", name,
9838 (unsigned int) ins.rex2_payload);
9839 else
9840 i386_dis_printf (info, dis_style_mnemonic, "%s ", name);
9841 }
9842
9843 /* Check maximum code length. */
9844 if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
9845 {
9846 i386_dis_printf (info, dis_style_text, "(bad)");
9847 ret = MAX_CODE_LENGTH;
9848 goto out;
9849 }
9850
9851 /* Calculate the number of operands this instruction has. */
9852 op_count = 0;
9853 for (i = 0; i < MAX_OPERANDS; ++i)
9854 if (*ins.op_out[i] != '\0')
9855 ++op_count;
9856
9857 /* Calculate the number of spaces to print after the mnemonic. */
9858 ins.obufp = ins.mnemonicendp;
9859 if (op_count > 0)
9860 {
9861 i = strlen (ins.obuf) + prefix_length;
9862 if (i < 7)
9863 i = 7 - i;
9864 else
9865 i = 1;
9866 }
9867 else
9868 i = 0;
9869
9870 /* Print the instruction mnemonic along with any trailing whitespace. */
9871 i386_dis_printf (info, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
9872
9873 /* The enter and bound instructions are printed with operands in the same
9874 order as the intel book; everything else is printed in reverse order. */
9875 intel_swap_2_3 = false;
9876 if (ins.intel_syntax || ins.two_source_ops)
9877 {
9878 for (i = 0; i < MAX_OPERANDS; ++i)
9879 op_txt[i] = ins.op_out[i];
9880
9881 if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9882 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9883 {
9884 op_txt[2] = ins.op_out[3];
9885 op_txt[3] = ins.op_out[2];
9886 intel_swap_2_3 = true;
9887 }
9888
9889 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9890 {
9891 bool riprel;
9892
9893 ins.op_ad = ins.op_index[i];
9894 ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
9895 ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
9896 riprel = ins.op_riprel[i];
9897 ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
9898 ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9899 }
9900 }
9901 else
9902 {
9903 for (i = 0; i < MAX_OPERANDS; ++i)
9904 op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
9905 }
9906
9907 needcomma = 0;
9908 for (i = 0; i < MAX_OPERANDS; ++i)
9909 if (*op_txt[i])
9910 {
9911 /* In Intel syntax embedded rounding / SAE are not separate operands.
9912 Instead they're attached to the prior register operand. Simply
9913 suppress emission of the comma to achieve that effect. */
9914 switch (i & -(ins.intel_syntax && dp))
9915 {
9916 case 2:
9917 if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
9918 needcomma = 0;
9919 break;
9920 case 3:
9921 if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
9922 needcomma = 0;
9923 break;
9924 }
9925 if (needcomma)
9926 i386_dis_printf (info, dis_style_text, ",");
9927 if (ins.op_index[i] != -1 && !ins.op_riprel[i])
9928 {
9929 bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
9930
9931 if (ins.op_is_jump)
9932 {
9933 info->insn_info_valid = 1;
9934 info->branch_delay_insns = 0;
9935 info->data_size = 0;
9936 info->target = target;
9937 info->target2 = 0;
9938 }
9939 (*info->print_address_func) (target, info);
9940 }
9941 else
9942 i386_dis_printf (info, dis_style_text, "%s", op_txt[i]);
9943 needcomma = 1;
9944 }
9945
9946 for (i = 0; i < MAX_OPERANDS; i++)
9947 if (ins.op_index[i] != -1 && ins.op_riprel[i])
9948 {
9949 i386_dis_printf (info, dis_style_comment_start, " # ");
9950 (*info->print_address_func)
9951 ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
9952 + ins.op_address[ins.op_index[i]]),
9953 info);
9954 break;
9955 }
9956 ret = ins.codep - priv.the_buffer;
9957 out:
9958 info->private_data = NULL;
9959 return ret;
9960 }
9961
9962 /* Here for backwards compatibility. When gdb stops using
9963 print_insn_i386_att and print_insn_i386_intel these functions can
9964 disappear, and print_insn_i386 be merged into print_insn. */
9965 int
print_insn_i386_att(bfd_vma pc,disassemble_info * info)9966 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9967 {
9968 return print_insn (pc, info, 0);
9969 }
9970
9971 int
print_insn_i386_intel(bfd_vma pc,disassemble_info * info)9972 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9973 {
9974 return print_insn (pc, info, 1);
9975 }
9976
9977 int
print_insn_i386(bfd_vma pc,disassemble_info * info)9978 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9979 {
9980 return print_insn (pc, info, -1);
9981 }
9982
9983 static const char *float_mem[] = {
9984 /* d8 */
9985 "fadd{s|}",
9986 "fmul{s|}",
9987 "fcom{s|}",
9988 "fcomp{s|}",
9989 "fsub{s|}",
9990 "fsubr{s|}",
9991 "fdiv{s|}",
9992 "fdivr{s|}",
9993 /* d9 */
9994 "fld{s|}",
9995 "(bad)",
9996 "fst{s|}",
9997 "fstp{s|}",
9998 "fldenv{C|C}",
9999 "fldcw",
10000 "fNstenv{C|C}",
10001 "fNstcw",
10002 /* da */
10003 "fiadd{l|}",
10004 "fimul{l|}",
10005 "ficom{l|}",
10006 "ficomp{l|}",
10007 "fisub{l|}",
10008 "fisubr{l|}",
10009 "fidiv{l|}",
10010 "fidivr{l|}",
10011 /* db */
10012 "fild{l|}",
10013 "fisttp{l|}",
10014 "fist{l|}",
10015 "fistp{l|}",
10016 "(bad)",
10017 "fld{t|}",
10018 "(bad)",
10019 "fstp{t|}",
10020 /* dc */
10021 "fadd{l|}",
10022 "fmul{l|}",
10023 "fcom{l|}",
10024 "fcomp{l|}",
10025 "fsub{l|}",
10026 "fsubr{l|}",
10027 "fdiv{l|}",
10028 "fdivr{l|}",
10029 /* dd */
10030 "fld{l|}",
10031 "fisttp{ll|}",
10032 "fst{l||}",
10033 "fstp{l|}",
10034 "frstor{C|C}",
10035 "(bad)",
10036 "fNsave{C|C}",
10037 "fNstsw",
10038 /* de */
10039 "fiadd{s|}",
10040 "fimul{s|}",
10041 "ficom{s|}",
10042 "ficomp{s|}",
10043 "fisub{s|}",
10044 "fisubr{s|}",
10045 "fidiv{s|}",
10046 "fidivr{s|}",
10047 /* df */
10048 "fild{s|}",
10049 "fisttp{s|}",
10050 "fist{s|}",
10051 "fistp{s|}",
10052 "fbld",
10053 "fild{ll|}",
10054 "fbstp",
10055 "fistp{ll|}",
10056 };
10057
10058 static const unsigned char float_mem_mode[] = {
10059 /* d8 */
10060 d_mode,
10061 d_mode,
10062 d_mode,
10063 d_mode,
10064 d_mode,
10065 d_mode,
10066 d_mode,
10067 d_mode,
10068 /* d9 */
10069 d_mode,
10070 0,
10071 d_mode,
10072 d_mode,
10073 0,
10074 w_mode,
10075 0,
10076 w_mode,
10077 /* da */
10078 d_mode,
10079 d_mode,
10080 d_mode,
10081 d_mode,
10082 d_mode,
10083 d_mode,
10084 d_mode,
10085 d_mode,
10086 /* db */
10087 d_mode,
10088 d_mode,
10089 d_mode,
10090 d_mode,
10091 0,
10092 t_mode,
10093 0,
10094 t_mode,
10095 /* dc */
10096 q_mode,
10097 q_mode,
10098 q_mode,
10099 q_mode,
10100 q_mode,
10101 q_mode,
10102 q_mode,
10103 q_mode,
10104 /* dd */
10105 q_mode,
10106 q_mode,
10107 q_mode,
10108 q_mode,
10109 0,
10110 0,
10111 0,
10112 w_mode,
10113 /* de */
10114 w_mode,
10115 w_mode,
10116 w_mode,
10117 w_mode,
10118 w_mode,
10119 w_mode,
10120 w_mode,
10121 w_mode,
10122 /* df */
10123 w_mode,
10124 w_mode,
10125 w_mode,
10126 w_mode,
10127 t_mode,
10128 q_mode,
10129 t_mode,
10130 q_mode
10131 };
10132
10133 #define ST { OP_ST, 0 }
10134 #define STi { OP_STi, 0 }
10135
10136 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10137 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10138 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10139 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10140 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10141 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10142 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10143 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10144 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10145
10146 static const struct dis386 float_reg[][8] = {
10147 /* d8 */
10148 {
10149 { "fadd", { ST, STi }, 0 },
10150 { "fmul", { ST, STi }, 0 },
10151 { "fcom", { STi }, 0 },
10152 { "fcomp", { STi }, 0 },
10153 { "fsub", { ST, STi }, 0 },
10154 { "fsubr", { ST, STi }, 0 },
10155 { "fdiv", { ST, STi }, 0 },
10156 { "fdivr", { ST, STi }, 0 },
10157 },
10158 /* d9 */
10159 {
10160 { "fld", { STi }, 0 },
10161 { "fxch", { STi }, 0 },
10162 { FGRPd9_2 },
10163 { Bad_Opcode },
10164 { FGRPd9_4 },
10165 { FGRPd9_5 },
10166 { FGRPd9_6 },
10167 { FGRPd9_7 },
10168 },
10169 /* da */
10170 {
10171 { "fcmovb", { ST, STi }, 0 },
10172 { "fcmove", { ST, STi }, 0 },
10173 { "fcmovbe",{ ST, STi }, 0 },
10174 { "fcmovu", { ST, STi }, 0 },
10175 { Bad_Opcode },
10176 { FGRPda_5 },
10177 { Bad_Opcode },
10178 { Bad_Opcode },
10179 },
10180 /* db */
10181 {
10182 { "fcmovnb",{ ST, STi }, 0 },
10183 { "fcmovne",{ ST, STi }, 0 },
10184 { "fcmovnbe",{ ST, STi }, 0 },
10185 { "fcmovnu",{ ST, STi }, 0 },
10186 { FGRPdb_4 },
10187 { "fucomi", { ST, STi }, 0 },
10188 { "fcomi", { ST, STi }, 0 },
10189 { Bad_Opcode },
10190 },
10191 /* dc */
10192 {
10193 { "fadd", { STi, ST }, 0 },
10194 { "fmul", { STi, ST }, 0 },
10195 { Bad_Opcode },
10196 { Bad_Opcode },
10197 { "fsub{!M|r}", { STi, ST }, 0 },
10198 { "fsub{M|}", { STi, ST }, 0 },
10199 { "fdiv{!M|r}", { STi, ST }, 0 },
10200 { "fdiv{M|}", { STi, ST }, 0 },
10201 },
10202 /* dd */
10203 {
10204 { "ffree", { STi }, 0 },
10205 { Bad_Opcode },
10206 { "fst", { STi }, 0 },
10207 { "fstp", { STi }, 0 },
10208 { "fucom", { STi }, 0 },
10209 { "fucomp", { STi }, 0 },
10210 { Bad_Opcode },
10211 { Bad_Opcode },
10212 },
10213 /* de */
10214 {
10215 { "faddp", { STi, ST }, 0 },
10216 { "fmulp", { STi, ST }, 0 },
10217 { Bad_Opcode },
10218 { FGRPde_3 },
10219 { "fsub{!M|r}p", { STi, ST }, 0 },
10220 { "fsub{M|}p", { STi, ST }, 0 },
10221 { "fdiv{!M|r}p", { STi, ST }, 0 },
10222 { "fdiv{M|}p", { STi, ST }, 0 },
10223 },
10224 /* df */
10225 {
10226 { "ffreep", { STi }, 0 },
10227 { Bad_Opcode },
10228 { Bad_Opcode },
10229 { Bad_Opcode },
10230 { FGRPdf_4 },
10231 { "fucomip", { ST, STi }, 0 },
10232 { "fcomip", { ST, STi }, 0 },
10233 { Bad_Opcode },
10234 },
10235 };
10236
10237 static const char *const fgrps[][8] = {
10238 /* Bad opcode 0 */
10239 {
10240 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10241 },
10242
10243 /* d9_2 1 */
10244 {
10245 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10246 },
10247
10248 /* d9_4 2 */
10249 {
10250 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10251 },
10252
10253 /* d9_5 3 */
10254 {
10255 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10256 },
10257
10258 /* d9_6 4 */
10259 {
10260 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10261 },
10262
10263 /* d9_7 5 */
10264 {
10265 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10266 },
10267
10268 /* da_5 6 */
10269 {
10270 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10271 },
10272
10273 /* db_4 7 */
10274 {
10275 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10276 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10277 },
10278
10279 /* de_3 8 */
10280 {
10281 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10282 },
10283
10284 /* df_4 9 */
10285 {
10286 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10287 },
10288 };
10289
10290 static void
swap_operand(instr_info * ins)10291 swap_operand (instr_info *ins)
10292 {
10293 ins->mnemonicendp[0] = '.';
10294 ins->mnemonicendp[1] = 's';
10295 ins->mnemonicendp[2] = '\0';
10296 ins->mnemonicendp += 2;
10297 }
10298
10299 static bool
dofloat(instr_info * ins,int sizeflag)10300 dofloat (instr_info *ins, int sizeflag)
10301 {
10302 const struct dis386 *dp;
10303 unsigned char floatop = ins->codep[-1];
10304
10305 if (ins->modrm.mod != 3)
10306 {
10307 int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10308
10309 putop (ins, float_mem[fp_indx], sizeflag);
10310 ins->obufp = ins->op_out[0];
10311 ins->op_ad = 2;
10312 return OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10313 }
10314 /* Skip mod/rm byte. */
10315 MODRM_CHECK;
10316 ins->codep++;
10317
10318 dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10319 if (dp->name == NULL)
10320 {
10321 putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10322
10323 /* Instruction fnstsw is only one with strange arg. */
10324 if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10325 strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10326 }
10327 else
10328 {
10329 putop (ins, dp->name, sizeflag);
10330
10331 ins->obufp = ins->op_out[0];
10332 ins->op_ad = 2;
10333 if (dp->op[0].rtn
10334 && !dp->op[0].rtn (ins, dp->op[0].bytemode, sizeflag))
10335 return false;
10336
10337 ins->obufp = ins->op_out[1];
10338 ins->op_ad = 1;
10339 if (dp->op[1].rtn
10340 && !dp->op[1].rtn (ins, dp->op[1].bytemode, sizeflag))
10341 return false;
10342 }
10343 return true;
10344 }
10345
10346 static bool
OP_ST(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)10347 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10348 int sizeflag ATTRIBUTE_UNUSED)
10349 {
10350 oappend_register (ins, "%st");
10351 return true;
10352 }
10353
10354 static bool
OP_STi(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)10355 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10356 int sizeflag ATTRIBUTE_UNUSED)
10357 {
10358 char scratch[8];
10359 int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10360
10361 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10362 abort ();
10363 oappend_register (ins, scratch);
10364 return true;
10365 }
10366
10367 /* Capital letters in template are macros. */
10368 static int
putop(instr_info * ins,const char * in_template,int sizeflag)10369 putop (instr_info *ins, const char *in_template, int sizeflag)
10370 {
10371 const char *p;
10372 int alt = 0;
10373 int cond = 1;
10374 unsigned int l = 0, len = 0;
10375 char last[4];
10376
10377 for (p = in_template; *p; p++)
10378 {
10379 if (len > l)
10380 {
10381 if (l >= sizeof (last) || !ISUPPER (*p))
10382 abort ();
10383 last[l++] = *p;
10384 continue;
10385 }
10386 switch (*p)
10387 {
10388 default:
10389 *ins->obufp++ = *p;
10390 break;
10391 case '%':
10392 len++;
10393 break;
10394 case '!':
10395 cond = 0;
10396 break;
10397 case '{':
10398 if (ins->intel_syntax)
10399 {
10400 while (*++p != '|')
10401 if (*p == '}' || *p == '\0')
10402 abort ();
10403 alt = 1;
10404 }
10405 break;
10406 case '|':
10407 while (*++p != '}')
10408 {
10409 if (*p == '\0')
10410 abort ();
10411 }
10412 break;
10413 case '}':
10414 alt = 0;
10415 break;
10416 case 'A':
10417 if (ins->intel_syntax)
10418 break;
10419 if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10420 || (sizeflag & SUFFIX_ALWAYS))
10421 *ins->obufp++ = 'b';
10422 break;
10423 case 'B':
10424 if (l == 0)
10425 {
10426 case_B:
10427 if (ins->intel_syntax)
10428 break;
10429 if (sizeflag & SUFFIX_ALWAYS)
10430 *ins->obufp++ = 'b';
10431 }
10432 else if (l == 1 && last[0] == 'L')
10433 {
10434 if (ins->address_mode == mode_64bit
10435 && !(ins->prefixes & PREFIX_ADDR))
10436 {
10437 *ins->obufp++ = 'a';
10438 *ins->obufp++ = 'b';
10439 *ins->obufp++ = 's';
10440 }
10441
10442 goto case_B;
10443 }
10444 else
10445 abort ();
10446 break;
10447 case 'C':
10448 if (ins->intel_syntax && !alt)
10449 break;
10450 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10451 {
10452 if (sizeflag & DFLAG)
10453 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10454 else
10455 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10456 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10457 }
10458 break;
10459 case 'D':
10460 if (l == 1)
10461 {
10462 switch (last[0])
10463 {
10464 case 'X':
10465 if (!ins->vex.evex || ins->vex.w)
10466 *ins->obufp++ = 'd';
10467 else
10468 oappend (ins, "{bad}");
10469 break;
10470 default:
10471 abort ();
10472 }
10473 break;
10474 }
10475 if (l)
10476 abort ();
10477 if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10478 break;
10479 USED_REX (REX_W);
10480 if (ins->modrm.mod == 3)
10481 {
10482 if (ins->rex & REX_W)
10483 *ins->obufp++ = 'q';
10484 else
10485 {
10486 if (sizeflag & DFLAG)
10487 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10488 else
10489 *ins->obufp++ = 'w';
10490 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10491 }
10492 }
10493 else
10494 *ins->obufp++ = 'w';
10495 break;
10496 case 'E':
10497 if (l == 1)
10498 {
10499 switch (last[0])
10500 {
10501 case 'X':
10502 if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10503 || (ins->rex2 & 7)
10504 || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10505 || !ins->vex.v || ins->vex.mask_register_specifier)
10506 break;
10507 /* AVX512 extends a number of V*D insns to also have V*Q variants,
10508 merely distinguished by EVEX.W. Look for a use of the
10509 respective macro. */
10510 if (ins->vex.w)
10511 {
10512 const char *pct = strchr (p + 1, '%');
10513
10514 if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10515 break;
10516 }
10517 *ins->obufp++ = '{';
10518 *ins->obufp++ = 'e';
10519 *ins->obufp++ = 'v';
10520 *ins->obufp++ = 'e';
10521 *ins->obufp++ = 'x';
10522 *ins->obufp++ = '}';
10523 *ins->obufp++ = ' ';
10524 break;
10525 default:
10526 abort ();
10527 }
10528 break;
10529 }
10530 /* For jcxz/jecxz */
10531 if (ins->address_mode == mode_64bit)
10532 {
10533 if (sizeflag & AFLAG)
10534 *ins->obufp++ = 'r';
10535 else
10536 *ins->obufp++ = 'e';
10537 }
10538 else
10539 if (sizeflag & AFLAG)
10540 *ins->obufp++ = 'e';
10541 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10542 break;
10543 case 'F':
10544 if (l == 0)
10545 {
10546 if (ins->intel_syntax)
10547 break;
10548 if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10549 {
10550 if (sizeflag & AFLAG)
10551 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10552 else
10553 *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10554 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10555 }
10556 }
10557 else if (l == 1 && last[0] == 'C')
10558 break;
10559 else
10560 abort ();
10561 break;
10562 case 'G':
10563 if (ins->intel_syntax || (ins->obufp[-1] != 's'
10564 && !(sizeflag & SUFFIX_ALWAYS)))
10565 break;
10566 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10567 *ins->obufp++ = 'l';
10568 else
10569 *ins->obufp++ = 'w';
10570 if (!(ins->rex & REX_W))
10571 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10572 break;
10573 case 'H':
10574 if (l == 0)
10575 {
10576 if (ins->intel_syntax)
10577 break;
10578 if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10579 || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10580 {
10581 ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10582 *ins->obufp++ = ',';
10583 *ins->obufp++ = 'p';
10584
10585 /* Set active_seg_prefix even if not set in 64-bit mode
10586 because here it is a valid branch hint. */
10587 if (ins->prefixes & PREFIX_DS)
10588 {
10589 ins->active_seg_prefix = PREFIX_DS;
10590 *ins->obufp++ = 't';
10591 }
10592 else
10593 {
10594 ins->active_seg_prefix = PREFIX_CS;
10595 *ins->obufp++ = 'n';
10596 }
10597 }
10598 }
10599 else if (l == 1 && last[0] == 'X')
10600 {
10601 if (!ins->vex.w)
10602 *ins->obufp++ = 'h';
10603 else
10604 oappend (ins, "{bad}");
10605 }
10606 else
10607 abort ();
10608 break;
10609 case 'K':
10610 USED_REX (REX_W);
10611 if (ins->rex & REX_W)
10612 *ins->obufp++ = 'q';
10613 else
10614 *ins->obufp++ = 'd';
10615 break;
10616 case 'L':
10617 if (ins->intel_syntax)
10618 break;
10619 if (sizeflag & SUFFIX_ALWAYS)
10620 {
10621 if (ins->rex & REX_W)
10622 *ins->obufp++ = 'q';
10623 else
10624 *ins->obufp++ = 'l';
10625 }
10626 break;
10627 case 'M':
10628 if (ins->intel_mnemonic != cond)
10629 *ins->obufp++ = 'r';
10630 break;
10631 case 'N':
10632 if ((ins->prefixes & PREFIX_FWAIT) == 0)
10633 *ins->obufp++ = 'n';
10634 else
10635 ins->used_prefixes |= PREFIX_FWAIT;
10636 break;
10637 case 'O':
10638 USED_REX (REX_W);
10639 if (ins->rex & REX_W)
10640 *ins->obufp++ = 'o';
10641 else if (ins->intel_syntax && (sizeflag & DFLAG))
10642 *ins->obufp++ = 'q';
10643 else
10644 *ins->obufp++ = 'd';
10645 if (!(ins->rex & REX_W))
10646 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10647 break;
10648 case '@':
10649 if (ins->address_mode == mode_64bit
10650 && (ins->isa64 == intel64 || (ins->rex & REX_W)
10651 || !(ins->prefixes & PREFIX_DATA)))
10652 {
10653 if (sizeflag & SUFFIX_ALWAYS)
10654 *ins->obufp++ = 'q';
10655 break;
10656 }
10657 /* Fall through. */
10658 case 'P':
10659 if (l == 0)
10660 {
10661 if (!cond && ins->last_rex2_prefix >= 0 && (ins->rex & REX_W))
10662 {
10663 /* For pushp and popp, p is printed and do not print {rex2}
10664 for them. */
10665 *ins->obufp++ = 'p';
10666 ins->rex2 |= REX2_SPECIAL;
10667 break;
10668 }
10669
10670 /* For "!P" print nothing else in Intel syntax. */
10671 if (!cond && ins->intel_syntax)
10672 break;
10673
10674 if ((ins->modrm.mod == 3 || !cond)
10675 && !(sizeflag & SUFFIX_ALWAYS))
10676 break;
10677 /* Fall through. */
10678 case 'T':
10679 if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10680 || ((sizeflag & SUFFIX_ALWAYS)
10681 && ins->address_mode != mode_64bit))
10682 {
10683 *ins->obufp++ = (sizeflag & DFLAG)
10684 ? ins->intel_syntax ? 'd' : 'l' : 'w';
10685 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10686 }
10687 else if (sizeflag & SUFFIX_ALWAYS)
10688 *ins->obufp++ = 'q';
10689 }
10690 else if (l == 1 && last[0] == 'L')
10691 {
10692 if ((ins->prefixes & PREFIX_DATA)
10693 || (ins->rex & REX_W)
10694 || (sizeflag & SUFFIX_ALWAYS))
10695 {
10696 USED_REX (REX_W);
10697 if (ins->rex & REX_W)
10698 *ins->obufp++ = 'q';
10699 else
10700 {
10701 if (sizeflag & DFLAG)
10702 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10703 else
10704 *ins->obufp++ = 'w';
10705 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10706 }
10707 }
10708 }
10709 else
10710 abort ();
10711 break;
10712 case 'Q':
10713 if (l == 0)
10714 {
10715 if (ins->intel_syntax && !alt)
10716 break;
10717 USED_REX (REX_W);
10718 if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10719 || (sizeflag & SUFFIX_ALWAYS))
10720 {
10721 if (ins->rex & REX_W)
10722 *ins->obufp++ = 'q';
10723 else
10724 {
10725 if (sizeflag & DFLAG)
10726 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10727 else
10728 *ins->obufp++ = 'w';
10729 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10730 }
10731 }
10732 }
10733 else if (l == 1 && last[0] == 'D')
10734 *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10735 else if (l == 1 && last[0] == 'L')
10736 {
10737 if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10738 : ins->address_mode != mode_64bit)
10739 break;
10740 if ((ins->rex & REX_W))
10741 {
10742 USED_REX (REX_W);
10743 *ins->obufp++ = 'q';
10744 }
10745 else if ((ins->address_mode == mode_64bit && cond)
10746 || (sizeflag & SUFFIX_ALWAYS))
10747 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10748 }
10749 else
10750 abort ();
10751 break;
10752 case 'R':
10753 USED_REX (REX_W);
10754 if (ins->rex & REX_W)
10755 *ins->obufp++ = 'q';
10756 else if (sizeflag & DFLAG)
10757 {
10758 if (ins->intel_syntax)
10759 *ins->obufp++ = 'd';
10760 else
10761 *ins->obufp++ = 'l';
10762 }
10763 else
10764 *ins->obufp++ = 'w';
10765 if (ins->intel_syntax && !p[1]
10766 && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10767 *ins->obufp++ = 'e';
10768 if (!(ins->rex & REX_W))
10769 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10770 break;
10771 case 'S':
10772 if (l == 0)
10773 {
10774 case_S:
10775 if (ins->intel_syntax)
10776 break;
10777 if (sizeflag & SUFFIX_ALWAYS)
10778 {
10779 if (ins->rex & REX_W)
10780 *ins->obufp++ = 'q';
10781 else
10782 {
10783 if (sizeflag & DFLAG)
10784 *ins->obufp++ = 'l';
10785 else
10786 *ins->obufp++ = 'w';
10787 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10788 }
10789 }
10790 break;
10791 }
10792 if (l != 1)
10793 abort ();
10794 switch (last[0])
10795 {
10796 case 'L':
10797 if (ins->address_mode == mode_64bit
10798 && !(ins->prefixes & PREFIX_ADDR))
10799 {
10800 *ins->obufp++ = 'a';
10801 *ins->obufp++ = 'b';
10802 *ins->obufp++ = 's';
10803 }
10804
10805 goto case_S;
10806 case 'X':
10807 if (!ins->vex.evex || !ins->vex.w)
10808 *ins->obufp++ = 's';
10809 else
10810 oappend (ins, "{bad}");
10811 break;
10812 default:
10813 abort ();
10814 }
10815 break;
10816 case 'V':
10817 if (l == 0)
10818 {
10819 if (ins->need_vex)
10820 *ins->obufp++ = 'v';
10821 }
10822 else if (l == 1)
10823 {
10824 switch (last[0])
10825 {
10826 case 'X':
10827 if (ins->vex.evex)
10828 break;
10829 *ins->obufp++ = '{';
10830 *ins->obufp++ = 'v';
10831 *ins->obufp++ = 'e';
10832 *ins->obufp++ = 'x';
10833 *ins->obufp++ = '}';
10834 *ins->obufp++ = ' ';
10835 break;
10836 case 'L':
10837 if (ins->rex & REX_W)
10838 {
10839 *ins->obufp++ = 'a';
10840 *ins->obufp++ = 'b';
10841 *ins->obufp++ = 's';
10842 }
10843 goto case_S;
10844 default:
10845 abort ();
10846 }
10847 }
10848 else
10849 abort ();
10850 break;
10851 case 'W':
10852 if (l == 0)
10853 {
10854 /* operand size flag for cwtl, cbtw */
10855 USED_REX (REX_W);
10856 if (ins->rex & REX_W)
10857 {
10858 if (ins->intel_syntax)
10859 *ins->obufp++ = 'd';
10860 else
10861 *ins->obufp++ = 'l';
10862 }
10863 else if (sizeflag & DFLAG)
10864 *ins->obufp++ = 'w';
10865 else
10866 *ins->obufp++ = 'b';
10867 if (!(ins->rex & REX_W))
10868 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10869 }
10870 else if (l == 1)
10871 {
10872 if (!ins->need_vex)
10873 abort ();
10874 if (last[0] == 'X')
10875 *ins->obufp++ = ins->vex.w ? 'd': 's';
10876 else if (last[0] == 'B')
10877 *ins->obufp++ = ins->vex.w ? 'w': 'b';
10878 else
10879 abort ();
10880 }
10881 else
10882 abort ();
10883 break;
10884 case 'X':
10885 if (l != 0)
10886 abort ();
10887 if (ins->need_vex
10888 ? ins->vex.prefix == DATA_PREFIX_OPCODE
10889 : ins->prefixes & PREFIX_DATA)
10890 {
10891 *ins->obufp++ = 'd';
10892 ins->used_prefixes |= PREFIX_DATA;
10893 }
10894 else
10895 *ins->obufp++ = 's';
10896 break;
10897 case 'Y':
10898 if (l == 0)
10899 {
10900 if (ins->vex.mask_register_specifier)
10901 ins->illegal_masking = true;
10902 }
10903 else if (l == 1 && last[0] == 'X')
10904 {
10905 if (!ins->need_vex)
10906 break;
10907 if (ins->intel_syntax
10908 || ((ins->modrm.mod == 3 || ins->vex.b)
10909 && !(sizeflag & SUFFIX_ALWAYS)))
10910 break;
10911 switch (ins->vex.length)
10912 {
10913 case 128:
10914 *ins->obufp++ = 'x';
10915 break;
10916 case 256:
10917 *ins->obufp++ = 'y';
10918 break;
10919 case 512:
10920 if (!ins->vex.evex)
10921 default:
10922 abort ();
10923 }
10924 }
10925 else
10926 abort ();
10927 break;
10928 case 'Z':
10929 if (l == 0)
10930 {
10931 /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
10932 ins->modrm.mod = 3;
10933 if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10934 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10935 }
10936 else if (l == 1 && last[0] == 'X')
10937 {
10938 if (!ins->vex.evex)
10939 abort ();
10940 if (ins->intel_syntax
10941 || ((ins->modrm.mod == 3 || ins->vex.b)
10942 && !(sizeflag & SUFFIX_ALWAYS)))
10943 break;
10944 switch (ins->vex.length)
10945 {
10946 case 128:
10947 *ins->obufp++ = 'x';
10948 break;
10949 case 256:
10950 *ins->obufp++ = 'y';
10951 break;
10952 case 512:
10953 *ins->obufp++ = 'z';
10954 break;
10955 default:
10956 abort ();
10957 }
10958 }
10959 else
10960 abort ();
10961 break;
10962 case '^':
10963 if (ins->intel_syntax)
10964 break;
10965 if (ins->isa64 == intel64 && (ins->rex & REX_W))
10966 {
10967 USED_REX (REX_W);
10968 *ins->obufp++ = 'q';
10969 break;
10970 }
10971 if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10972 {
10973 if (sizeflag & DFLAG)
10974 *ins->obufp++ = 'l';
10975 else
10976 *ins->obufp++ = 'w';
10977 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10978 }
10979 break;
10980 }
10981
10982 if (len == l)
10983 len = l = 0;
10984 }
10985 *ins->obufp = 0;
10986 ins->mnemonicendp = ins->obufp;
10987 return 0;
10988 }
10989
10990 /* Add a style marker to *INS->obufp that encodes STYLE. This assumes that
10991 the buffer pointed to by INS->obufp has space. A style marker is made
10992 from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
10993 digit, followed by another STYLE_MARKER_CHAR. This function assumes
10994 that the number of styles is not greater than 16. */
10995
10996 static void
oappend_insert_style(instr_info * ins,enum disassembler_style style)10997 oappend_insert_style (instr_info *ins, enum disassembler_style style)
10998 {
10999 unsigned num = (unsigned) style;
11000
11001 /* We currently assume that STYLE can be encoded as a single hex
11002 character. If more styles are added then this might start to fail,
11003 and we'll need to expand this code. */
11004 if (num > 0xf)
11005 abort ();
11006
11007 *ins->obufp++ = STYLE_MARKER_CHAR;
11008 *ins->obufp++ = (num < 10 ? ('0' + num)
11009 : ((num < 16) ? ('a' + (num - 10)) : '0'));
11010 *ins->obufp++ = STYLE_MARKER_CHAR;
11011
11012 /* This final null character is not strictly necessary, after inserting a
11013 style marker we should always be inserting some additional content.
11014 However, having the buffer null terminated doesn't cost much, and make
11015 it easier to debug what's going on. Also, if we do ever forget to add
11016 any additional content after this style marker, then the buffer will
11017 still be well formed. */
11018 *ins->obufp = '\0';
11019 }
11020
11021 static void
oappend_with_style(instr_info * ins,const char * s,enum disassembler_style style)11022 oappend_with_style (instr_info *ins, const char *s,
11023 enum disassembler_style style)
11024 {
11025 oappend_insert_style (ins, style);
11026 ins->obufp = stpcpy (ins->obufp, s);
11027 }
11028
11029 /* Add a single character C to the buffer pointer to by INS->obufp, marking
11030 the style for the character as STYLE. */
11031
11032 static void
oappend_char_with_style(instr_info * ins,const char c,enum disassembler_style style)11033 oappend_char_with_style (instr_info *ins, const char c,
11034 enum disassembler_style style)
11035 {
11036 oappend_insert_style (ins, style);
11037 *ins->obufp++ = c;
11038 *ins->obufp = '\0';
11039 }
11040
11041 /* Like oappend_char_with_style, but always uses dis_style_text. */
11042
11043 static void
oappend_char(instr_info * ins,const char c)11044 oappend_char (instr_info *ins, const char c)
11045 {
11046 oappend_char_with_style (ins, c, dis_style_text);
11047 }
11048
11049 static void
append_seg(instr_info * ins)11050 append_seg (instr_info *ins)
11051 {
11052 /* Only print the active segment register. */
11053 if (!ins->active_seg_prefix)
11054 return;
11055
11056 ins->used_prefixes |= ins->active_seg_prefix;
11057 switch (ins->active_seg_prefix)
11058 {
11059 case PREFIX_CS:
11060 oappend_register (ins, att_names_seg[1]);
11061 break;
11062 case PREFIX_DS:
11063 oappend_register (ins, att_names_seg[3]);
11064 break;
11065 case PREFIX_SS:
11066 oappend_register (ins, att_names_seg[2]);
11067 break;
11068 case PREFIX_ES:
11069 oappend_register (ins, att_names_seg[0]);
11070 break;
11071 case PREFIX_FS:
11072 oappend_register (ins, att_names_seg[4]);
11073 break;
11074 case PREFIX_GS:
11075 oappend_register (ins, att_names_seg[5]);
11076 break;
11077 default:
11078 break;
11079 }
11080 oappend_char (ins, ':');
11081 }
11082
11083 static void
print_operand_value(instr_info * ins,bfd_vma disp,enum disassembler_style style)11084 print_operand_value (instr_info *ins, bfd_vma disp,
11085 enum disassembler_style style)
11086 {
11087 char tmp[30];
11088
11089 if (ins->address_mode != mode_64bit)
11090 disp &= 0xffffffff;
11091 sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11092 oappend_with_style (ins, tmp, style);
11093 }
11094
11095 /* Like oappend, but called for immediate operands. */
11096
11097 static void
oappend_immediate(instr_info * ins,bfd_vma imm)11098 oappend_immediate (instr_info *ins, bfd_vma imm)
11099 {
11100 if (!ins->intel_syntax)
11101 oappend_char_with_style (ins, '$', dis_style_immediate);
11102 print_operand_value (ins, imm, dis_style_immediate);
11103 }
11104
11105 /* Put DISP in BUF as signed hex number. */
11106
11107 static void
print_displacement(instr_info * ins,bfd_signed_vma val)11108 print_displacement (instr_info *ins, bfd_signed_vma val)
11109 {
11110 char tmp[30];
11111
11112 if (val < 0)
11113 {
11114 oappend_char_with_style (ins, '-', dis_style_address_offset);
11115 val = (bfd_vma) 0 - val;
11116
11117 /* Check for possible overflow. */
11118 if (val < 0)
11119 {
11120 switch (ins->address_mode)
11121 {
11122 case mode_64bit:
11123 oappend_with_style (ins, "0x8000000000000000",
11124 dis_style_address_offset);
11125 break;
11126 case mode_32bit:
11127 oappend_with_style (ins, "0x80000000",
11128 dis_style_address_offset);
11129 break;
11130 case mode_16bit:
11131 oappend_with_style (ins, "0x8000",
11132 dis_style_address_offset);
11133 break;
11134 }
11135 return;
11136 }
11137 }
11138
11139 sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11140 oappend_with_style (ins, tmp, dis_style_address_offset);
11141 }
11142
11143 static void
intel_operand_size(instr_info * ins,int bytemode,int sizeflag)11144 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11145 {
11146 /* Check if there is a broadcast, when evex.b is not treated as evex.nd. */
11147 if (ins->vex.b && ins->evex_type == evex_default)
11148 {
11149 if (!ins->vex.no_broadcast)
11150 switch (bytemode)
11151 {
11152 case x_mode:
11153 case evex_half_bcst_xmmq_mode:
11154 if (ins->vex.w)
11155 oappend (ins, "QWORD BCST ");
11156 else
11157 oappend (ins, "DWORD BCST ");
11158 break;
11159 case xh_mode:
11160 case evex_half_bcst_xmmqh_mode:
11161 case evex_half_bcst_xmmqdh_mode:
11162 oappend (ins, "WORD BCST ");
11163 break;
11164 default:
11165 ins->vex.no_broadcast = true;
11166 break;
11167 }
11168 return;
11169 }
11170 switch (bytemode)
11171 {
11172 case b_mode:
11173 case b_swap_mode:
11174 case db_mode:
11175 oappend (ins, "BYTE PTR ");
11176 break;
11177 case w_mode:
11178 case w_swap_mode:
11179 case dw_mode:
11180 oappend (ins, "WORD PTR ");
11181 break;
11182 case indir_v_mode:
11183 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11184 {
11185 oappend (ins, "QWORD PTR ");
11186 break;
11187 }
11188 /* Fall through. */
11189 case stack_v_mode:
11190 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11191 || (ins->rex & REX_W)))
11192 {
11193 oappend (ins, "QWORD PTR ");
11194 break;
11195 }
11196 /* Fall through. */
11197 case v_mode:
11198 case v_swap_mode:
11199 case dq_mode:
11200 USED_REX (REX_W);
11201 if (ins->rex & REX_W)
11202 oappend (ins, "QWORD PTR ");
11203 else if (bytemode == dq_mode)
11204 oappend (ins, "DWORD PTR ");
11205 else
11206 {
11207 if (sizeflag & DFLAG)
11208 oappend (ins, "DWORD PTR ");
11209 else
11210 oappend (ins, "WORD PTR ");
11211 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11212 }
11213 break;
11214 case z_mode:
11215 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11216 *ins->obufp++ = 'D';
11217 oappend (ins, "WORD PTR ");
11218 if (!(ins->rex & REX_W))
11219 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11220 break;
11221 case a_mode:
11222 if (sizeflag & DFLAG)
11223 oappend (ins, "QWORD PTR ");
11224 else
11225 oappend (ins, "DWORD PTR ");
11226 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11227 break;
11228 case movsxd_mode:
11229 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11230 oappend (ins, "WORD PTR ");
11231 else
11232 oappend (ins, "DWORD PTR ");
11233 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11234 break;
11235 case d_mode:
11236 case d_swap_mode:
11237 oappend (ins, "DWORD PTR ");
11238 break;
11239 case q_mode:
11240 case q_swap_mode:
11241 oappend (ins, "QWORD PTR ");
11242 break;
11243 case m_mode:
11244 if (ins->address_mode == mode_64bit)
11245 oappend (ins, "QWORD PTR ");
11246 else
11247 oappend (ins, "DWORD PTR ");
11248 break;
11249 case f_mode:
11250 if (sizeflag & DFLAG)
11251 oappend (ins, "FWORD PTR ");
11252 else
11253 oappend (ins, "DWORD PTR ");
11254 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11255 break;
11256 case t_mode:
11257 oappend (ins, "TBYTE PTR ");
11258 break;
11259 case x_mode:
11260 case xh_mode:
11261 case x_swap_mode:
11262 case evex_x_gscat_mode:
11263 case evex_x_nobcst_mode:
11264 case bw_unit_mode:
11265 if (ins->need_vex)
11266 {
11267 switch (ins->vex.length)
11268 {
11269 case 128:
11270 oappend (ins, "XMMWORD PTR ");
11271 break;
11272 case 256:
11273 oappend (ins, "YMMWORD PTR ");
11274 break;
11275 case 512:
11276 oappend (ins, "ZMMWORD PTR ");
11277 break;
11278 default:
11279 abort ();
11280 }
11281 }
11282 else
11283 oappend (ins, "XMMWORD PTR ");
11284 break;
11285 case xmm_mode:
11286 oappend (ins, "XMMWORD PTR ");
11287 break;
11288 case ymm_mode:
11289 oappend (ins, "YMMWORD PTR ");
11290 break;
11291 case xmmq_mode:
11292 case evex_half_bcst_xmmqh_mode:
11293 case evex_half_bcst_xmmq_mode:
11294 switch (ins->vex.length)
11295 {
11296 case 0:
11297 case 128:
11298 oappend (ins, "QWORD PTR ");
11299 break;
11300 case 256:
11301 oappend (ins, "XMMWORD PTR ");
11302 break;
11303 case 512:
11304 oappend (ins, "YMMWORD PTR ");
11305 break;
11306 default:
11307 abort ();
11308 }
11309 break;
11310 case xmmdw_mode:
11311 if (!ins->need_vex)
11312 abort ();
11313
11314 switch (ins->vex.length)
11315 {
11316 case 128:
11317 oappend (ins, "WORD PTR ");
11318 break;
11319 case 256:
11320 oappend (ins, "DWORD PTR ");
11321 break;
11322 case 512:
11323 oappend (ins, "QWORD PTR ");
11324 break;
11325 default:
11326 abort ();
11327 }
11328 break;
11329 case xmmqd_mode:
11330 case evex_half_bcst_xmmqdh_mode:
11331 if (!ins->need_vex)
11332 abort ();
11333
11334 switch (ins->vex.length)
11335 {
11336 case 128:
11337 oappend (ins, "DWORD PTR ");
11338 break;
11339 case 256:
11340 oappend (ins, "QWORD PTR ");
11341 break;
11342 case 512:
11343 oappend (ins, "XMMWORD PTR ");
11344 break;
11345 default:
11346 abort ();
11347 }
11348 break;
11349 case ymmq_mode:
11350 if (!ins->need_vex)
11351 abort ();
11352
11353 switch (ins->vex.length)
11354 {
11355 case 128:
11356 oappend (ins, "QWORD PTR ");
11357 break;
11358 case 256:
11359 oappend (ins, "YMMWORD PTR ");
11360 break;
11361 case 512:
11362 oappend (ins, "ZMMWORD PTR ");
11363 break;
11364 default:
11365 abort ();
11366 }
11367 break;
11368 case o_mode:
11369 oappend (ins, "OWORD PTR ");
11370 break;
11371 case vex_vsib_d_w_dq_mode:
11372 case vex_vsib_q_w_dq_mode:
11373 if (!ins->need_vex)
11374 abort ();
11375 if (ins->vex.w)
11376 oappend (ins, "QWORD PTR ");
11377 else
11378 oappend (ins, "DWORD PTR ");
11379 break;
11380 case mask_bd_mode:
11381 if (!ins->need_vex || ins->vex.length != 128)
11382 abort ();
11383 if (ins->vex.w)
11384 oappend (ins, "DWORD PTR ");
11385 else
11386 oappend (ins, "BYTE PTR ");
11387 break;
11388 case mask_mode:
11389 if (!ins->need_vex)
11390 abort ();
11391 if (ins->vex.w)
11392 oappend (ins, "QWORD PTR ");
11393 else
11394 oappend (ins, "WORD PTR ");
11395 break;
11396 case v_bnd_mode:
11397 case v_bndmk_mode:
11398 default:
11399 break;
11400 }
11401 }
11402
11403 static void
print_register(instr_info * ins,unsigned int reg,unsigned int rexmask,int bytemode,int sizeflag)11404 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11405 int bytemode, int sizeflag)
11406 {
11407 const char (*names)[8];
11408
11409 /* Masking is invalid for insns with GPR destination. Set the flag uniformly,
11410 as the consumer will inspect it only for the destination operand. */
11411 if (bytemode != mask_mode && ins->vex.mask_register_specifier)
11412 ins->illegal_masking = true;
11413
11414 USED_REX (rexmask);
11415 if (ins->rex & rexmask)
11416 reg += 8;
11417 if (ins->rex2 & rexmask)
11418 reg += 16;
11419
11420 switch (bytemode)
11421 {
11422 case b_mode:
11423 case b_swap_mode:
11424 if (reg & 4)
11425 USED_REX (0);
11426 if (ins->rex || ins->rex2)
11427 names = att_names8rex;
11428 else
11429 names = att_names8;
11430 break;
11431 case w_mode:
11432 names = att_names16;
11433 break;
11434 case d_mode:
11435 case dw_mode:
11436 case db_mode:
11437 names = att_names32;
11438 break;
11439 case q_mode:
11440 names = att_names64;
11441 break;
11442 case m_mode:
11443 case v_bnd_mode:
11444 names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11445 break;
11446 case bnd_mode:
11447 case bnd_swap_mode:
11448 if (reg > 0x3)
11449 {
11450 oappend (ins, "(bad)");
11451 return;
11452 }
11453 names = att_names_bnd;
11454 break;
11455 case indir_v_mode:
11456 if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11457 {
11458 names = att_names64;
11459 break;
11460 }
11461 /* Fall through. */
11462 case stack_v_mode:
11463 if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11464 || (ins->rex & REX_W)))
11465 {
11466 names = att_names64;
11467 break;
11468 }
11469 bytemode = v_mode;
11470 /* Fall through. */
11471 case v_mode:
11472 case v_swap_mode:
11473 case dq_mode:
11474 USED_REX (REX_W);
11475 if (ins->rex & REX_W)
11476 names = att_names64;
11477 else if (bytemode != v_mode && bytemode != v_swap_mode)
11478 names = att_names32;
11479 else
11480 {
11481 if (sizeflag & DFLAG)
11482 names = att_names32;
11483 else
11484 names = att_names16;
11485 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11486 }
11487 break;
11488 case movsxd_mode:
11489 if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11490 names = att_names16;
11491 else
11492 names = att_names32;
11493 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11494 break;
11495 case va_mode:
11496 names = (ins->address_mode == mode_64bit
11497 ? att_names64 : att_names32);
11498 if (!(ins->prefixes & PREFIX_ADDR))
11499 names = (ins->address_mode == mode_16bit
11500 ? att_names16 : names);
11501 else
11502 {
11503 /* Remove "addr16/addr32". */
11504 ins->all_prefixes[ins->last_addr_prefix] = 0;
11505 names = (ins->address_mode != mode_32bit
11506 ? att_names32 : att_names16);
11507 ins->used_prefixes |= PREFIX_ADDR;
11508 }
11509 break;
11510 case mask_bd_mode:
11511 case mask_mode:
11512 if (reg > 0x7)
11513 {
11514 oappend (ins, "(bad)");
11515 return;
11516 }
11517 names = att_names_mask;
11518 break;
11519 case 0:
11520 return;
11521 default:
11522 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11523 return;
11524 }
11525 oappend_register (ins, names[reg]);
11526 }
11527
11528 static bool
get8s(instr_info * ins,bfd_vma * res)11529 get8s (instr_info *ins, bfd_vma *res)
11530 {
11531 if (!fetch_code (ins->info, ins->codep + 1))
11532 return false;
11533 *res = ((bfd_vma) *ins->codep++ ^ 0x80) - 0x80;
11534 return true;
11535 }
11536
11537 static bool
get16(instr_info * ins,bfd_vma * res)11538 get16 (instr_info *ins, bfd_vma *res)
11539 {
11540 if (!fetch_code (ins->info, ins->codep + 2))
11541 return false;
11542 *res = *ins->codep++;
11543 *res |= (bfd_vma) *ins->codep++ << 8;
11544 return true;
11545 }
11546
11547 static bool
get16s(instr_info * ins,bfd_vma * res)11548 get16s (instr_info *ins, bfd_vma *res)
11549 {
11550 if (!get16 (ins, res))
11551 return false;
11552 *res = (*res ^ 0x8000) - 0x8000;
11553 return true;
11554 }
11555
11556 static bool
get32(instr_info * ins,bfd_vma * res)11557 get32 (instr_info *ins, bfd_vma *res)
11558 {
11559 if (!fetch_code (ins->info, ins->codep + 4))
11560 return false;
11561 *res = *ins->codep++;
11562 *res |= (bfd_vma) *ins->codep++ << 8;
11563 *res |= (bfd_vma) *ins->codep++ << 16;
11564 *res |= (bfd_vma) *ins->codep++ << 24;
11565 return true;
11566 }
11567
11568 static bool
get32s(instr_info * ins,bfd_vma * res)11569 get32s (instr_info *ins, bfd_vma *res)
11570 {
11571 if (!get32 (ins, res))
11572 return false;
11573
11574 *res = (*res ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
11575
11576 return true;
11577 }
11578
11579 static bool
get64(instr_info * ins,uint64_t * res)11580 get64 (instr_info *ins, uint64_t *res)
11581 {
11582 unsigned int a;
11583 unsigned int b;
11584
11585 if (!fetch_code (ins->info, ins->codep + 8))
11586 return false;
11587 a = *ins->codep++;
11588 a |= (unsigned int) *ins->codep++ << 8;
11589 a |= (unsigned int) *ins->codep++ << 16;
11590 a |= (unsigned int) *ins->codep++ << 24;
11591 b = *ins->codep++;
11592 b |= (unsigned int) *ins->codep++ << 8;
11593 b |= (unsigned int) *ins->codep++ << 16;
11594 b |= (unsigned int) *ins->codep++ << 24;
11595 *res = a + ((uint64_t) b << 32);
11596 return true;
11597 }
11598
11599 static void
set_op(instr_info * ins,bfd_vma op,bool riprel)11600 set_op (instr_info *ins, bfd_vma op, bool riprel)
11601 {
11602 ins->op_index[ins->op_ad] = ins->op_ad;
11603 if (ins->address_mode == mode_64bit)
11604 ins->op_address[ins->op_ad] = op;
11605 else /* Mask to get a 32-bit address. */
11606 ins->op_address[ins->op_ad] = op & 0xffffffff;
11607 ins->op_riprel[ins->op_ad] = riprel;
11608 }
11609
11610 static bool
BadOp(instr_info * ins)11611 BadOp (instr_info *ins)
11612 {
11613 /* Throw away prefixes and 1st. opcode byte. */
11614 struct dis_private *priv = ins->info->private_data;
11615
11616 ins->codep = priv->the_buffer + ins->nr_prefixes + ins->need_vex + 1;
11617 ins->obufp = stpcpy (ins->obufp, "(bad)");
11618 return true;
11619 }
11620
11621 static bool
OP_Skip_MODRM(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)11622 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
11623 int sizeflag ATTRIBUTE_UNUSED)
11624 {
11625 if (ins->modrm.mod != 3)
11626 return BadOp (ins);
11627
11628 /* Skip mod/rm byte. */
11629 MODRM_CHECK;
11630 ins->codep++;
11631 ins->has_skipped_modrm = true;
11632 return true;
11633 }
11634
11635 static bool
OP_E_memory(instr_info * ins,int bytemode,int sizeflag)11636 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11637 {
11638 int add = (ins->rex & REX_B) ? 8 : 0;
11639 int riprel = 0;
11640 int shift;
11641
11642 add += (ins->rex2 & REX_B) ? 16 : 0;
11643
11644 /* Handles EVEX other than APX EVEX-promoted instructions. */
11645 if (ins->vex.evex && ins->evex_type == evex_default)
11646 {
11647
11648 /* Zeroing-masking is invalid for memory destinations. Set the flag
11649 uniformly, as the consumer will inspect it only for the destination
11650 operand. */
11651 if (ins->vex.zeroing)
11652 ins->illegal_masking = true;
11653
11654 switch (bytemode)
11655 {
11656 case dw_mode:
11657 case w_mode:
11658 case w_swap_mode:
11659 shift = 1;
11660 break;
11661 case db_mode:
11662 case b_mode:
11663 shift = 0;
11664 break;
11665 case dq_mode:
11666 if (ins->address_mode != mode_64bit)
11667 {
11668 case d_mode:
11669 case d_swap_mode:
11670 shift = 2;
11671 break;
11672 }
11673 /* fall through */
11674 case vex_vsib_d_w_dq_mode:
11675 case vex_vsib_q_w_dq_mode:
11676 case evex_x_gscat_mode:
11677 shift = ins->vex.w ? 3 : 2;
11678 break;
11679 case xh_mode:
11680 case evex_half_bcst_xmmqh_mode:
11681 case evex_half_bcst_xmmqdh_mode:
11682 if (ins->vex.b)
11683 {
11684 shift = ins->vex.w ? 2 : 1;
11685 break;
11686 }
11687 /* Fall through. */
11688 case x_mode:
11689 case evex_half_bcst_xmmq_mode:
11690 if (ins->vex.b)
11691 {
11692 shift = ins->vex.w ? 3 : 2;
11693 break;
11694 }
11695 /* Fall through. */
11696 case xmmqd_mode:
11697 case xmmdw_mode:
11698 case xmmq_mode:
11699 case ymmq_mode:
11700 case evex_x_nobcst_mode:
11701 case x_swap_mode:
11702 switch (ins->vex.length)
11703 {
11704 case 128:
11705 shift = 4;
11706 break;
11707 case 256:
11708 shift = 5;
11709 break;
11710 case 512:
11711 shift = 6;
11712 break;
11713 default:
11714 abort ();
11715 }
11716 /* Make necessary corrections to shift for modes that need it. */
11717 if (bytemode == xmmq_mode
11718 || bytemode == evex_half_bcst_xmmqh_mode
11719 || bytemode == evex_half_bcst_xmmq_mode
11720 || (bytemode == ymmq_mode && ins->vex.length == 128))
11721 shift -= 1;
11722 else if (bytemode == xmmqd_mode
11723 || bytemode == evex_half_bcst_xmmqdh_mode)
11724 shift -= 2;
11725 else if (bytemode == xmmdw_mode)
11726 shift -= 3;
11727 break;
11728 case ymm_mode:
11729 shift = 5;
11730 break;
11731 case xmm_mode:
11732 shift = 4;
11733 break;
11734 case q_mode:
11735 case q_swap_mode:
11736 shift = 3;
11737 break;
11738 case bw_unit_mode:
11739 shift = ins->vex.w ? 1 : 0;
11740 break;
11741 default:
11742 abort ();
11743 }
11744 }
11745 else
11746 shift = 0;
11747
11748 USED_REX (REX_B);
11749 if (ins->intel_syntax)
11750 intel_operand_size (ins, bytemode, sizeflag);
11751 append_seg (ins);
11752
11753 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11754 {
11755 /* 32/64 bit address mode */
11756 bfd_vma disp = 0;
11757 int havedisp;
11758 int havebase;
11759 int needindex;
11760 int needaddr32;
11761 int base, rbase;
11762 int vindex = 0;
11763 int scale = 0;
11764 int addr32flag = !((sizeflag & AFLAG)
11765 || bytemode == v_bnd_mode
11766 || bytemode == v_bndmk_mode
11767 || bytemode == bnd_mode
11768 || bytemode == bnd_swap_mode);
11769 bool check_gather = false;
11770 const char (*indexes)[8] = NULL;
11771
11772 havebase = 1;
11773 base = ins->modrm.rm;
11774
11775 if (base == 4)
11776 {
11777 vindex = ins->sib.index;
11778 USED_REX (REX_X);
11779 if (ins->rex & REX_X)
11780 vindex += 8;
11781 switch (bytemode)
11782 {
11783 case vex_vsib_d_w_dq_mode:
11784 case vex_vsib_q_w_dq_mode:
11785 if (!ins->need_vex)
11786 abort ();
11787 if (ins->vex.evex)
11788 {
11789 /* S/G EVEX insns require EVEX.X4 not to be set. */
11790 if (ins->rex2 & REX_X)
11791 {
11792 oappend (ins, "(bad)");
11793 return true;
11794 }
11795
11796 if (!ins->vex.v)
11797 vindex += 16;
11798 check_gather = ins->obufp == ins->op_out[1];
11799 }
11800
11801 switch (ins->vex.length)
11802 {
11803 case 128:
11804 indexes = att_names_xmm;
11805 break;
11806 case 256:
11807 if (!ins->vex.w
11808 || bytemode == vex_vsib_q_w_dq_mode)
11809 indexes = att_names_ymm;
11810 else
11811 indexes = att_names_xmm;
11812 break;
11813 case 512:
11814 if (!ins->vex.w
11815 || bytemode == vex_vsib_q_w_dq_mode)
11816 indexes = att_names_zmm;
11817 else
11818 indexes = att_names_ymm;
11819 break;
11820 default:
11821 abort ();
11822 }
11823 break;
11824 default:
11825 if (ins->rex2 & REX_X)
11826 vindex += 16;
11827
11828 if (vindex != 4)
11829 indexes = ins->address_mode == mode_64bit && !addr32flag
11830 ? att_names64 : att_names32;
11831 break;
11832 }
11833 scale = ins->sib.scale;
11834 base = ins->sib.base;
11835 ins->codep++;
11836 }
11837 else
11838 {
11839 /* Check for mandatory SIB. */
11840 if (bytemode == vex_vsib_d_w_dq_mode
11841 || bytemode == vex_vsib_q_w_dq_mode
11842 || bytemode == vex_sibmem_mode)
11843 {
11844 oappend (ins, "(bad)");
11845 return true;
11846 }
11847 }
11848 rbase = base + add;
11849
11850 switch (ins->modrm.mod)
11851 {
11852 case 0:
11853 if (base == 5)
11854 {
11855 havebase = 0;
11856 if (ins->address_mode == mode_64bit && !ins->has_sib)
11857 riprel = 1;
11858 if (!get32s (ins, &disp))
11859 return false;
11860 if (riprel && bytemode == v_bndmk_mode)
11861 {
11862 oappend (ins, "(bad)");
11863 return true;
11864 }
11865 }
11866 break;
11867 case 1:
11868 if (!get8s (ins, &disp))
11869 return false;
11870 if (ins->vex.evex && shift > 0)
11871 disp <<= shift;
11872 break;
11873 case 2:
11874 if (!get32s (ins, &disp))
11875 return false;
11876 break;
11877 }
11878
11879 needindex = 0;
11880 needaddr32 = 0;
11881 if (ins->has_sib
11882 && !havebase
11883 && !indexes
11884 && ins->address_mode != mode_16bit)
11885 {
11886 if (ins->address_mode == mode_64bit)
11887 {
11888 if (addr32flag)
11889 {
11890 /* Without base nor index registers, zero-extend the
11891 lower 32-bit displacement to 64 bits. */
11892 disp &= 0xffffffff;
11893 needindex = 1;
11894 }
11895 needaddr32 = 1;
11896 }
11897 else
11898 {
11899 /* In 32-bit mode, we need index register to tell [offset]
11900 from [eiz*1 + offset]. */
11901 needindex = 1;
11902 }
11903 }
11904
11905 havedisp = (havebase
11906 || needindex
11907 || (ins->has_sib && (indexes || scale != 0)));
11908
11909 if (!ins->intel_syntax)
11910 if (ins->modrm.mod != 0 || base == 5)
11911 {
11912 if (havedisp || riprel)
11913 print_displacement (ins, disp);
11914 else
11915 print_operand_value (ins, disp, dis_style_address_offset);
11916 if (riprel)
11917 {
11918 set_op (ins, disp, true);
11919 oappend_char (ins, '(');
11920 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
11921 dis_style_register);
11922 oappend_char (ins, ')');
11923 }
11924 }
11925
11926 if ((havebase || indexes || needindex || needaddr32 || riprel)
11927 && (ins->address_mode != mode_64bit
11928 || ((bytemode != v_bnd_mode)
11929 && (bytemode != v_bndmk_mode)
11930 && (bytemode != bnd_mode)
11931 && (bytemode != bnd_swap_mode))))
11932 ins->used_prefixes |= PREFIX_ADDR;
11933
11934 if (havedisp || (ins->intel_syntax && riprel))
11935 {
11936 oappend_char (ins, ins->open_char);
11937 if (ins->intel_syntax && riprel)
11938 {
11939 set_op (ins, disp, true);
11940 oappend_with_style (ins, !addr32flag ? "rip" : "eip",
11941 dis_style_register);
11942 }
11943 if (havebase)
11944 oappend_register
11945 (ins,
11946 (ins->address_mode == mode_64bit && !addr32flag
11947 ? att_names64 : att_names32)[rbase]);
11948 if (ins->has_sib)
11949 {
11950 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11951 print index to tell base + index from base. */
11952 if (scale != 0
11953 || needindex
11954 || indexes
11955 || (havebase && base != ESP_REG_NUM))
11956 {
11957 if (!ins->intel_syntax || havebase)
11958 oappend_char (ins, ins->separator_char);
11959 if (indexes)
11960 {
11961 if (ins->address_mode == mode_64bit || vindex < 16)
11962 oappend_register (ins, indexes[vindex]);
11963 else
11964 oappend (ins, "(bad)");
11965 }
11966 else
11967 oappend_register (ins,
11968 ins->address_mode == mode_64bit
11969 && !addr32flag
11970 ? att_index64
11971 : att_index32);
11972
11973 oappend_char (ins, ins->scale_char);
11974 oappend_char_with_style (ins, '0' + (1 << scale),
11975 dis_style_immediate);
11976 }
11977 }
11978 if (ins->intel_syntax
11979 && (disp || ins->modrm.mod != 0 || base == 5))
11980 {
11981 if (!havedisp || (bfd_signed_vma) disp >= 0)
11982 oappend_char (ins, '+');
11983 if (havedisp)
11984 print_displacement (ins, disp);
11985 else
11986 print_operand_value (ins, disp, dis_style_address_offset);
11987 }
11988
11989 oappend_char (ins, ins->close_char);
11990
11991 if (check_gather)
11992 {
11993 /* Both XMM/YMM/ZMM registers must be distinct. */
11994 int modrm_reg = ins->modrm.reg;
11995
11996 if (ins->rex & REX_R)
11997 modrm_reg += 8;
11998 if (ins->rex2 & REX_R)
11999 modrm_reg += 16;
12000 if (vindex == modrm_reg)
12001 oappend (ins, "/(bad)");
12002 }
12003 }
12004 else if (ins->intel_syntax)
12005 {
12006 if (ins->modrm.mod != 0 || base == 5)
12007 {
12008 if (!ins->active_seg_prefix)
12009 {
12010 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12011 oappend (ins, ":");
12012 }
12013 print_operand_value (ins, disp, dis_style_text);
12014 }
12015 }
12016 }
12017 else if (bytemode == v_bnd_mode
12018 || bytemode == v_bndmk_mode
12019 || bytemode == bnd_mode
12020 || bytemode == bnd_swap_mode
12021 || bytemode == vex_vsib_d_w_dq_mode
12022 || bytemode == vex_vsib_q_w_dq_mode)
12023 {
12024 oappend (ins, "(bad)");
12025 return true;
12026 }
12027 else
12028 {
12029 /* 16 bit address mode */
12030 bfd_vma disp = 0;
12031
12032 ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
12033 switch (ins->modrm.mod)
12034 {
12035 case 0:
12036 if (ins->modrm.rm == 6)
12037 {
12038 case 2:
12039 if (!get16s (ins, &disp))
12040 return false;
12041 }
12042 break;
12043 case 1:
12044 if (!get8s (ins, &disp))
12045 return false;
12046 if (ins->vex.evex && shift > 0)
12047 disp <<= shift;
12048 break;
12049 }
12050
12051 if (!ins->intel_syntax)
12052 if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
12053 print_displacement (ins, disp);
12054
12055 if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
12056 {
12057 oappend_char (ins, ins->open_char);
12058 oappend (ins, ins->intel_syntax ? intel_index16[ins->modrm.rm]
12059 : att_index16[ins->modrm.rm]);
12060 if (ins->intel_syntax
12061 && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
12062 {
12063 if ((bfd_signed_vma) disp >= 0)
12064 oappend_char (ins, '+');
12065 print_displacement (ins, disp);
12066 }
12067
12068 oappend_char (ins, ins->close_char);
12069 }
12070 else if (ins->intel_syntax)
12071 {
12072 if (!ins->active_seg_prefix)
12073 {
12074 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12075 oappend (ins, ":");
12076 }
12077 print_operand_value (ins, disp & 0xffff, dis_style_text);
12078 }
12079 }
12080 if (ins->vex.b && ins->evex_type == evex_default)
12081 {
12082 ins->evex_used |= EVEX_b_used;
12083
12084 /* Broadcast can only ever be valid for memory sources. */
12085 if (ins->obufp == ins->op_out[0])
12086 ins->vex.no_broadcast = true;
12087
12088 if (!ins->vex.no_broadcast
12089 && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
12090 {
12091 if (bytemode == xh_mode)
12092 {
12093 switch (ins->vex.length)
12094 {
12095 case 128:
12096 oappend (ins, "{1to8}");
12097 break;
12098 case 256:
12099 oappend (ins, "{1to16}");
12100 break;
12101 case 512:
12102 oappend (ins, "{1to32}");
12103 break;
12104 default:
12105 abort ();
12106 }
12107 }
12108 else if (bytemode == q_mode
12109 || bytemode == ymmq_mode)
12110 ins->vex.no_broadcast = true;
12111 else if (ins->vex.w
12112 || bytemode == evex_half_bcst_xmmqdh_mode
12113 || bytemode == evex_half_bcst_xmmq_mode)
12114 {
12115 switch (ins->vex.length)
12116 {
12117 case 128:
12118 oappend (ins, "{1to2}");
12119 break;
12120 case 256:
12121 oappend (ins, "{1to4}");
12122 break;
12123 case 512:
12124 oappend (ins, "{1to8}");
12125 break;
12126 default:
12127 abort ();
12128 }
12129 }
12130 else if (bytemode == x_mode
12131 || bytemode == evex_half_bcst_xmmqh_mode)
12132 {
12133 switch (ins->vex.length)
12134 {
12135 case 128:
12136 oappend (ins, "{1to4}");
12137 break;
12138 case 256:
12139 oappend (ins, "{1to8}");
12140 break;
12141 case 512:
12142 oappend (ins, "{1to16}");
12143 break;
12144 default:
12145 abort ();
12146 }
12147 }
12148 else
12149 ins->vex.no_broadcast = true;
12150 }
12151 if (ins->vex.no_broadcast)
12152 oappend (ins, "{bad}");
12153 }
12154
12155 return true;
12156 }
12157
12158 static bool
OP_E(instr_info * ins,int bytemode,int sizeflag)12159 OP_E (instr_info *ins, int bytemode, int sizeflag)
12160 {
12161 /* Skip mod/rm byte. */
12162 MODRM_CHECK;
12163 if (!ins->has_skipped_modrm)
12164 {
12165 ins->codep++;
12166 ins->has_skipped_modrm = true;
12167 }
12168
12169 if (ins->modrm.mod == 3)
12170 {
12171 if ((sizeflag & SUFFIX_ALWAYS)
12172 && (bytemode == b_swap_mode
12173 || bytemode == bnd_swap_mode
12174 || bytemode == v_swap_mode))
12175 swap_operand (ins);
12176
12177 print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12178 return true;
12179 }
12180
12181 /* Masking is invalid for insns with GPR-like memory destination. Set the
12182 flag uniformly, as the consumer will inspect it only for the destination
12183 operand. */
12184 if (ins->vex.mask_register_specifier)
12185 ins->illegal_masking = true;
12186
12187 return OP_E_memory (ins, bytemode, sizeflag);
12188 }
12189
12190 static bool
OP_indirE(instr_info * ins,int bytemode,int sizeflag)12191 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
12192 {
12193 if (ins->modrm.mod == 3 && bytemode == f_mode)
12194 /* bad lcall/ljmp */
12195 return BadOp (ins);
12196 if (!ins->intel_syntax)
12197 oappend (ins, "*");
12198 return OP_E (ins, bytemode, sizeflag);
12199 }
12200
12201 static bool
OP_G(instr_info * ins,int bytemode,int sizeflag)12202 OP_G (instr_info *ins, int bytemode, int sizeflag)
12203 {
12204 print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12205 return true;
12206 }
12207
12208 static bool
OP_REG(instr_info * ins,int code,int sizeflag)12209 OP_REG (instr_info *ins, int code, int sizeflag)
12210 {
12211 const char *s;
12212 int add = 0;
12213
12214 switch (code)
12215 {
12216 case es_reg: case ss_reg: case cs_reg:
12217 case ds_reg: case fs_reg: case gs_reg:
12218 oappend_register (ins, att_names_seg[code - es_reg]);
12219 return true;
12220 }
12221
12222 USED_REX (REX_B);
12223 if (ins->rex & REX_B)
12224 add = 8;
12225 if (ins->rex2 & REX_B)
12226 add += 16;
12227
12228 switch (code)
12229 {
12230 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12231 case sp_reg: case bp_reg: case si_reg: case di_reg:
12232 s = att_names16[code - ax_reg + add];
12233 break;
12234 case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12235 USED_REX (0);
12236 /* Fall through. */
12237 case al_reg: case cl_reg: case dl_reg: case bl_reg:
12238 if (ins->rex)
12239 s = att_names8rex[code - al_reg + add];
12240 else
12241 s = att_names8[code - al_reg];
12242 break;
12243 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12244 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12245 if (ins->address_mode == mode_64bit
12246 && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12247 {
12248 s = att_names64[code - rAX_reg + add];
12249 break;
12250 }
12251 code += eAX_reg - rAX_reg;
12252 /* Fall through. */
12253 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12254 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12255 USED_REX (REX_W);
12256 if (ins->rex & REX_W)
12257 s = att_names64[code - eAX_reg + add];
12258 else
12259 {
12260 if (sizeflag & DFLAG)
12261 s = att_names32[code - eAX_reg + add];
12262 else
12263 s = att_names16[code - eAX_reg + add];
12264 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12265 }
12266 break;
12267 default:
12268 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12269 return true;
12270 }
12271 oappend_register (ins, s);
12272 return true;
12273 }
12274
12275 static bool
OP_IMREG(instr_info * ins,int code,int sizeflag)12276 OP_IMREG (instr_info *ins, int code, int sizeflag)
12277 {
12278 const char *s;
12279
12280 switch (code)
12281 {
12282 case indir_dx_reg:
12283 if (!ins->intel_syntax)
12284 {
12285 oappend (ins, "(%dx)");
12286 return true;
12287 }
12288 s = att_names16[dx_reg - ax_reg];
12289 break;
12290 case al_reg: case cl_reg:
12291 s = att_names8[code - al_reg];
12292 break;
12293 case eAX_reg:
12294 USED_REX (REX_W);
12295 if (ins->rex & REX_W)
12296 {
12297 s = *att_names64;
12298 break;
12299 }
12300 /* Fall through. */
12301 case z_mode_ax_reg:
12302 if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12303 s = *att_names32;
12304 else
12305 s = *att_names16;
12306 if (!(ins->rex & REX_W))
12307 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12308 break;
12309 default:
12310 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12311 return true;
12312 }
12313 oappend_register (ins, s);
12314 return true;
12315 }
12316
12317 static bool
OP_I(instr_info * ins,int bytemode,int sizeflag)12318 OP_I (instr_info *ins, int bytemode, int sizeflag)
12319 {
12320 bfd_vma op;
12321
12322 switch (bytemode)
12323 {
12324 case b_mode:
12325 if (!fetch_code (ins->info, ins->codep + 1))
12326 return false;
12327 op = *ins->codep++;
12328 break;
12329 case v_mode:
12330 USED_REX (REX_W);
12331 if (ins->rex & REX_W)
12332 {
12333 if (!get32s (ins, &op))
12334 return false;
12335 }
12336 else
12337 {
12338 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12339 if (sizeflag & DFLAG)
12340 {
12341 case d_mode:
12342 if (!get32 (ins, &op))
12343 return false;
12344 }
12345 else
12346 {
12347 /* Fall through. */
12348 case w_mode:
12349 if (!get16 (ins, &op))
12350 return false;
12351 }
12352 }
12353 break;
12354 case const_1_mode:
12355 if (ins->intel_syntax)
12356 oappend (ins, "1");
12357 else
12358 oappend (ins, "$1");
12359 return true;
12360 default:
12361 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12362 return true;
12363 }
12364
12365 oappend_immediate (ins, op);
12366 return true;
12367 }
12368
12369 static bool
OP_I64(instr_info * ins,int bytemode,int sizeflag)12370 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12371 {
12372 uint64_t op;
12373
12374 if (bytemode != v_mode || ins->address_mode != mode_64bit
12375 || !(ins->rex & REX_W))
12376 return OP_I (ins, bytemode, sizeflag);
12377
12378 USED_REX (REX_W);
12379
12380 if (!get64 (ins, &op))
12381 return false;
12382
12383 oappend_immediate (ins, op);
12384 return true;
12385 }
12386
12387 static bool
OP_sI(instr_info * ins,int bytemode,int sizeflag)12388 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12389 {
12390 bfd_vma op;
12391
12392 switch (bytemode)
12393 {
12394 case b_mode:
12395 case b_T_mode:
12396 if (!get8s (ins, &op))
12397 return false;
12398 if (bytemode == b_T_mode)
12399 {
12400 if (ins->address_mode != mode_64bit
12401 || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12402 {
12403 /* The operand-size prefix is overridden by a REX prefix. */
12404 if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12405 op &= 0xffffffff;
12406 else
12407 op &= 0xffff;
12408 }
12409 }
12410 else
12411 {
12412 if (!(ins->rex & REX_W))
12413 {
12414 if (sizeflag & DFLAG)
12415 op &= 0xffffffff;
12416 else
12417 op &= 0xffff;
12418 }
12419 }
12420 break;
12421 case v_mode:
12422 /* The operand-size prefix is overridden by a REX prefix. */
12423 if (!(sizeflag & DFLAG) && !(ins->rex & REX_W))
12424 {
12425 if (!get16 (ins, &op))
12426 return false;
12427 }
12428 else if (!get32s (ins, &op))
12429 return false;
12430 break;
12431 default:
12432 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12433 return true;
12434 }
12435
12436 oappend_immediate (ins, op);
12437 return true;
12438 }
12439
12440 static bool
OP_J(instr_info * ins,int bytemode,int sizeflag)12441 OP_J (instr_info *ins, int bytemode, int sizeflag)
12442 {
12443 bfd_vma disp;
12444 bfd_vma mask = -1;
12445 bfd_vma segment = 0;
12446
12447 switch (bytemode)
12448 {
12449 case b_mode:
12450 if (!get8s (ins, &disp))
12451 return false;
12452 break;
12453 case v_mode:
12454 case dqw_mode:
12455 if ((sizeflag & DFLAG)
12456 || (ins->address_mode == mode_64bit
12457 && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12458 || (ins->rex & REX_W))))
12459 {
12460 if (!get32s (ins, &disp))
12461 return false;
12462 }
12463 else
12464 {
12465 if (!get16s (ins, &disp))
12466 return false;
12467 /* In 16bit mode, address is wrapped around at 64k within
12468 the same segment. Otherwise, a data16 prefix on a jump
12469 instruction means that the pc is masked to 16 bits after
12470 the displacement is added! */
12471 mask = 0xffff;
12472 if ((ins->prefixes & PREFIX_DATA) == 0)
12473 segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12474 & ~((bfd_vma) 0xffff));
12475 }
12476 if (ins->address_mode != mode_64bit
12477 || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12478 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12479 break;
12480 default:
12481 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12482 return true;
12483 }
12484 disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12485 | segment;
12486 set_op (ins, disp, false);
12487 print_operand_value (ins, disp, dis_style_text);
12488 return true;
12489 }
12490
12491 static bool
OP_SEG(instr_info * ins,int bytemode,int sizeflag)12492 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12493 {
12494 if (bytemode == w_mode)
12495 {
12496 oappend_register (ins, att_names_seg[ins->modrm.reg]);
12497 return true;
12498 }
12499 return OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12500 }
12501
12502 static bool
OP_DIR(instr_info * ins,int dummy ATTRIBUTE_UNUSED,int sizeflag)12503 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12504 {
12505 bfd_vma seg, offset;
12506 int res;
12507 char scratch[24];
12508
12509 if (sizeflag & DFLAG)
12510 {
12511 if (!get32 (ins, &offset))
12512 return false;;
12513 }
12514 else if (!get16 (ins, &offset))
12515 return false;
12516 if (!get16 (ins, &seg))
12517 return false;;
12518 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12519
12520 res = snprintf (scratch, ARRAY_SIZE (scratch),
12521 ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
12522 (unsigned) seg, (unsigned) offset);
12523 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12524 abort ();
12525 oappend (ins, scratch);
12526 return true;
12527 }
12528
12529 static bool
OP_OFF(instr_info * ins,int bytemode,int sizeflag)12530 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12531 {
12532 bfd_vma off;
12533
12534 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12535 intel_operand_size (ins, bytemode, sizeflag);
12536 append_seg (ins);
12537
12538 if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12539 {
12540 if (!get32 (ins, &off))
12541 return false;
12542 }
12543 else
12544 {
12545 if (!get16 (ins, &off))
12546 return false;
12547 }
12548
12549 if (ins->intel_syntax)
12550 {
12551 if (!ins->active_seg_prefix)
12552 {
12553 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12554 oappend (ins, ":");
12555 }
12556 }
12557 print_operand_value (ins, off, dis_style_address_offset);
12558 return true;
12559 }
12560
12561 static bool
OP_OFF64(instr_info * ins,int bytemode,int sizeflag)12562 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12563 {
12564 uint64_t off;
12565
12566 if (ins->address_mode != mode_64bit
12567 || (ins->prefixes & PREFIX_ADDR))
12568 return OP_OFF (ins, bytemode, sizeflag);
12569
12570 if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12571 intel_operand_size (ins, bytemode, sizeflag);
12572 append_seg (ins);
12573
12574 if (!get64 (ins, &off))
12575 return false;
12576
12577 if (ins->intel_syntax)
12578 {
12579 if (!ins->active_seg_prefix)
12580 {
12581 oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12582 oappend (ins, ":");
12583 }
12584 }
12585 print_operand_value (ins, off, dis_style_address_offset);
12586 return true;
12587 }
12588
12589 static void
ptr_reg(instr_info * ins,int code,int sizeflag)12590 ptr_reg (instr_info *ins, int code, int sizeflag)
12591 {
12592 const char *s;
12593
12594 *ins->obufp++ = ins->open_char;
12595 ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12596 if (ins->address_mode == mode_64bit)
12597 {
12598 if (!(sizeflag & AFLAG))
12599 s = att_names32[code - eAX_reg];
12600 else
12601 s = att_names64[code - eAX_reg];
12602 }
12603 else if (sizeflag & AFLAG)
12604 s = att_names32[code - eAX_reg];
12605 else
12606 s = att_names16[code - eAX_reg];
12607 oappend_register (ins, s);
12608 oappend_char (ins, ins->close_char);
12609 }
12610
12611 static bool
OP_ESreg(instr_info * ins,int code,int sizeflag)12612 OP_ESreg (instr_info *ins, int code, int sizeflag)
12613 {
12614 if (ins->intel_syntax)
12615 {
12616 switch (ins->codep[-1])
12617 {
12618 case 0x6d: /* insw/insl */
12619 intel_operand_size (ins, z_mode, sizeflag);
12620 break;
12621 case 0xa5: /* movsw/movsl/movsq */
12622 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12623 case 0xab: /* stosw/stosl */
12624 case 0xaf: /* scasw/scasl */
12625 intel_operand_size (ins, v_mode, sizeflag);
12626 break;
12627 default:
12628 intel_operand_size (ins, b_mode, sizeflag);
12629 }
12630 }
12631 oappend_register (ins, att_names_seg[0]);
12632 oappend_char (ins, ':');
12633 ptr_reg (ins, code, sizeflag);
12634 return true;
12635 }
12636
12637 static bool
OP_DSreg(instr_info * ins,int code,int sizeflag)12638 OP_DSreg (instr_info *ins, int code, int sizeflag)
12639 {
12640 if (ins->intel_syntax)
12641 {
12642 switch (ins->codep[-1])
12643 {
12644 case 0x6f: /* outsw/outsl */
12645 intel_operand_size (ins, z_mode, sizeflag);
12646 break;
12647 case 0xa5: /* movsw/movsl/movsq */
12648 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12649 case 0xad: /* lodsw/lodsl/lodsq */
12650 intel_operand_size (ins, v_mode, sizeflag);
12651 break;
12652 default:
12653 intel_operand_size (ins, b_mode, sizeflag);
12654 }
12655 }
12656 /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12657 default segment register DS is printed. */
12658 if (!ins->active_seg_prefix)
12659 ins->active_seg_prefix = PREFIX_DS;
12660 append_seg (ins);
12661 ptr_reg (ins, code, sizeflag);
12662 return true;
12663 }
12664
12665 static bool
OP_C(instr_info * ins,int dummy ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12666 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12667 int sizeflag ATTRIBUTE_UNUSED)
12668 {
12669 int add, res;
12670 char scratch[8];
12671
12672 if (ins->rex & REX_R)
12673 {
12674 USED_REX (REX_R);
12675 add = 8;
12676 }
12677 else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12678 {
12679 ins->all_prefixes[ins->last_lock_prefix] = 0;
12680 ins->used_prefixes |= PREFIX_LOCK;
12681 add = 8;
12682 }
12683 else
12684 add = 0;
12685 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
12686 ins->modrm.reg + add);
12687 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12688 abort ();
12689 oappend_register (ins, scratch);
12690 return true;
12691 }
12692
12693 static bool
OP_D(instr_info * ins,int dummy ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12694 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12695 int sizeflag ATTRIBUTE_UNUSED)
12696 {
12697 int add, res;
12698 char scratch[8];
12699
12700 USED_REX (REX_R);
12701 if (ins->rex & REX_R)
12702 add = 8;
12703 else
12704 add = 0;
12705 res = snprintf (scratch, ARRAY_SIZE (scratch),
12706 ins->intel_syntax ? "dr%d" : "%%db%d",
12707 ins->modrm.reg + add);
12708 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12709 abort ();
12710 oappend (ins, scratch);
12711 return true;
12712 }
12713
12714 static bool
OP_T(instr_info * ins,int dummy ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12715 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12716 int sizeflag ATTRIBUTE_UNUSED)
12717 {
12718 int res;
12719 char scratch[8];
12720
12721 res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
12722 if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12723 abort ();
12724 oappend_register (ins, scratch);
12725 return true;
12726 }
12727
12728 static bool
OP_MMX(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12729 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12730 int sizeflag ATTRIBUTE_UNUSED)
12731 {
12732 int reg = ins->modrm.reg;
12733 const char (*names)[8];
12734
12735 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12736 if (ins->prefixes & PREFIX_DATA)
12737 {
12738 names = att_names_xmm;
12739 USED_REX (REX_R);
12740 if (ins->rex & REX_R)
12741 reg += 8;
12742 }
12743 else
12744 names = att_names_mm;
12745 oappend_register (ins, names[reg]);
12746 return true;
12747 }
12748
12749 static void
print_vector_reg(instr_info * ins,unsigned int reg,int bytemode)12750 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12751 {
12752 const char (*names)[8];
12753
12754 if (bytemode == xmmq_mode
12755 || bytemode == evex_half_bcst_xmmqh_mode
12756 || bytemode == evex_half_bcst_xmmq_mode)
12757 {
12758 switch (ins->vex.length)
12759 {
12760 case 0:
12761 case 128:
12762 case 256:
12763 names = att_names_xmm;
12764 break;
12765 case 512:
12766 names = att_names_ymm;
12767 ins->evex_used |= EVEX_len_used;
12768 break;
12769 default:
12770 abort ();
12771 }
12772 }
12773 else if (bytemode == ymm_mode)
12774 names = att_names_ymm;
12775 else if (bytemode == tmm_mode)
12776 {
12777 if (reg >= 8)
12778 {
12779 oappend (ins, "(bad)");
12780 return;
12781 }
12782 names = att_names_tmm;
12783 }
12784 else if (ins->need_vex
12785 && bytemode != xmm_mode
12786 && bytemode != scalar_mode
12787 && bytemode != xmmdw_mode
12788 && bytemode != xmmqd_mode
12789 && bytemode != evex_half_bcst_xmmqdh_mode
12790 && bytemode != w_swap_mode
12791 && bytemode != b_mode
12792 && bytemode != w_mode
12793 && bytemode != d_mode
12794 && bytemode != q_mode)
12795 {
12796 ins->evex_used |= EVEX_len_used;
12797 switch (ins->vex.length)
12798 {
12799 case 128:
12800 names = att_names_xmm;
12801 break;
12802 case 256:
12803 if (ins->vex.w
12804 || bytemode != vex_vsib_q_w_dq_mode)
12805 names = att_names_ymm;
12806 else
12807 names = att_names_xmm;
12808 break;
12809 case 512:
12810 if (ins->vex.w
12811 || bytemode != vex_vsib_q_w_dq_mode)
12812 names = att_names_zmm;
12813 else
12814 names = att_names_ymm;
12815 break;
12816 default:
12817 abort ();
12818 }
12819 }
12820 else
12821 names = att_names_xmm;
12822 oappend_register (ins, names[reg]);
12823 }
12824
12825 static bool
OP_XMM(instr_info * ins,int bytemode,int sizeflag ATTRIBUTE_UNUSED)12826 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12827 {
12828 unsigned int reg = ins->modrm.reg;
12829
12830 USED_REX (REX_R);
12831 if (ins->rex & REX_R)
12832 reg += 8;
12833 if (ins->vex.evex)
12834 {
12835 if (ins->rex2 & REX_R)
12836 reg += 16;
12837 }
12838
12839 if (bytemode == tmm_mode)
12840 ins->modrm.reg = reg;
12841 else if (bytemode == scalar_mode)
12842 ins->vex.no_broadcast = true;
12843
12844 print_vector_reg (ins, reg, bytemode);
12845 return true;
12846 }
12847
12848 static bool
OP_EM(instr_info * ins,int bytemode,int sizeflag)12849 OP_EM (instr_info *ins, int bytemode, int sizeflag)
12850 {
12851 int reg;
12852 const char (*names)[8];
12853
12854 if (ins->modrm.mod != 3)
12855 {
12856 if (ins->intel_syntax
12857 && (bytemode == v_mode || bytemode == v_swap_mode))
12858 {
12859 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12860 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12861 }
12862 return OP_E (ins, bytemode, sizeflag);
12863 }
12864
12865 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12866 swap_operand (ins);
12867
12868 /* Skip mod/rm byte. */
12869 MODRM_CHECK;
12870 ins->codep++;
12871 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12872 reg = ins->modrm.rm;
12873 if (ins->prefixes & PREFIX_DATA)
12874 {
12875 names = att_names_xmm;
12876 USED_REX (REX_B);
12877 if (ins->rex & REX_B)
12878 reg += 8;
12879 }
12880 else
12881 names = att_names_mm;
12882 oappend_register (ins, names[reg]);
12883 return true;
12884 }
12885
12886 /* cvt* are the only instructions in sse2 which have
12887 both SSE and MMX operands and also have 0x66 prefix
12888 in their opcode. 0x66 was originally used to differentiate
12889 between SSE and MMX instruction(operands). So we have to handle the
12890 cvt* separately using OP_EMC and OP_MXC */
12891 static bool
OP_EMC(instr_info * ins,int bytemode,int sizeflag)12892 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
12893 {
12894 if (ins->modrm.mod != 3)
12895 {
12896 if (ins->intel_syntax && bytemode == v_mode)
12897 {
12898 bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12899 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12900 }
12901 return OP_E (ins, bytemode, sizeflag);
12902 }
12903
12904 /* Skip mod/rm byte. */
12905 MODRM_CHECK;
12906 ins->codep++;
12907 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12908 oappend_register (ins, att_names_mm[ins->modrm.rm]);
12909 return true;
12910 }
12911
12912 static bool
OP_MXC(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)12913 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12914 int sizeflag ATTRIBUTE_UNUSED)
12915 {
12916 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12917 oappend_register (ins, att_names_mm[ins->modrm.reg]);
12918 return true;
12919 }
12920
12921 static bool
OP_EX(instr_info * ins,int bytemode,int sizeflag)12922 OP_EX (instr_info *ins, int bytemode, int sizeflag)
12923 {
12924 int reg;
12925
12926 /* Skip mod/rm byte. */
12927 MODRM_CHECK;
12928 ins->codep++;
12929
12930 if (bytemode == dq_mode)
12931 bytemode = ins->vex.w ? q_mode : d_mode;
12932
12933 if (ins->modrm.mod != 3)
12934 return OP_E_memory (ins, bytemode, sizeflag);
12935
12936 reg = ins->modrm.rm;
12937 USED_REX (REX_B);
12938 if (ins->rex & REX_B)
12939 reg += 8;
12940 if (ins->rex2 & REX_B)
12941 reg += 16;
12942 if (ins->vex.evex)
12943 {
12944 USED_REX (REX_X);
12945 if ((ins->rex & REX_X))
12946 reg += 16;
12947 }
12948
12949 if ((sizeflag & SUFFIX_ALWAYS)
12950 && (bytemode == x_swap_mode
12951 || bytemode == w_swap_mode
12952 || bytemode == d_swap_mode
12953 || bytemode == q_swap_mode))
12954 swap_operand (ins);
12955
12956 if (bytemode == tmm_mode)
12957 ins->modrm.rm = reg;
12958
12959 print_vector_reg (ins, reg, bytemode);
12960 return true;
12961 }
12962
12963 static bool
OP_R(instr_info * ins,int bytemode,int sizeflag)12964 OP_R (instr_info *ins, int bytemode, int sizeflag)
12965 {
12966 if (ins->modrm.mod != 3)
12967 return BadOp (ins);
12968
12969 switch (bytemode)
12970 {
12971 case d_mode:
12972 case dq_mode:
12973 case q_mode:
12974 case mask_mode:
12975 return OP_E (ins, bytemode, sizeflag);
12976 case q_mm_mode:
12977 return OP_EM (ins, x_mode, sizeflag);
12978 case xmm_mode:
12979 if (ins->vex.length <= 128)
12980 break;
12981 return BadOp (ins);
12982 }
12983
12984 return OP_EX (ins, bytemode, sizeflag);
12985 }
12986
12987 static bool
OP_M(instr_info * ins,int bytemode,int sizeflag)12988 OP_M (instr_info *ins, int bytemode, int sizeflag)
12989 {
12990 /* Skip mod/rm byte. */
12991 MODRM_CHECK;
12992 ins->codep++;
12993
12994 if (ins->modrm.mod == 3)
12995 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12996 return BadOp (ins);
12997
12998 if (bytemode == x_mode)
12999 ins->vex.no_broadcast = true;
13000
13001 return OP_E_memory (ins, bytemode, sizeflag);
13002 }
13003
13004 static bool
OP_0f07(instr_info * ins,int bytemode,int sizeflag)13005 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
13006 {
13007 if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13008 return BadOp (ins);
13009 return OP_E (ins, bytemode, sizeflag);
13010 }
13011
13012 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13013 32bit mode and "xchg %rax,%rax" in 64bit mode. */
13014
13015 static bool
NOP_Fixup(instr_info * ins,int opnd,int sizeflag)13016 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
13017 {
13018 if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
13019 {
13020 ins->mnemonicendp = stpcpy (ins->obuf, "nop");
13021 return true;
13022 }
13023 if (opnd == 0)
13024 return OP_REG (ins, eAX_reg, sizeflag);
13025 return OP_IMREG (ins, eAX_reg, sizeflag);
13026 }
13027
13028 static const char *const Suffix3DNow[] = {
13029 /* 00 */ NULL, NULL, NULL, NULL,
13030 /* 04 */ NULL, NULL, NULL, NULL,
13031 /* 08 */ NULL, NULL, NULL, NULL,
13032 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
13033 /* 10 */ NULL, NULL, NULL, NULL,
13034 /* 14 */ NULL, NULL, NULL, NULL,
13035 /* 18 */ NULL, NULL, NULL, NULL,
13036 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
13037 /* 20 */ NULL, NULL, NULL, NULL,
13038 /* 24 */ NULL, NULL, NULL, NULL,
13039 /* 28 */ NULL, NULL, NULL, NULL,
13040 /* 2C */ NULL, NULL, NULL, NULL,
13041 /* 30 */ NULL, NULL, NULL, NULL,
13042 /* 34 */ NULL, NULL, NULL, NULL,
13043 /* 38 */ NULL, NULL, NULL, NULL,
13044 /* 3C */ NULL, NULL, NULL, NULL,
13045 /* 40 */ NULL, NULL, NULL, NULL,
13046 /* 44 */ NULL, NULL, NULL, NULL,
13047 /* 48 */ NULL, NULL, NULL, NULL,
13048 /* 4C */ NULL, NULL, NULL, NULL,
13049 /* 50 */ NULL, NULL, NULL, NULL,
13050 /* 54 */ NULL, NULL, NULL, NULL,
13051 /* 58 */ NULL, NULL, NULL, NULL,
13052 /* 5C */ NULL, NULL, NULL, NULL,
13053 /* 60 */ NULL, NULL, NULL, NULL,
13054 /* 64 */ NULL, NULL, NULL, NULL,
13055 /* 68 */ NULL, NULL, NULL, NULL,
13056 /* 6C */ NULL, NULL, NULL, NULL,
13057 /* 70 */ NULL, NULL, NULL, NULL,
13058 /* 74 */ NULL, NULL, NULL, NULL,
13059 /* 78 */ NULL, NULL, NULL, NULL,
13060 /* 7C */ NULL, NULL, NULL, NULL,
13061 /* 80 */ NULL, NULL, NULL, NULL,
13062 /* 84 */ NULL, NULL, NULL, NULL,
13063 /* 88 */ NULL, NULL, "pfnacc", NULL,
13064 /* 8C */ NULL, NULL, "pfpnacc", NULL,
13065 /* 90 */ "pfcmpge", NULL, NULL, NULL,
13066 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
13067 /* 98 */ NULL, NULL, "pfsub", NULL,
13068 /* 9C */ NULL, NULL, "pfadd", NULL,
13069 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
13070 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
13071 /* A8 */ NULL, NULL, "pfsubr", NULL,
13072 /* AC */ NULL, NULL, "pfacc", NULL,
13073 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
13074 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
13075 /* B8 */ NULL, NULL, NULL, "pswapd",
13076 /* BC */ NULL, NULL, NULL, "pavgusb",
13077 /* C0 */ NULL, NULL, NULL, NULL,
13078 /* C4 */ NULL, NULL, NULL, NULL,
13079 /* C8 */ NULL, NULL, NULL, NULL,
13080 /* CC */ NULL, NULL, NULL, NULL,
13081 /* D0 */ NULL, NULL, NULL, NULL,
13082 /* D4 */ NULL, NULL, NULL, NULL,
13083 /* D8 */ NULL, NULL, NULL, NULL,
13084 /* DC */ NULL, NULL, NULL, NULL,
13085 /* E0 */ NULL, NULL, NULL, NULL,
13086 /* E4 */ NULL, NULL, NULL, NULL,
13087 /* E8 */ NULL, NULL, NULL, NULL,
13088 /* EC */ NULL, NULL, NULL, NULL,
13089 /* F0 */ NULL, NULL, NULL, NULL,
13090 /* F4 */ NULL, NULL, NULL, NULL,
13091 /* F8 */ NULL, NULL, NULL, NULL,
13092 /* FC */ NULL, NULL, NULL, NULL,
13093 };
13094
13095 static bool
OP_3DNowSuffix(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13096 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13097 int sizeflag ATTRIBUTE_UNUSED)
13098 {
13099 const char *mnemonic;
13100
13101 if (!fetch_code (ins->info, ins->codep + 1))
13102 return false;
13103 /* AMD 3DNow! instructions are specified by an opcode suffix in the
13104 place where an 8-bit immediate would normally go. ie. the last
13105 byte of the instruction. */
13106 ins->obufp = ins->mnemonicendp;
13107 mnemonic = Suffix3DNow[*ins->codep++];
13108 if (mnemonic)
13109 ins->obufp = stpcpy (ins->obufp, mnemonic);
13110 else
13111 {
13112 /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13113 of the opcode (0x0f0f) and the opcode suffix, we need to do
13114 all the ins->modrm processing first, and don't know until now that
13115 we have a bad opcode. This necessitates some cleaning up. */
13116 ins->op_out[0][0] = '\0';
13117 ins->op_out[1][0] = '\0';
13118 BadOp (ins);
13119 }
13120 ins->mnemonicendp = ins->obufp;
13121 return true;
13122 }
13123
13124 static const struct op simd_cmp_op[] =
13125 {
13126 { STRING_COMMA_LEN ("eq") },
13127 { STRING_COMMA_LEN ("lt") },
13128 { STRING_COMMA_LEN ("le") },
13129 { STRING_COMMA_LEN ("unord") },
13130 { STRING_COMMA_LEN ("neq") },
13131 { STRING_COMMA_LEN ("nlt") },
13132 { STRING_COMMA_LEN ("nle") },
13133 { STRING_COMMA_LEN ("ord") }
13134 };
13135
13136 static const struct op vex_cmp_op[] =
13137 {
13138 { STRING_COMMA_LEN ("eq_uq") },
13139 { STRING_COMMA_LEN ("nge") },
13140 { STRING_COMMA_LEN ("ngt") },
13141 { STRING_COMMA_LEN ("false") },
13142 { STRING_COMMA_LEN ("neq_oq") },
13143 { STRING_COMMA_LEN ("ge") },
13144 { STRING_COMMA_LEN ("gt") },
13145 { STRING_COMMA_LEN ("true") },
13146 { STRING_COMMA_LEN ("eq_os") },
13147 { STRING_COMMA_LEN ("lt_oq") },
13148 { STRING_COMMA_LEN ("le_oq") },
13149 { STRING_COMMA_LEN ("unord_s") },
13150 { STRING_COMMA_LEN ("neq_us") },
13151 { STRING_COMMA_LEN ("nlt_uq") },
13152 { STRING_COMMA_LEN ("nle_uq") },
13153 { STRING_COMMA_LEN ("ord_s") },
13154 { STRING_COMMA_LEN ("eq_us") },
13155 { STRING_COMMA_LEN ("nge_uq") },
13156 { STRING_COMMA_LEN ("ngt_uq") },
13157 { STRING_COMMA_LEN ("false_os") },
13158 { STRING_COMMA_LEN ("neq_os") },
13159 { STRING_COMMA_LEN ("ge_oq") },
13160 { STRING_COMMA_LEN ("gt_oq") },
13161 { STRING_COMMA_LEN ("true_us") },
13162 };
13163
13164 static bool
CMP_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13165 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13166 int sizeflag ATTRIBUTE_UNUSED)
13167 {
13168 unsigned int cmp_type;
13169
13170 if (!fetch_code (ins->info, ins->codep + 1))
13171 return false;
13172 cmp_type = *ins->codep++;
13173 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13174 {
13175 char suffix[3];
13176 char *p = ins->mnemonicendp - 2;
13177 suffix[0] = p[0];
13178 suffix[1] = p[1];
13179 suffix[2] = '\0';
13180 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13181 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13182 }
13183 else if (ins->need_vex
13184 && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13185 {
13186 char suffix[3];
13187 char *p = ins->mnemonicendp - 2;
13188 suffix[0] = p[0];
13189 suffix[1] = p[1];
13190 suffix[2] = '\0';
13191 cmp_type -= ARRAY_SIZE (simd_cmp_op);
13192 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13193 ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13194 }
13195 else
13196 {
13197 /* We have a reserved extension byte. Output it directly. */
13198 oappend_immediate (ins, cmp_type);
13199 }
13200 return true;
13201 }
13202
13203 static bool
OP_Mwait(instr_info * ins,int bytemode,int sizeflag ATTRIBUTE_UNUSED)13204 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13205 {
13206 /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
13207 if (!ins->intel_syntax)
13208 {
13209 strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13210 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13211 if (bytemode == eBX_reg)
13212 strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13213 ins->two_source_ops = true;
13214 }
13215 /* Skip mod/rm byte. */
13216 MODRM_CHECK;
13217 ins->codep++;
13218 return true;
13219 }
13220
13221 static bool
OP_Monitor(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13222 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13223 int sizeflag ATTRIBUTE_UNUSED)
13224 {
13225 /* monitor %{e,r,}ax,%ecx,%edx" */
13226 if (!ins->intel_syntax)
13227 {
13228 const char (*names)[8] = (ins->address_mode == mode_64bit
13229 ? att_names64 : att_names32);
13230
13231 if (ins->prefixes & PREFIX_ADDR)
13232 {
13233 /* Remove "addr16/addr32". */
13234 ins->all_prefixes[ins->last_addr_prefix] = 0;
13235 names = (ins->address_mode != mode_32bit
13236 ? att_names32 : att_names16);
13237 ins->used_prefixes |= PREFIX_ADDR;
13238 }
13239 else if (ins->address_mode == mode_16bit)
13240 names = att_names16;
13241 strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13242 strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13243 strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13244 ins->two_source_ops = true;
13245 }
13246 /* Skip mod/rm byte. */
13247 MODRM_CHECK;
13248 ins->codep++;
13249 return true;
13250 }
13251
13252 static bool
REP_Fixup(instr_info * ins,int bytemode,int sizeflag)13253 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13254 {
13255 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13256 lods and stos. */
13257 if (ins->prefixes & PREFIX_REPZ)
13258 ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13259
13260 switch (bytemode)
13261 {
13262 case al_reg:
13263 case eAX_reg:
13264 case indir_dx_reg:
13265 return OP_IMREG (ins, bytemode, sizeflag);
13266 case eDI_reg:
13267 return OP_ESreg (ins, bytemode, sizeflag);
13268 case eSI_reg:
13269 return OP_DSreg (ins, bytemode, sizeflag);
13270 default:
13271 abort ();
13272 break;
13273 }
13274 return true;
13275 }
13276
13277 static bool
SEP_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13278 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13279 int sizeflag ATTRIBUTE_UNUSED)
13280 {
13281 if (ins->isa64 != amd64)
13282 return true;
13283
13284 ins->obufp = ins->obuf;
13285 BadOp (ins);
13286 ins->mnemonicendp = ins->obufp;
13287 ++ins->codep;
13288 return true;
13289 }
13290
13291 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13292 "bnd". */
13293
13294 static bool
BND_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13295 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13296 int sizeflag ATTRIBUTE_UNUSED)
13297 {
13298 if (ins->prefixes & PREFIX_REPNZ)
13299 ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13300 return true;
13301 }
13302
13303 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13304 "notrack". */
13305
13306 static bool
NOTRACK_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13307 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13308 int sizeflag ATTRIBUTE_UNUSED)
13309 {
13310 /* Since active_seg_prefix is not set in 64-bit mode, check whether
13311 we've seen a PREFIX_DS. */
13312 if ((ins->prefixes & PREFIX_DS) != 0
13313 && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13314 {
13315 /* NOTRACK prefix is only valid on indirect branch instructions.
13316 NB: DATA prefix is unsupported for Intel64. */
13317 ins->active_seg_prefix = 0;
13318 ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13319 }
13320 return true;
13321 }
13322
13323 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13324 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13325 */
13326
13327 static bool
HLE_Fixup1(instr_info * ins,int bytemode,int sizeflag)13328 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13329 {
13330 if (ins->modrm.mod != 3
13331 && (ins->prefixes & PREFIX_LOCK) != 0)
13332 {
13333 if (ins->prefixes & PREFIX_REPZ)
13334 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13335 if (ins->prefixes & PREFIX_REPNZ)
13336 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13337 }
13338
13339 return OP_E (ins, bytemode, sizeflag);
13340 }
13341
13342 /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as
13343 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
13344 */
13345
13346 static bool
HLE_Fixup2(instr_info * ins,int bytemode,int sizeflag)13347 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13348 {
13349 if (ins->modrm.mod != 3)
13350 {
13351 if (ins->prefixes & PREFIX_REPZ)
13352 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13353 if (ins->prefixes & PREFIX_REPNZ)
13354 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13355 }
13356
13357 return OP_E (ins, bytemode, sizeflag);
13358 }
13359
13360 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
13361 "xrelease" for memory operand. No check for LOCK prefix. */
13362
13363 static bool
HLE_Fixup3(instr_info * ins,int bytemode,int sizeflag)13364 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13365 {
13366 if (ins->modrm.mod != 3
13367 && ins->last_repz_prefix > ins->last_repnz_prefix
13368 && (ins->prefixes & PREFIX_REPZ) != 0)
13369 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13370
13371 return OP_E (ins, bytemode, sizeflag);
13372 }
13373
13374 static bool
CMPXCHG8B_Fixup(instr_info * ins,int bytemode,int sizeflag)13375 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13376 {
13377 USED_REX (REX_W);
13378 if (ins->rex & REX_W)
13379 {
13380 /* Change cmpxchg8b to cmpxchg16b. */
13381 char *p = ins->mnemonicendp - 2;
13382 ins->mnemonicendp = stpcpy (p, "16b");
13383 bytemode = o_mode;
13384 }
13385 else if ((ins->prefixes & PREFIX_LOCK) != 0)
13386 {
13387 if (ins->prefixes & PREFIX_REPZ)
13388 ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13389 if (ins->prefixes & PREFIX_REPNZ)
13390 ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13391 }
13392
13393 return OP_M (ins, bytemode, sizeflag);
13394 }
13395
13396 static bool
XMM_Fixup(instr_info * ins,int reg,int sizeflag ATTRIBUTE_UNUSED)13397 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13398 {
13399 const char (*names)[8] = att_names_xmm;
13400
13401 if (ins->need_vex)
13402 {
13403 switch (ins->vex.length)
13404 {
13405 case 128:
13406 break;
13407 case 256:
13408 names = att_names_ymm;
13409 break;
13410 default:
13411 abort ();
13412 }
13413 }
13414 oappend_register (ins, names[reg]);
13415 return true;
13416 }
13417
13418 static bool
FXSAVE_Fixup(instr_info * ins,int bytemode,int sizeflag)13419 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13420 {
13421 /* Add proper suffix to "fxsave" and "fxrstor". */
13422 USED_REX (REX_W);
13423 if (ins->rex & REX_W)
13424 {
13425 char *p = ins->mnemonicendp;
13426 *p++ = '6';
13427 *p++ = '4';
13428 *p = '\0';
13429 ins->mnemonicendp = p;
13430 }
13431 return OP_M (ins, bytemode, sizeflag);
13432 }
13433
13434 /* Display the destination register operand for instructions with
13435 VEX. */
13436
13437 static bool
OP_VEX(instr_info * ins,int bytemode,int sizeflag ATTRIBUTE_UNUSED)13438 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13439 {
13440 int reg, modrm_reg, sib_index = -1;
13441 const char (*names)[8];
13442
13443 if (!ins->need_vex)
13444 return true;
13445
13446 if (ins->evex_type == evex_from_legacy)
13447 {
13448 ins->evex_used |= EVEX_b_used;
13449 if (!ins->vex.nd)
13450 return true;
13451 }
13452
13453 reg = ins->vex.register_specifier;
13454 ins->vex.register_specifier = 0;
13455 if (ins->address_mode != mode_64bit)
13456 {
13457 if (ins->vex.evex && !ins->vex.v)
13458 {
13459 oappend (ins, "(bad)");
13460 return true;
13461 }
13462
13463 reg &= 7;
13464 }
13465 else if (ins->vex.evex && !ins->vex.v)
13466 reg += 16;
13467
13468 switch (bytemode)
13469 {
13470 case scalar_mode:
13471 oappend_register (ins, att_names_xmm[reg]);
13472 return true;
13473
13474 case vex_vsib_d_w_dq_mode:
13475 case vex_vsib_q_w_dq_mode:
13476 /* This must be the 3rd operand. */
13477 if (ins->obufp != ins->op_out[2])
13478 abort ();
13479 if (ins->vex.length == 128
13480 || (bytemode != vex_vsib_d_w_dq_mode
13481 && !ins->vex.w))
13482 oappend_register (ins, att_names_xmm[reg]);
13483 else
13484 oappend_register (ins, att_names_ymm[reg]);
13485
13486 /* All 3 XMM/YMM registers must be distinct. */
13487 modrm_reg = ins->modrm.reg;
13488 if (ins->rex & REX_R)
13489 modrm_reg += 8;
13490
13491 if (ins->has_sib && ins->modrm.rm == 4)
13492 {
13493 sib_index = ins->sib.index;
13494 if (ins->rex & REX_X)
13495 sib_index += 8;
13496 }
13497
13498 if (reg == modrm_reg || reg == sib_index)
13499 strcpy (ins->obufp, "/(bad)");
13500 if (modrm_reg == sib_index || modrm_reg == reg)
13501 strcat (ins->op_out[0], "/(bad)");
13502 if (sib_index == modrm_reg || sib_index == reg)
13503 strcat (ins->op_out[1], "/(bad)");
13504
13505 return true;
13506
13507 case tmm_mode:
13508 /* All 3 TMM registers must be distinct. */
13509 if (reg >= 8)
13510 oappend (ins, "(bad)");
13511 else
13512 {
13513 /* This must be the 3rd operand. */
13514 if (ins->obufp != ins->op_out[2])
13515 abort ();
13516 oappend_register (ins, att_names_tmm[reg]);
13517 if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13518 strcpy (ins->obufp, "/(bad)");
13519 }
13520
13521 if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13522 || ins->modrm.rm == reg)
13523 {
13524 if (ins->modrm.reg <= 8
13525 && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13526 strcat (ins->op_out[0], "/(bad)");
13527 if (ins->modrm.rm <= 8
13528 && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13529 strcat (ins->op_out[1], "/(bad)");
13530 }
13531
13532 return true;
13533 }
13534
13535 switch (ins->vex.length)
13536 {
13537 case 128:
13538 switch (bytemode)
13539 {
13540 case x_mode:
13541 names = att_names_xmm;
13542 ins->evex_used |= EVEX_len_used;
13543 break;
13544 case v_mode:
13545 case dq_mode:
13546 if (ins->rex & REX_W)
13547 names = att_names64;
13548 else if (bytemode == v_mode
13549 && !(sizeflag & DFLAG))
13550 names = att_names16;
13551 else
13552 names = att_names32;
13553 break;
13554 case b_mode:
13555 names = att_names8rex;
13556 break;
13557 case q_mode:
13558 names = att_names64;
13559 break;
13560 case mask_bd_mode:
13561 case mask_mode:
13562 if (reg > 0x7)
13563 {
13564 oappend (ins, "(bad)");
13565 return true;
13566 }
13567 names = att_names_mask;
13568 break;
13569 default:
13570 abort ();
13571 return true;
13572 }
13573 break;
13574 case 256:
13575 switch (bytemode)
13576 {
13577 case x_mode:
13578 names = att_names_ymm;
13579 ins->evex_used |= EVEX_len_used;
13580 break;
13581 case mask_bd_mode:
13582 case mask_mode:
13583 if (reg <= 0x7)
13584 {
13585 names = att_names_mask;
13586 break;
13587 }
13588 /* Fall through. */
13589 default:
13590 /* See PR binutils/20893 for a reproducer. */
13591 oappend (ins, "(bad)");
13592 return true;
13593 }
13594 break;
13595 case 512:
13596 names = att_names_zmm;
13597 ins->evex_used |= EVEX_len_used;
13598 break;
13599 default:
13600 abort ();
13601 break;
13602 }
13603 oappend_register (ins, names[reg]);
13604 return true;
13605 }
13606
13607 static bool
OP_VexR(instr_info * ins,int bytemode,int sizeflag)13608 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13609 {
13610 if (ins->modrm.mod == 3)
13611 return OP_VEX (ins, bytemode, sizeflag);
13612 return true;
13613 }
13614
13615 static bool
OP_VexW(instr_info * ins,int bytemode,int sizeflag)13616 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13617 {
13618 OP_VEX (ins, bytemode, sizeflag);
13619
13620 if (ins->vex.w)
13621 {
13622 /* Swap 2nd and 3rd operands. */
13623 char *tmp = ins->op_out[2];
13624
13625 ins->op_out[2] = ins->op_out[1];
13626 ins->op_out[1] = tmp;
13627 }
13628 return true;
13629 }
13630
13631 static bool
OP_REG_VexI4(instr_info * ins,int bytemode,int sizeflag ATTRIBUTE_UNUSED)13632 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13633 {
13634 int reg;
13635 const char (*names)[8] = att_names_xmm;
13636
13637 if (!fetch_code (ins->info, ins->codep + 1))
13638 return false;
13639 reg = *ins->codep++;
13640
13641 if (bytemode != x_mode && bytemode != scalar_mode)
13642 abort ();
13643
13644 reg >>= 4;
13645 if (ins->address_mode != mode_64bit)
13646 reg &= 7;
13647
13648 if (bytemode == x_mode && ins->vex.length == 256)
13649 names = att_names_ymm;
13650
13651 oappend_register (ins, names[reg]);
13652
13653 if (ins->vex.w)
13654 {
13655 /* Swap 3rd and 4th operands. */
13656 char *tmp = ins->op_out[3];
13657
13658 ins->op_out[3] = ins->op_out[2];
13659 ins->op_out[2] = tmp;
13660 }
13661 return true;
13662 }
13663
13664 static bool
OP_VexI4(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13665 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13666 int sizeflag ATTRIBUTE_UNUSED)
13667 {
13668 oappend_immediate (ins, ins->codep[-1] & 0xf);
13669 return true;
13670 }
13671
13672 static bool
VPCMP_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13673 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13674 int sizeflag ATTRIBUTE_UNUSED)
13675 {
13676 unsigned int cmp_type;
13677
13678 if (!ins->vex.evex)
13679 abort ();
13680
13681 if (!fetch_code (ins->info, ins->codep + 1))
13682 return false;
13683 cmp_type = *ins->codep++;
13684 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13685 If it's the case, print suffix, otherwise - print the immediate. */
13686 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13687 && cmp_type != 3
13688 && cmp_type != 7)
13689 {
13690 char suffix[3];
13691 char *p = ins->mnemonicendp - 2;
13692
13693 /* vpcmp* can have both one- and two-lettered suffix. */
13694 if (p[0] == 'p')
13695 {
13696 p++;
13697 suffix[0] = p[0];
13698 suffix[1] = '\0';
13699 }
13700 else
13701 {
13702 suffix[0] = p[0];
13703 suffix[1] = p[1];
13704 suffix[2] = '\0';
13705 }
13706
13707 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13708 ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13709 }
13710 else
13711 {
13712 /* We have a reserved extension byte. Output it directly. */
13713 oappend_immediate (ins, cmp_type);
13714 }
13715 return true;
13716 }
13717
13718 static const struct op xop_cmp_op[] =
13719 {
13720 { STRING_COMMA_LEN ("lt") },
13721 { STRING_COMMA_LEN ("le") },
13722 { STRING_COMMA_LEN ("gt") },
13723 { STRING_COMMA_LEN ("ge") },
13724 { STRING_COMMA_LEN ("eq") },
13725 { STRING_COMMA_LEN ("neq") },
13726 { STRING_COMMA_LEN ("false") },
13727 { STRING_COMMA_LEN ("true") }
13728 };
13729
13730 static bool
VPCOM_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13731 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13732 int sizeflag ATTRIBUTE_UNUSED)
13733 {
13734 unsigned int cmp_type;
13735
13736 if (!fetch_code (ins->info, ins->codep + 1))
13737 return false;
13738 cmp_type = *ins->codep++;
13739 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13740 {
13741 char suffix[3];
13742 char *p = ins->mnemonicendp - 2;
13743
13744 /* vpcom* can have both one- and two-lettered suffix. */
13745 if (p[0] == 'm')
13746 {
13747 p++;
13748 suffix[0] = p[0];
13749 suffix[1] = '\0';
13750 }
13751 else
13752 {
13753 suffix[0] = p[0];
13754 suffix[1] = p[1];
13755 suffix[2] = '\0';
13756 }
13757
13758 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13759 ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13760 }
13761 else
13762 {
13763 /* We have a reserved extension byte. Output it directly. */
13764 oappend_immediate (ins, cmp_type);
13765 }
13766 return true;
13767 }
13768
13769 static const struct op pclmul_op[] =
13770 {
13771 { STRING_COMMA_LEN ("lql") },
13772 { STRING_COMMA_LEN ("hql") },
13773 { STRING_COMMA_LEN ("lqh") },
13774 { STRING_COMMA_LEN ("hqh") }
13775 };
13776
13777 static bool
PCLMUL_Fixup(instr_info * ins,int bytemode ATTRIBUTE_UNUSED,int sizeflag ATTRIBUTE_UNUSED)13778 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13779 int sizeflag ATTRIBUTE_UNUSED)
13780 {
13781 unsigned int pclmul_type;
13782
13783 if (!fetch_code (ins->info, ins->codep + 1))
13784 return false;
13785 pclmul_type = *ins->codep++;
13786 switch (pclmul_type)
13787 {
13788 case 0x10:
13789 pclmul_type = 2;
13790 break;
13791 case 0x11:
13792 pclmul_type = 3;
13793 break;
13794 default:
13795 break;
13796 }
13797 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13798 {
13799 char suffix[4];
13800 char *p = ins->mnemonicendp - 3;
13801 suffix[0] = p[0];
13802 suffix[1] = p[1];
13803 suffix[2] = p[2];
13804 suffix[3] = '\0';
13805 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13806 ins->mnemonicendp += pclmul_op[pclmul_type].len;
13807 }
13808 else
13809 {
13810 /* We have a reserved extension byte. Output it directly. */
13811 oappend_immediate (ins, pclmul_type);
13812 }
13813 return true;
13814 }
13815
13816 static bool
MOVSXD_Fixup(instr_info * ins,int bytemode,int sizeflag)13817 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13818 {
13819 /* Add proper suffix to "movsxd". */
13820 char *p = ins->mnemonicendp;
13821
13822 switch (bytemode)
13823 {
13824 case movsxd_mode:
13825 if (!ins->intel_syntax)
13826 {
13827 USED_REX (REX_W);
13828 if (ins->rex & REX_W)
13829 {
13830 *p++ = 'l';
13831 *p++ = 'q';
13832 break;
13833 }
13834 }
13835
13836 *p++ = 'x';
13837 *p++ = 'd';
13838 break;
13839 default:
13840 oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13841 break;
13842 }
13843
13844 ins->mnemonicendp = p;
13845 *p = '\0';
13846 return OP_E (ins, bytemode, sizeflag);
13847 }
13848
13849 static bool
DistinctDest_Fixup(instr_info * ins,int bytemode,int sizeflag)13850 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13851 {
13852 unsigned int reg = ins->vex.register_specifier;
13853 unsigned int modrm_reg = ins->modrm.reg;
13854 unsigned int modrm_rm = ins->modrm.rm;
13855
13856 /* Calc destination register number. */
13857 if (ins->rex & REX_R)
13858 modrm_reg += 8;
13859 if (ins->rex2 & REX_R)
13860 modrm_reg += 16;
13861
13862 /* Calc src1 register number. */
13863 if (ins->address_mode != mode_64bit)
13864 reg &= 7;
13865 else if (ins->vex.evex && !ins->vex.v)
13866 reg += 16;
13867
13868 /* Calc src2 register number. */
13869 if (ins->modrm.mod == 3)
13870 {
13871 if (ins->rex & REX_B)
13872 modrm_rm += 8;
13873 if (ins->rex & REX_X)
13874 modrm_rm += 16;
13875 }
13876
13877 /* Destination and source registers must be distinct, output bad if
13878 dest == src1 or dest == src2. */
13879 if (modrm_reg == reg
13880 || (ins->modrm.mod == 3
13881 && modrm_reg == modrm_rm))
13882 {
13883 oappend (ins, "(bad)");
13884 return true;
13885 }
13886 return OP_XMM (ins, bytemode, sizeflag);
13887 }
13888
13889 static bool
OP_Rounding(instr_info * ins,int bytemode,int sizeflag ATTRIBUTE_UNUSED)13890 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13891 {
13892 if (ins->modrm.mod != 3 || !ins->vex.b)
13893 return true;
13894
13895 switch (bytemode)
13896 {
13897 case evex_rounding_64_mode:
13898 if (ins->address_mode != mode_64bit || !ins->vex.w)
13899 return true;
13900 /* Fall through. */
13901 case evex_rounding_mode:
13902 ins->evex_used |= EVEX_b_used;
13903 oappend (ins, names_rounding[ins->vex.ll]);
13904 break;
13905 case evex_sae_mode:
13906 ins->evex_used |= EVEX_b_used;
13907 oappend (ins, "{");
13908 break;
13909 default:
13910 abort ();
13911 }
13912 oappend (ins, "sae}");
13913 return true;
13914 }
13915
13916 static bool
PREFETCHI_Fixup(instr_info * ins,int bytemode,int sizeflag)13917 PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
13918 {
13919 if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
13920 {
13921 if (ins->intel_syntax)
13922 {
13923 ins->mnemonicendp = stpcpy (ins->obuf, "nop ");
13924 }
13925 else
13926 {
13927 USED_REX (REX_W);
13928 if (ins->rex & REX_W)
13929 ins->mnemonicendp = stpcpy (ins->obuf, "nopq ");
13930 else
13931 {
13932 if (sizeflag & DFLAG)
13933 ins->mnemonicendp = stpcpy (ins->obuf, "nopl ");
13934 else
13935 ins->mnemonicendp = stpcpy (ins->obuf, "nopw ");
13936 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13937 }
13938 }
13939 bytemode = v_mode;
13940 }
13941
13942 return OP_M (ins, bytemode, sizeflag);
13943 }
13944
13945 static bool
PUSH2_POP2_Fixup(instr_info * ins,int bytemode,int sizeflag)13946 PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag)
13947 {
13948 if (ins->modrm.mod != 3)
13949 return true;
13950
13951 unsigned int vvvv_reg = ins->vex.register_specifier
13952 | (!ins->vex.v << 4);
13953 unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0)
13954 + (ins->rex2 & REX_B ? 16 : 0);
13955
13956 /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers. */
13957 if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4
13958 || (!ins->modrm.reg
13959 && vvvv_reg == rm_reg))
13960 {
13961 oappend (ins, "(bad)");
13962 return true;
13963 }
13964
13965 return OP_VEX (ins, bytemode, sizeflag);
13966 }
13967
13968 static bool
JMPABS_Fixup(instr_info * ins,int bytemode,int sizeflag)13969 JMPABS_Fixup (instr_info *ins, int bytemode, int sizeflag)
13970 {
13971 if (ins->last_rex2_prefix >= 0)
13972 {
13973 uint64_t op;
13974
13975 if ((ins->prefixes & (PREFIX_OPCODE | PREFIX_ADDR | PREFIX_LOCK)) != 0x0
13976 || (ins->rex & REX_W) != 0x0)
13977 {
13978 oappend (ins, "(bad)");
13979 return true;
13980 }
13981
13982 if (bytemode == eAX_reg)
13983 return true;
13984
13985 if (!get64 (ins, &op))
13986 return false;
13987
13988 ins->mnemonicendp = stpcpy (ins->obuf, "jmpabs");
13989 ins->rex2 |= REX2_SPECIAL;
13990 oappend_immediate (ins, op);
13991
13992 return true;
13993 }
13994
13995 if (bytemode == eAX_reg)
13996 return OP_IMREG (ins, bytemode, sizeflag);
13997 return OP_OFF64 (ins, bytemode, sizeflag);
13998 }
13999