1 /* $NetBSD: dvo_ch7xxx.c,v 1.2 2021/12/18 23:45:29 riastradh Exp $ */
2
3 /**************************************************************************
4
5 Copyright © 2006 Dave Airlie
6
7 All Rights Reserved.
8
9 Permission is hereby granted, free of charge, to any person obtaining a
10 copy of this software and associated documentation files (the
11 "Software"), to deal in the Software without restriction, including
12 without limitation the rights to use, copy, modify, merge, publish,
13 distribute, sub license, and/or sell copies of the Software, and to
14 permit persons to whom the Software is furnished to do so, subject to
15 the following conditions:
16
17 The above copyright notice and this permission notice (including the
18 next paragraph) shall be included in all copies or substantial portions
19 of the Software.
20
21 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
22 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
23 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
24 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
25 ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
26 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
27 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28
29 **************************************************************************/
30
31 #include <sys/cdefs.h>
32 __KERNEL_RCSID(0, "$NetBSD: dvo_ch7xxx.c,v 1.2 2021/12/18 23:45:29 riastradh Exp $");
33
34 #include "intel_display_types.h"
35 #include "intel_dvo_dev.h"
36
37 #define CH7xxx_REG_VID 0x4a
38 #define CH7xxx_REG_DID 0x4b
39
40 #define CH7011_VID 0x83 /* 7010 as well */
41 #define CH7010B_VID 0x05
42 #define CH7009A_VID 0x84
43 #define CH7009B_VID 0x85
44 #define CH7301_VID 0x95
45
46 #define CH7xxx_VID 0x84
47 #define CH7xxx_DID 0x17
48 #define CH7010_DID 0x16
49
50 #define CH7xxx_NUM_REGS 0x4c
51
52 #define CH7xxx_CM 0x1c
53 #define CH7xxx_CM_XCM (1<<0)
54 #define CH7xxx_CM_MCP (1<<2)
55 #define CH7xxx_INPUT_CLOCK 0x1d
56 #define CH7xxx_GPIO 0x1e
57 #define CH7xxx_GPIO_HPIR (1<<3)
58 #define CH7xxx_IDF 0x1f
59
60 #define CH7xxx_IDF_HSP (1<<3)
61 #define CH7xxx_IDF_VSP (1<<4)
62
63 #define CH7xxx_CONNECTION_DETECT 0x20
64 #define CH7xxx_CDET_DVI (1<<5)
65
66 #define CH7301_DAC_CNTL 0x21
67 #define CH7301_HOTPLUG 0x23
68 #define CH7xxx_TCTL 0x31
69 #define CH7xxx_TVCO 0x32
70 #define CH7xxx_TPCP 0x33
71 #define CH7xxx_TPD 0x34
72 #define CH7xxx_TPVT 0x35
73 #define CH7xxx_TLPF 0x36
74 #define CH7xxx_TCT 0x37
75 #define CH7301_TEST_PATTERN 0x48
76
77 #define CH7xxx_PM 0x49
78 #define CH7xxx_PM_FPD (1<<0)
79 #define CH7301_PM_DACPD0 (1<<1)
80 #define CH7301_PM_DACPD1 (1<<2)
81 #define CH7301_PM_DACPD2 (1<<3)
82 #define CH7xxx_PM_DVIL (1<<6)
83 #define CH7xxx_PM_DVIP (1<<7)
84
85 #define CH7301_SYNC_POLARITY 0x56
86 #define CH7301_SYNC_RGB_YUV (1<<0)
87 #define CH7301_SYNC_POL_DVI (1<<5)
88
89 /** @file
90 * driver for the Chrontel 7xxx DVI chip over DVO.
91 */
92
93 static struct ch7xxx_id_struct {
94 u8 vid;
95 const char *name;
96 } ch7xxx_ids[] = {
97 { CH7011_VID, "CH7011" },
98 { CH7010B_VID, "CH7010B" },
99 { CH7009A_VID, "CH7009A" },
100 { CH7009B_VID, "CH7009B" },
101 { CH7301_VID, "CH7301" },
102 };
103
104 static struct ch7xxx_did_struct {
105 u8 did;
106 const char *name;
107 } ch7xxx_dids[] = {
108 { CH7xxx_DID, "CH7XXX" },
109 { CH7010_DID, "CH7010B" },
110 };
111
112 struct ch7xxx_priv {
113 bool quiet;
114 };
115
ch7xxx_get_id(u8 vid)116 static const char *ch7xxx_get_id(u8 vid)
117 {
118 int i;
119
120 for (i = 0; i < ARRAY_SIZE(ch7xxx_ids); i++) {
121 if (ch7xxx_ids[i].vid == vid)
122 return ch7xxx_ids[i].name;
123 }
124
125 return NULL;
126 }
127
ch7xxx_get_did(u8 did)128 static const char *ch7xxx_get_did(u8 did)
129 {
130 int i;
131
132 for (i = 0; i < ARRAY_SIZE(ch7xxx_dids); i++) {
133 if (ch7xxx_dids[i].did == did)
134 return ch7xxx_dids[i].name;
135 }
136
137 return NULL;
138 }
139
140 /** Reads an 8 bit register */
ch7xxx_readb(struct intel_dvo_device * dvo,int addr,u8 * ch)141 static bool ch7xxx_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
142 {
143 struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
144 struct i2c_adapter *adapter = dvo->i2c_bus;
145 u8 out_buf[2];
146 u8 in_buf[2];
147
148 struct i2c_msg msgs[] = {
149 {
150 .addr = dvo->slave_addr,
151 .flags = 0,
152 .len = 1,
153 .buf = out_buf,
154 },
155 {
156 .addr = dvo->slave_addr,
157 .flags = I2C_M_RD,
158 .len = 1,
159 .buf = in_buf,
160 }
161 };
162
163 out_buf[0] = addr;
164 out_buf[1] = 0;
165
166 if (i2c_transfer(adapter, msgs, 2) == 2) {
167 *ch = in_buf[0];
168 return true;
169 }
170
171 if (!ch7xxx->quiet) {
172 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
173 addr, adapter->name, dvo->slave_addr);
174 }
175 return false;
176 }
177
178 /** Writes an 8 bit register */
ch7xxx_writeb(struct intel_dvo_device * dvo,int addr,u8 ch)179 static bool ch7xxx_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
180 {
181 struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
182 struct i2c_adapter *adapter = dvo->i2c_bus;
183 u8 out_buf[2];
184 struct i2c_msg msg = {
185 .addr = dvo->slave_addr,
186 .flags = 0,
187 .len = 2,
188 .buf = out_buf,
189 };
190
191 out_buf[0] = addr;
192 out_buf[1] = ch;
193
194 if (i2c_transfer(adapter, &msg, 1) == 1)
195 return true;
196
197 if (!ch7xxx->quiet) {
198 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
199 addr, adapter->name, dvo->slave_addr);
200 }
201
202 return false;
203 }
204
ch7xxx_init(struct intel_dvo_device * dvo,struct i2c_adapter * adapter)205 static bool ch7xxx_init(struct intel_dvo_device *dvo,
206 struct i2c_adapter *adapter)
207 {
208 /* this will detect the CH7xxx chip on the specified i2c bus */
209 struct ch7xxx_priv *ch7xxx;
210 u8 vendor, device;
211 const char *name, *devid;
212
213 ch7xxx = kzalloc(sizeof(struct ch7xxx_priv), GFP_KERNEL);
214 if (ch7xxx == NULL)
215 return false;
216
217 dvo->i2c_bus = adapter;
218 dvo->dev_priv = ch7xxx;
219 ch7xxx->quiet = true;
220
221 if (!ch7xxx_readb(dvo, CH7xxx_REG_VID, &vendor))
222 goto out;
223
224 name = ch7xxx_get_id(vendor);
225 if (!name) {
226 DRM_DEBUG_KMS("ch7xxx not detected; got VID 0x%02x from %s slave %d.\n",
227 vendor, adapter->name, dvo->slave_addr);
228 goto out;
229 }
230
231
232 if (!ch7xxx_readb(dvo, CH7xxx_REG_DID, &device))
233 goto out;
234
235 devid = ch7xxx_get_did(device);
236 if (!devid) {
237 DRM_DEBUG_KMS("ch7xxx not detected; got DID 0x%02x from %s slave %d.\n",
238 device, adapter->name, dvo->slave_addr);
239 goto out;
240 }
241
242 ch7xxx->quiet = false;
243 DRM_DEBUG_KMS("Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n",
244 name, vendor, device);
245 return true;
246 out:
247 kfree(ch7xxx);
248 return false;
249 }
250
ch7xxx_detect(struct intel_dvo_device * dvo)251 static enum drm_connector_status ch7xxx_detect(struct intel_dvo_device *dvo)
252 {
253 u8 cdet, orig_pm, pm;
254
255 ch7xxx_readb(dvo, CH7xxx_PM, &orig_pm);
256
257 pm = orig_pm;
258 pm &= ~CH7xxx_PM_FPD;
259 pm |= CH7xxx_PM_DVIL | CH7xxx_PM_DVIP;
260
261 ch7xxx_writeb(dvo, CH7xxx_PM, pm);
262
263 ch7xxx_readb(dvo, CH7xxx_CONNECTION_DETECT, &cdet);
264
265 ch7xxx_writeb(dvo, CH7xxx_PM, orig_pm);
266
267 if (cdet & CH7xxx_CDET_DVI)
268 return connector_status_connected;
269 return connector_status_disconnected;
270 }
271
ch7xxx_mode_valid(struct intel_dvo_device * dvo,struct drm_display_mode * mode)272 static enum drm_mode_status ch7xxx_mode_valid(struct intel_dvo_device *dvo,
273 struct drm_display_mode *mode)
274 {
275 if (mode->clock > 165000)
276 return MODE_CLOCK_HIGH;
277
278 return MODE_OK;
279 }
280
ch7xxx_mode_set(struct intel_dvo_device * dvo,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted_mode)281 static void ch7xxx_mode_set(struct intel_dvo_device *dvo,
282 const struct drm_display_mode *mode,
283 const struct drm_display_mode *adjusted_mode)
284 {
285 u8 tvco, tpcp, tpd, tlpf, idf;
286
287 if (mode->clock <= 65000) {
288 tvco = 0x23;
289 tpcp = 0x08;
290 tpd = 0x16;
291 tlpf = 0x60;
292 } else {
293 tvco = 0x2d;
294 tpcp = 0x06;
295 tpd = 0x26;
296 tlpf = 0xa0;
297 }
298
299 ch7xxx_writeb(dvo, CH7xxx_TCTL, 0x00);
300 ch7xxx_writeb(dvo, CH7xxx_TVCO, tvco);
301 ch7xxx_writeb(dvo, CH7xxx_TPCP, tpcp);
302 ch7xxx_writeb(dvo, CH7xxx_TPD, tpd);
303 ch7xxx_writeb(dvo, CH7xxx_TPVT, 0x30);
304 ch7xxx_writeb(dvo, CH7xxx_TLPF, tlpf);
305 ch7xxx_writeb(dvo, CH7xxx_TCT, 0x00);
306
307 ch7xxx_readb(dvo, CH7xxx_IDF, &idf);
308
309 idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP);
310 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
311 idf |= CH7xxx_IDF_HSP;
312
313 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
314 idf |= CH7xxx_IDF_VSP;
315
316 ch7xxx_writeb(dvo, CH7xxx_IDF, idf);
317 }
318
319 /* set the CH7xxx power state */
ch7xxx_dpms(struct intel_dvo_device * dvo,bool enable)320 static void ch7xxx_dpms(struct intel_dvo_device *dvo, bool enable)
321 {
322 if (enable)
323 ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_DVIL | CH7xxx_PM_DVIP);
324 else
325 ch7xxx_writeb(dvo, CH7xxx_PM, CH7xxx_PM_FPD);
326 }
327
ch7xxx_get_hw_state(struct intel_dvo_device * dvo)328 static bool ch7xxx_get_hw_state(struct intel_dvo_device *dvo)
329 {
330 u8 val;
331
332 ch7xxx_readb(dvo, CH7xxx_PM, &val);
333
334 if (val & (CH7xxx_PM_DVIL | CH7xxx_PM_DVIP))
335 return true;
336 else
337 return false;
338 }
339
ch7xxx_dump_regs(struct intel_dvo_device * dvo)340 static void ch7xxx_dump_regs(struct intel_dvo_device *dvo)
341 {
342 int i;
343
344 for (i = 0; i < CH7xxx_NUM_REGS; i++) {
345 u8 val;
346 if ((i % 8) == 0)
347 DRM_DEBUG_KMS("\n %02X: ", i);
348 ch7xxx_readb(dvo, i, &val);
349 DRM_DEBUG_KMS("%02X ", val);
350 }
351 }
352
ch7xxx_destroy(struct intel_dvo_device * dvo)353 static void ch7xxx_destroy(struct intel_dvo_device *dvo)
354 {
355 struct ch7xxx_priv *ch7xxx = dvo->dev_priv;
356
357 if (ch7xxx) {
358 kfree(ch7xxx);
359 dvo->dev_priv = NULL;
360 }
361 }
362
363 const struct intel_dvo_dev_ops ch7xxx_ops = {
364 .init = ch7xxx_init,
365 .detect = ch7xxx_detect,
366 .mode_valid = ch7xxx_mode_valid,
367 .mode_set = ch7xxx_mode_set,
368 .dpms = ch7xxx_dpms,
369 .get_hw_state = ch7xxx_get_hw_state,
370 .dump_regs = ch7xxx_dump_regs,
371 .destroy = ch7xxx_destroy,
372 };
373