1 /* $NetBSD: c_magnum.c,v 1.23 2013/12/16 15:46:57 mrg Exp $ */
2 /* $OpenBSD: machdep.c,v 1.36 1999/05/22 21:22:19 weingart Exp $ */
3
4 /*
5 * Copyright (c) 1988 University of Utah.
6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved.
8 *
9 * This code is derived from software contributed to Berkeley by
10 * the Systems Programming Group of the University of Utah Computer
11 * Science Department, The Mach Operating System project at
12 * Carnegie-Mellon University and Ralph Campbell.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * SUCH DAMAGE.
37 *
38 * from: @(#)machdep.c 8.3 (Berkeley) 1/12/94
39 */
40
41 /*
42 * for Magnum derived machines like Microsoft-Jazz and PICA-61.
43 */
44
45 #include <sys/cdefs.h>
46 __KERNEL_RCSID(0, "$NetBSD: c_magnum.c,v 1.23 2013/12/16 15:46:57 mrg Exp $");
47
48 #define __INTR_PRIVATE
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/intr.h>
52 #include <sys/device.h>
53
54 #include <uvm/uvm_extern.h>
55
56 #include <machine/autoconf.h>
57 #include <sys/bus.h>
58 #include <machine/pio.h>
59 #include <machine/platform.h>
60 #include <machine/wired_map.h>
61 #include <mips/locore.h>
62 #include <mips/pte.h>
63
64 #include <dev/isa/isavar.h>
65
66 #include <arc/arc/timervar.h>
67 #include <arc/jazz/pica.h>
68 #include <arc/jazz/jazziovar.h>
69 #include <arc/jazz/timer_jazziovar.h>
70 #include <arc/isa/isabrvar.h>
71
72 /*
73 * chipset-dependent timer routine.
74 */
75
76 uint32_t timer_magnum_intr(uint32_t, struct clockframe *);
77 void timer_magnum_init(int);
78
79 struct timer_jazzio_config timer_magnum_conf = {
80 MIPS_INT_MASK_4,
81 timer_magnum_intr,
82 timer_magnum_init,
83 };
84
85 /*
86 * This is a mask of bits to clear in the SR when we go to a
87 * given interrupt priority level.
88 */
89 static const struct ipl_sr_map magnum_ipl_sr_map = {
90 .sr_bits = {
91 [IPL_NONE] = 0,
92 [IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
93 [IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
94 [IPL_VM] = MIPS_SOFT_INT_MASK
95 | MIPS_INT_MASK_0
96 | MIPS_INT_MASK_1
97 | MIPS_INT_MASK_2
98 | MIPS_INT_MASK_3,
99 [IPL_SCHED] = MIPS_INT_MASK,
100 [IPL_DDB] = MIPS_INT_MASK,
101 [IPL_HIGH] = MIPS_INT_MASK,
102 },
103 };
104
105 uint32_t
timer_magnum_intr(uint32_t mask,struct clockframe * cf)106 timer_magnum_intr(uint32_t mask, struct clockframe *cf)
107 {
108
109 (void)inw(R4030_SYS_IT_STAT);
110 last_cp0_count = mips3_cp0_count_read();
111 hardclock(cf);
112 timer_jazzio_ev.ev_count++;
113
114 return MIPS_INT_MASK_4; /* Keep clock interrupts enabled */
115 }
116
117 void
timer_magnum_init(int interval)118 timer_magnum_init(int interval)
119 {
120
121 if (interval <= 0)
122 panic("timer_magnum_init: invalid interval %d", interval);
123
124 out32(R4030_SYS_IT_VALUE, interval - 1);
125
126 /* Enable periodic clock interrupt */
127 out32(R4030_SYS_EXT_IMASK, cpu_int_mask);
128 }
129
130 /*
131 * chipset-dependent isa bus configuration
132 */
133
134 int isabr_magnum_intr_status(void);
135
136 struct isabr_config isabr_magnum_conf = {
137 isabr_magnum_intr_status,
138 };
139
140 int
isabr_magnum_intr_status(void)141 isabr_magnum_intr_status(void)
142 {
143
144 return in32(R4030_SYS_ISA_VECTOR) & (ICU_LEN - 1);
145 }
146
147 /*
148 * chipset-dependent jazzio bus configuration
149 */
150
151 void jazzio_magnum_set_iointr_mask(int);
152
153 struct jazzio_config jazzio_magnum_conf = {
154 PVIS,
155 jazzio_magnum_set_iointr_mask,
156 R4030_SYS_TL_BASE,
157 R4030_SYS_DMA1_REGS,
158 };
159
160 void
jazzio_magnum_set_iointr_mask(int mask)161 jazzio_magnum_set_iointr_mask(int mask)
162 {
163
164 out16(PICA_SYS_LB_IE, mask);
165 }
166
167 /*
168 * chipset-dependent platform routines.
169 */
170
171 void
c_magnum_set_intr(uint32_t mask,uint32_t (* int_hand)(uint32_t,struct clockframe *),int prio)172 c_magnum_set_intr(uint32_t mask,
173 uint32_t (*int_hand)(uint32_t, struct clockframe *), int prio)
174 {
175
176 arc_set_intr(mask, int_hand, prio);
177
178 /* Update external interrupt mask but don't enable clock. */
179 out32(R4030_SYS_EXT_IMASK, cpu_int_mask & (~MIPS_INT_MASK_4 >> 10));
180 }
181
182 /*
183 * critial i/o space, interrupt, and other chipset related initialization.
184 */
185 void
c_magnum_init(void)186 c_magnum_init(void)
187 {
188
189 /*
190 * Initialize interrupt priority
191 */
192 ipl_sr_map = magnum_ipl_sr_map;
193
194 /*
195 * Initialize I/O address offset
196 */
197 arc_bus_space_init(&jazzio_bus, "jazzio",
198 R4030_P_LOCAL_IO_BASE, R4030_V_LOCAL_IO_BASE,
199 R4030_V_LOCAL_IO_BASE, R4030_S_LOCAL_IO_BASE);
200 arc_bus_space_init(&arc_bus_io, "picaisaio",
201 PICA_P_ISA_IO, PICA_V_ISA_IO, 0, PICA_S_ISA_IO);
202 arc_bus_space_init(&arc_bus_mem, "picaisamem",
203 PICA_P_ISA_MEM, PICA_V_ISA_MEM, 0, PICA_S_ISA_MEM);
204
205 /*
206 * Initialize wired TLB for I/O space which is used on early stage
207 */
208 arc_init_wired_map();
209 arc_wired_enter_page(R4030_V_LOCAL_IO_BASE, R4030_P_LOCAL_IO_BASE,
210 R4030_S_LOCAL_IO_BASE);
211 arc_wired_enter_page(PICA_V_INT_SOURCE, PICA_P_INT_SOURCE,
212 R4030_S_LOCAL_IO_BASE);
213
214 arc_wired_enter_page(PICA_V_ISA_IO, PICA_P_ISA_IO, PICA_S_ISA_IO);
215 arc_wired_enter_page(PICA_V_ISA_MEM, PICA_P_ISA_MEM, PICA_S_ISA_MEM);
216
217 /*
218 * Disable all interrupts. New masks will be set up
219 * during system configuration
220 */
221 out16(PICA_SYS_LB_IE,0x000);
222 out32(R4030_SYS_EXT_IMASK, 0x00);
223
224 /* common configuration for Magnum derived and NEC EISA machines */
225 c_jazz_eisa_init();
226
227 /* chipset-dependent timer configuration */
228 timer_jazzio_conf = &timer_magnum_conf;
229
230 /* chipset-dependent jazzio bus configuration */
231 jazzio_conf = &jazzio_magnum_conf;
232
233 /* chipset-dependent isa bus configuration */
234 isabr_conf = &isabr_magnum_conf;
235 }
236