1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2019 Intel Corporation 3 */ 4 5 #ifndef _OPAE_INTEL_MAX10_H_ 6 #define _OPAE_INTEL_MAX10_H_ 7 8 #include "opae_osdep.h" 9 #include "opae_spi.h" 10 #include "ifpga_compat.h" 11 12 struct intel_max10_device; 13 14 struct max10_compatible_id { 15 char compatible[128]; 16 }; 17 18 #define MAX10_PAC "intel,max10" 19 #define MAX10_PAC_N3000 "intel,max10-pac-n3000" 20 #define MAX10_PAC_END "intel,end" 21 22 /* max10 capability flags */ 23 #define MAX10_FLAGS_NO_I2C2 BIT(0) 24 #define MAX10_FLAGS_NO_BMCIMG_FLASH BIT(1) 25 #define MAX10_FLAGS_DEVICE_TABLE BIT(2) 26 #define MAX10_FLAGS_SPI BIT(3) 27 #define MAX10_FLGAS_NIOS_SPI BIT(4) 28 #define MAX10_FLAGS_PKVL BIT(5) 29 #define MAX10_FLAGS_SECURE BIT(6) 30 #define MAX10_FLAGS_MAC_CACHE BIT(7) 31 32 /** List of opae sensors */ 33 TAILQ_HEAD(opae_sensor_list, opae_sensor_info); 34 35 /* Supported MAX10 BMC types */ 36 enum m10bmc_type { 37 M10_N3000, 38 M10_N6000 39 }; 40 41 struct regmap_range { 42 unsigned int min; 43 unsigned int max; 44 }; 45 46 struct m10bmc_regmap { 47 int (*reg_write)(struct intel_max10_device *dev, 48 unsigned int reg, unsigned int val); 49 int (*reg_read)(struct intel_max10_device *dev, 50 unsigned int reg, unsigned int *val); 51 const struct regmap_range *range; 52 int num_ranges; 53 }; 54 55 struct m10bmc_csr { 56 unsigned int base; 57 unsigned int build_version; 58 unsigned int fw_version; 59 unsigned int fpga_page_info; 60 unsigned int doorbell; 61 unsigned int auth_result; 62 }; 63 64 /** 65 * struct flash_raw_blk_ops - device specific operations for flash R/W 66 * @write_blk: write a block of data to flash 67 * @read_blk: read a block of data from flash 68 */ 69 struct flash_raw_blk_ops { 70 int (*write_blk)(struct intel_max10_device *dev, uint32_t addr, 71 void *buf, uint32_t size); 72 int (*read_blk)(struct intel_max10_device *dev, uint32_t addr, 73 void *buf, uint32_t size); 74 }; 75 76 /** 77 * struct m10bmc_ops - device specific operations 78 * @lock: prevent concurrent flash read/write 79 * @mutex: prevent concurrent bmc read/write 80 * @check_flash_range: validate flash address 81 * @flash_read: read a block of data from flash 82 * @flash_write: write a block of data to flash 83 */ 84 struct m10bmc_ops { 85 pthread_mutex_t lock; 86 pthread_mutex_t *mutex; 87 int (*check_flash_range)(u32 start, u32 end); 88 int (*flash_read)(struct intel_max10_device *dev, u32 addr, 89 void *buf, u32 size); 90 int (*flash_write)(struct intel_max10_device *dev, u32 addr, 91 void *buf, u32 size); 92 }; 93 94 struct intel_max10_device { 95 unsigned int flags; /*max10 hardware capability*/ 96 struct altera_spi_device *spi_master; 97 struct spi_transaction_dev *spi_tran_dev; 98 struct max10_compatible_id *id; /*max10 compatible*/ 99 char *fdt_root; 100 unsigned int base; /* max10 base address */ 101 u16 bus; 102 struct opae_sensor_list opae_sensor_list; 103 u32 staging_area_base; 104 u32 staging_area_size; 105 enum m10bmc_type type; 106 const struct m10bmc_regmap *ops; 107 const struct m10bmc_csr *csr; 108 struct flash_raw_blk_ops raw_blk_ops; 109 struct m10bmc_ops bmc_ops; 110 u8 *mmio; /* mmio address for PMCI */ 111 }; 112 113 /* retimer speed */ 114 enum retimer_speed { 115 MXD_1GB = 1, 116 MXD_2_5GB = 2, 117 MXD_5GB = 5, 118 MXD_10GB = 10, 119 MXD_25GB = 25, 120 MXD_40GB = 40, 121 MXD_100GB = 100, 122 MXD_SPEED_UNKNOWN, 123 }; 124 125 /* retimer info */ 126 struct opae_retimer_info { 127 unsigned int nums_retimer; 128 unsigned int ports_per_retimer; 129 unsigned int nums_fvl; 130 unsigned int ports_per_fvl; 131 enum retimer_speed support_speed; 132 }; 133 134 /* retimer status*/ 135 struct opae_retimer_status { 136 enum retimer_speed speed; 137 /* 138 * retimer line link status bitmap: 139 * bit 0: Retimer0 Port0 link status 140 * bit 1: Retimer0 Port1 link status 141 * bit 2: Retimer0 Port2 link status 142 * bit 3: Retimer0 Port3 link status 143 * 144 * bit 4: Retimer1 Port0 link status 145 * bit 5: Retimer1 Port1 link status 146 * bit 6: Retimer1 Port2 link status 147 * bit 7: Retimer1 Port3 link status 148 */ 149 unsigned int line_link_bitmap; 150 }; 151 152 #define FLASH_BASE 0x10000000 153 #define FLASH_OPTION_BITS 0x10000 154 155 /* System Registers */ 156 #define MAX10_BASE_ADDR 0x300400 157 #define MAX10_SEC_BASE_ADDR 0x300800 158 159 /* Register offset of system registers */ 160 #define NIOS2_FW_VERSION 0x0 161 #define MAX10_MACADDR1 0x10 162 #define MAX10_MAC_BYTE4 GENMASK(7, 0) 163 #define MAX10_MAC_BYTE3 GENMASK(15, 8) 164 #define MAX10_MAC_BYTE2 GENMASK(23, 16) 165 #define MAX10_MAC_BYTE1 GENMASK(31, 24) 166 #define MAX10_MACADDR2 0x14 167 #define MAX10_MAC_BYTE6 GENMASK(7, 0) 168 #define MAX10_MAC_BYTE5 GENMASK(15, 8) 169 #define MAX10_MAC_COUNT GENMASK(23, 16) 170 #define RSU_REG 0x2c 171 #define FPGA_RECONF_PAGE GENMASK(2, 0) 172 #define FPGA_PAGE(p) ((p) & 0x1) 173 #define FPGA_RP_LOAD BIT(3) 174 #define NIOS2_PRERESET BIT(4) 175 #define NIOS2_HANG BIT(5) 176 #define RSU_ENABLE BIT(6) 177 #define NIOS2_RESET BIT(7) 178 #define NIOS2_I2C2_POLL_STOP BIT(13) 179 #define PKVL_EEPROM_LOAD BIT(31) 180 #define FPGA_RECONF_REG 0x30 181 #define SFPGA_RECONF_PAGE GENMASK(22, 20) 182 #define SFPGA_PAGE(p) (((p) & 0x1) << 20) 183 #define SFPGA_RP_LOAD BIT(23) 184 #define MAX10_TEST_REG 0x3c 185 #define COUNTDOWN_START BIT(18) 186 #define MAX10_BUILD_VER 0x68 187 #define MAX10_VERSION_MAJOR GENMASK(23, 16) 188 #define PCB_INFO GENMASK(31, 24) 189 #define FPGA_PAGE_INFO 0x6c 190 #define DT_AVAIL_REG 0x90 191 #define DT_AVAIL BIT(0) 192 #define DT_BASE_ADDR_REG 0x94 193 #define MAX10_DOORBELL 0x400 194 #define RSU_REQUEST BIT(0) 195 #define SEC_PROGRESS GENMASK(7, 4) 196 #define SEC_PROGRESS_G(v) (((v) >> 4) & 0xf) 197 #define SEC_PROGRESS_IDLE 0x0 198 #define SEC_PROGRESS_PREPARE 0x1 199 #define SEC_PROGRESS_SLEEP 0x2 200 #define SEC_PROGRESS_READY 0x3 201 #define SEC_PROGRESS_AUTHENTICATING 0x4 202 #define SEC_PROGRESS_COPYING 0x5 203 #define SEC_PROGRESS_UPDATE_CANCEL 0x6 204 #define SEC_PROGRESS_PROGRAM_KEY_HASH 0x7 205 #define SEC_PROGRESS_RSU_DONE 0x8 206 #define SEC_PROGRESS_PKVL_PROM_DONE 0x9 207 #define HOST_STATUS GENMASK(11, 8) 208 #define HOST_STATUS_S(v) (((v) << 8) & 0xf00) 209 #define HOST_STATUS_IDLE 0x0 210 #define HOST_STATUS_WRITE_DONE 0x1 211 #define HOST_STATUS_ABORT_RSU 0x2 212 #define SEC_STATUS GENMASK(23, 16) 213 #define SEC_STATUS_G(v) (((v) >> 16) & 0xff) 214 #define SEC_STATUS_NORMAL 0x0 215 #define SEC_STATUS_TIMEOUT 0x1 216 #define SEC_STATUS_AUTH_FAIL 0x2 217 #define SEC_STATUS_COPY_FAIL 0x3 218 #define SEC_STATUS_FATAL 0x4 219 #define SEC_STATUS_PKVL_REJECT 0x5 220 #define SEC_STATUS_NON_INC 0x6 221 #define SEC_STATUS_ERASE_FAIL 0x7 222 #define SEC_STATUS_WEAROUT 0x8 223 #define SEC_STATUS_PMCI_SS_FAIL 0x9 224 #define SEC_STATUS_FLASH_CMD 0xa 225 #define SEC_STATUS_FACTORY_UNVERITY 0xb 226 #define SEC_STATUS_FACTORY_ACTIVE 0xc 227 #define SEC_STATUS_POWER_DOWN 0xd 228 #define SEC_STATUS_CANCELLATION 0xe 229 #define SEC_STATUS_HASH 0xf 230 #define SEC_STATUS_FLASH_ACCESS 0x10 231 #define SEC_STATUS_SDM_PR_CERT 0x20 232 #define SEC_STATUS_SDM_PR_NIOS_BUSY 0x21 233 #define SEC_STATUS_SDM_PR_TIMEOUT 0x22 234 #define SEC_STATUS_SDM_PR_FAILED 0x23 235 #define SEC_STATUS_SDM_PR_MISMATCH 0x24 236 #define SEC_STATUS_SDM_PR_FLUSH 0x25 237 #define SEC_STATUS_SDM_SR_CERT 0x30 238 #define SEC_STATUS_SDM_SR_NIOS_BUSY 0x31 239 #define SEC_STATUS_SDM_SR_TIMEOUT 0x32 240 #define SEC_STATUS_SDM_SR_FAILED 0x33 241 #define SEC_STATUS_SDM_SR_MISMATCH 0x34 242 #define SEC_STATUS_SDM_SR_FLUSH 0x35 243 #define SEC_STATUS_SDM_KEY_CERT 0x40 244 #define SEC_STATUS_SDM_KEY_NIOS_BUSY 0x41 245 #define SEC_STATUS_SDM_KEY_TIMEOUT 0x42 246 #define SEC_STATUS_SDM_KEY_FAILED 0x43 247 #define SEC_STATUS_SDM_KEY_MISMATCH 0x44 248 #define SEC_STATUS_SDM_KEY_FLUSH 0x45 249 #define SEC_STATUS_NIOS_OK 0x80 250 #define SEC_STATUS_USER_OK 0x81 251 #define SEC_STATUS_FACTORY_OK 0x82 252 #define SEC_STATUS_USER_FAIL 0x83 253 #define SEC_STATUS_FACTORY_FAIL 0x84 254 #define SEC_STATUS_NIOS_FLASH_ERR 0x85 255 #define SEC_STATUS_FPGA_FLASH_ERR 0x86 256 #define SEC_STATUS_MAX SEC_STATUS_FPGA_FLASH_ERR 257 258 /* Authentication status */ 259 #define SEC_AUTH_G(v) ((v) & 0xff) 260 #define AUTH_STAT_PASS 0x0 261 #define AUTH_STAT_B0_MAGIC 0x1 262 #define AUTH_STAT_CONLEN 0x2 263 #define AUTH_STAT_CONTYPE 0x3 264 #define AUTH_STAT_B1_MAGIC 0x4 265 #define AUTH_STAT_ROOT_MAGIC 0x5 266 #define AUTH_STAT_CURVE_MAGIC 0x6 267 #define AUTH_STAT_PERMISSION 0x7 268 #define AUTH_STAT_KEY_ID 0x8 269 #define AUTH_STAT_CSK_MAGIC 0x9 270 #define AUTH_STAT_CSK_CURVE 0xa 271 #define AUTH_STAT_CSK_PERMISSION 0xb 272 #define AUTH_STAT_CSK_ID 0xc 273 #define AUTH_STAT_CSK_SM 0xd 274 #define AUTH_STAT_B0_E_MAGIC 0xe 275 #define AUTH_STAT_B0_E_SIGN 0xf 276 #define AUTH_STAT_RK_P 0x10 277 #define AUTH_STAT_RE_SHA 0x11 278 #define AUTH_STAT_CSK_SHA 0x12 279 #define AUTH_STAT_B0_SHA 0x13 280 #define AUTH_STAT_KEY_INV 0x14 281 #define AUTH_STAT_KEY_CAN 0x15 282 #define AUTH_STAT_UP_SHA 0x16 283 #define AUTH_STAT_CAN_SHA 0x17 284 #define AUTH_STAT_HASH 0x18 285 #define AUTH_STAT_INV_ID 0x19 286 #define AUTH_STAT_KEY_PROG 0x1a 287 #define AUTH_STAT_INV_BC 0x1b 288 #define AUTH_STAT_INV_SLOT 0x1c 289 #define AUTH_STAT_IN_OP 0x1d 290 #define AUTH_STAT_TIME_OUT 0X1e 291 #define AUTH_STAT_SHA_TO 0x1f 292 #define AUTH_STAT_CSK_TO 0x20 293 #define AUTH_STAT_B0_TO 0x21 294 #define AUTH_STAT_UP_TO 0x22 295 #define AUTH_STAT_CAN_TO 0x23 296 #define AUTH_STAT_HASH_TO 0x24 297 #define AUTH_STAT_AUTH_IDLE 0xfe 298 #define AUTH_STAT_GA_FAIL 0xff 299 #define AUTH_STAT_S_ERR 0x8000 300 #define AUTH_STAT_S_MN 0x8001 301 #define AUTH_STAT_SH_CRC 0x8002 302 #define AUTH_STAT_SD_CRC 0x8003 303 #define AUTH_STAT_SD_LEN 0x8004 304 #define AUTH_STAT_S_ID 0x8005 305 #define AUTH_STAT_S_THR 0x8006 306 #define AUTH_STAT_S_TO 0x8007 307 #define AUTH_STAT_S_EN 0x8008 308 #define AUTH_STAT_SF 0x8009 309 #define AUTH_STAT_MAX AUTH_STAT_SF 310 311 #define CONFIG_SEL BIT(28) 312 #define CONFIG_SEL_S(v) (((v) & 0x1) << 28) 313 #define REBOOT_REQ BIT(29) 314 #define REBOOT_DISABLED BIT(30) 315 #define MAX10_AUTH_RESULT 0x404 316 317 /* PKVL related registers, in system register region */ 318 #define PKVL_POLLING_CTRL 0x80 319 #define POLLING_MODE GENMASK(15, 0) 320 #define PKVL_A_PRELOAD BIT(16) 321 #define PKVL_A_PRELOAD_TIMEOUT BIT(17) 322 #define PKVL_A_DATA_TOO_BIG BIT(18) 323 #define PKVL_A_HDR_CHECKSUM BIT(20) 324 #define PKVL_B_PRELOAD BIT(24) 325 #define PKVL_B_PRELOAD_TIMEOUT BIT(25) 326 #define PKVL_B_DATA_TOO_BIG BIT(26) 327 #define PKVL_B_HDR_CHECKSUM BIT(28) 328 #define PKVL_EEPROM_UPG_STATUS GENMASK(31, 16) 329 #define PKVL_LINK_STATUS 0x164 330 #define PKVL_A_VERSION 0x254 331 #define PKVL_B_VERSION 0x258 332 #define SERDES_VERSION GENMASK(15, 0) 333 #define SBUS_VERSION GENMASK(31, 16) 334 335 #define DFT_MAX_SIZE 0x7e0000 336 #define MAX_STAGING_AREA_BASE 0xffffffff 337 #define MAX_STAGING_AREA_SIZE 0x3800000 338 339 #define m10bmc_base(max10) ((max10)->csr->base) 340 #define doorbell_reg(max10) ((max10)->csr->doorbell) 341 #define auth_result_reg(max10) ((max10)->csr->auth_result) 342 343 int max10_sys_read(struct intel_max10_device *dev, 344 unsigned int offset, unsigned int *val); 345 int max10_sys_write(struct intel_max10_device *dev, 346 unsigned int offset, unsigned int val); 347 int max10_reg_read(struct intel_max10_device *dev, 348 unsigned int offset, unsigned int *val); 349 int max10_reg_write(struct intel_max10_device *dev, 350 unsigned int offset, unsigned int val); 351 int max10_sys_update_bits(struct intel_max10_device *dev, 352 unsigned int offset, unsigned int msk, unsigned int val); 353 int max10_get_bmcfw_version(struct intel_max10_device *dev, unsigned int *val); 354 int max10_get_bmc_version(struct intel_max10_device *dev, unsigned int *val); 355 int max10_get_fpga_load_info(struct intel_max10_device *dev, unsigned int *val); 356 int intel_max10_device_init(struct intel_max10_device *dev); 357 int intel_max10_device_remove(struct intel_max10_device *dev); 358 359 360 #define SENSOR_REG_VALUE 0x0 361 #define SENSOR_REG_HIGH_WARN 0x1 362 #define SENSOR_REG_HIGH_FATAL 0x2 363 #define SENSOR_REG_LOW_WARN 0x3 364 #define SENSOR_REG_LOW_FATAL 0x4 365 #define SENSOR_REG_HYSTERESIS 0x5 366 #define SENSOR_REG_MAX 0x6 367 368 static const char * const sensor_reg_name[] = { 369 "value", 370 "high_warn", 371 "high_fatal", 372 "low_warn", 373 "low_fatal", 374 "hysteresis", 375 }; 376 377 struct sensor_reg { 378 unsigned int regoff; 379 size_t size; 380 }; 381 382 struct raw_sensor_info { 383 const char *name; 384 const char *type; 385 unsigned int id; 386 unsigned int multiplier; 387 struct sensor_reg regs[SENSOR_REG_MAX]; 388 }; 389 390 #define OPAE_SENSOR_VALID 0x1 391 #define OPAE_SENSOR_HIGH_WARN_VALID 0x2 392 #define OPAE_SENSOR_HIGH_FATAL_VALID 0x4 393 #define OPAE_SENSOR_LOW_WARN_VALID 0x8 394 #define OPAE_SENSOR_LOW_FATAL_VALID 0x10 395 #define OPAE_SENSOR_HYSTERESIS_VALID 0x20 396 397 struct opae_sensor_info { 398 TAILQ_ENTRY(opae_sensor_info) node; 399 const char *name; 400 const char *type; 401 unsigned int id; 402 unsigned int high_fatal; 403 unsigned int high_warn; 404 unsigned int low_fatal; 405 unsigned int low_warn; 406 unsigned int hysteresis; 407 unsigned int multiplier; 408 unsigned int flags; 409 unsigned int value; 410 unsigned int value_reg; 411 }; 412 413 #define SENSOR_INVALID 0xdeadbeef 414 415 struct max10_sensor_raw_data { 416 unsigned int reg_input; 417 unsigned int reg_high_warn; 418 unsigned int reg_high_fatal; 419 unsigned int reg_hyst; 420 unsigned int reg_low_warn; 421 unsigned int multiplier; 422 const char *label; 423 }; 424 425 struct max10_sensor_data { 426 const char *type; 427 unsigned int number; 428 const struct max10_sensor_raw_data *table; 429 }; 430 431 enum max10_sensor_types { 432 sensor_temp, 433 sensor_in, 434 sensor_curr, 435 sensor_power, 436 sensor_max, 437 }; 438 439 #define SENSOR_TMP_NAME "Temperature" 440 #define SENSOR_IN_NAME "Voltage" 441 #define SENSOR_CURR_NAME "Current" 442 #define SENSOR_POWER_NAME "Power" 443 444 struct max10_sensor_board_data { 445 const struct max10_sensor_data *tables[sensor_max]; 446 }; 447 448 /* indirect access for PMCI */ 449 #define PMCI_INDIRECT_BASE 0x400 450 #define INDIRECT_CMD_OFF (PMCI_INDIRECT_BASE + 0x0) 451 #define INDIRECT_CMD_RD BIT(0) 452 #define INDIRECT_CMD_WR BIT(1) 453 #define INDIRECT_CMD_ACK BIT(2) 454 455 #define INDIRECT_ADDR_OFF (PMCI_INDIRECT_BASE + 0x4) 456 #define INDIRECT_RD_OFF (PMCI_INDIRECT_BASE + 0x8) 457 #define INDIRECT_WR_OFF (PMCI_INDIRECT_BASE + 0xc) 458 459 #define INDIRECT_INT_US 1 460 #define INDIRECT_TIMEOUT_US 10000 461 462 #define M10BMC_PMCI_SYS_BASE 0x0 463 #define M10BMC_PMCI_SYS_END 0xfff 464 465 #define M10BMC_PMCI_BUILD_VER 0x0 466 #define NIOS2_PMCI_FW_VERSION 0x4 467 468 #define M10BMC_PMCI_PWR_STATE 0xb4 469 #define PMCI_PRIMARY_IMAGE_PAGE GENMASK(10, 8) 470 471 #define M10BMC_PMCI_DOORBELL 0x1c0 472 #define PMCI_DRBL_REBOOT_DISABLED BIT(1) 473 #define M10BMC_PMCI_AUTH_RESULT 0x1c4 474 475 #define M10BMC_PMCI_MAX10_RECONF 0xfc 476 #define PMCI_MAX10_REBOOT_REQ BIT(0) 477 #define PMCI_MAX10_REBOOT_PAGE BIT(1) 478 479 #define M10BMC_PMCI_FPGA_RECONF 0xb8 480 #define PMCI_FPGA_RECONF_PAGE GENMASK(22, 20) 481 #define PMCI_FPGA_RP_LOAD BIT(23) 482 483 #define PMCI_FLASH_CTRL 0x40 484 #define PMCI_FLASH_WR_MODE BIT(0) 485 #define PMCI_FLASH_RD_MODE BIT(1) 486 #define PMCI_FLASH_BUSY BIT(2) 487 #define PMCI_FLASH_FIFO_SPACE GENMASK(13, 4) 488 #define PMCI_FLASH_READ_COUNT GENMASK(25, 16) 489 490 #define PMCI_FLASH_INT_US 1 491 #define PMCI_FLASH_TIMEOUT_US 10000 492 493 #define PMCI_FLASH_ADDR 0x44 494 #define PMCI_FLASH_FIFO 0x800 495 #define PMCI_READ_BLOCK_SIZE 0x800 496 #define PMCI_FIFO_MAX_BYTES 0x800 497 #define PMCI_FIFO_MAX_WORDS (PMCI_FIFO_MAX_BYTES / 4) 498 499 #define M10BMC_PMCI_FPGA_POC 0xb0 500 #define PMCI_FPGA_POC BIT(0) 501 #define PMCI_NIOS_REQ_CLEAR BIT(1) 502 #define PMCI_NIOS_STATUS GENMASK(5, 4) 503 #define NIOS_STATUS_IDLE 0 504 #define NIOS_STATUS_SUCCESS 1 505 #define NIOS_STATUS_FAIL 2 506 #define PMCI_USER_IMAGE_PAGE GENMASK(10, 8) 507 #define POC_USER_IMAGE_1 1 508 #define POC_USER_IMAGE_2 2 509 #define PMCI_FACTORY_IMAGE_SEL BIT(31) 510 511 #define M10BMC_PMCI_FPGA_CONF_STS 0xa0 512 #define PMCI_FPGA_BOOT_PAGE GENMASK(2, 0) 513 #define PMCI_FPGA_CONFIGURED BIT(3) 514 515 #define M10BMC_PMCI_FLASH_CTRL 0x1d0 516 #define FLASH_MUX_SELECTION GENMASK(2, 0) 517 #define FLASH_MUX_IDLE 0 518 #define FLASH_MUX_NIOS 1 519 #define FLASH_MUX_HOST 2 520 #define FLASH_MUX_PFL 4 521 #define get_flash_mux(mux) GET_FIELD(FLASH_MUX_SELECTION, mux) 522 #define FLASH_NIOS_REQUEST BIT(4) 523 #define FLASH_HOST_REQUEST BIT(5) 524 525 #define M10BMC_PMCI_SDM_CTRL_STS 0x230 526 #define PMCI_SDM_IMG_REQ BIT(0) 527 #define PMCI_SDM_STAT GENMASK(23, 16) 528 529 #define SDM_STAT_DONE 0x0 530 #define SDM_STAT_PROV 0x1 531 #define SDM_STAT_BUSY 0x2 532 #define SDM_STAT_INV 0x3 533 #define SDM_STAT_FAIL 0x4 534 #define SDM_STAT_BMC_BUSY 0x5 535 #define SDM_STAT_TO 0x6 536 #define SDM_STAT_DB 0x7 537 #define SDM_STAT_CON_R 0x8 538 #define SDM_STAT_CON_E 0x9 539 #define SDM_STAT_WAIT 0xa 540 #define SDM_STAT_RTO 0xb 541 #define SDM_STAT_SB 0xc 542 #define SDM_STAT_RE 0xd 543 #define SDM_STAT_PDD 0xe 544 #define SDM_STAT_ISC 0xf 545 #define SDM_STAT_SIC 0x10 546 #define SDM_STAT_NO_PROV 0x11 547 #define SDM_STAT_CS_MIS 0x12 548 #define SDM_STAT_PR_MIS 0x13 549 #define SDM_STAT_MAX SDM_STAT_PR_MIS 550 551 #define PMCI_FLASH_START 0x10000 552 #define PMCI_FLASH_END 0xC7FFFFF 553 554 int opae_read_flash(struct intel_max10_device *dev, u32 addr, 555 u32 size, void *buf); 556 #endif 557