1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) 2 * 3 * Copyright 2008-2016 Freescale Semiconductor Inc. 4 * Copyright 2017 NXP 5 * 6 */ 7 8 #ifndef __BMAN_PRIV_H 9 #define __BMAN_PRIV_H 10 11 #include "dpaa_sys.h" 12 #include <fsl_bman.h> 13 14 /* Revision info (for errata and feature handling) */ 15 #define BMAN_REV10 0x0100 16 #define BMAN_REV20 0x0200 17 #define BMAN_REV21 0x0201 18 19 #define BMAN_PORTAL_IRQ_PATH "/dev/fsl-usdpaa-irq" 20 #define BMAN_CCSR_MAP "/dev/mem" 21 22 /* This mask contains all the "irqsource" bits visible to API users */ 23 #define BM_PIRQ_VISIBLE (BM_PIRQ_RCRI | BM_PIRQ_BSCN) 24 25 /* These are bm_<reg>_<verb>(). So for example, bm_disable_write() means "write 26 * the disable register" rather than "disable the ability to write". 27 */ 28 #define bm_isr_status_read(bm) __bm_isr_read(bm, bm_isr_status) 29 #define bm_isr_status_clear(bm, m) __bm_isr_write(bm, bm_isr_status, m) 30 #define bm_isr_enable_read(bm) __bm_isr_read(bm, bm_isr_enable) 31 #define bm_isr_enable_write(bm, v) __bm_isr_write(bm, bm_isr_enable, v) 32 #define bm_isr_disable_read(bm) __bm_isr_read(bm, bm_isr_disable) 33 #define bm_isr_disable_write(bm, v) __bm_isr_write(bm, bm_isr_disable, v) 34 #define bm_isr_inhibit(bm) __bm_isr_write(bm, bm_isr_inhibit, 1) 35 #define bm_isr_uninhibit(bm) __bm_isr_write(bm, bm_isr_inhibit, 0) 36 37 /* 38 * Global variables of the max portal/pool number this bman version supported 39 */ 40 extern u16 bman_pool_max; 41 42 /* used by CCSR and portal interrupt code */ 43 enum bm_isr_reg { 44 bm_isr_status = 0, 45 bm_isr_enable = 1, 46 bm_isr_disable = 2, 47 bm_isr_inhibit = 3 48 }; 49 50 struct bm_portal_config { 51 /* 52 * Corenet portal addresses; 53 * [0]==cache-enabled, [1]==cache-inhibited. 54 */ 55 void __iomem *addr_virt[2]; 56 /* Allow these to be joined in lists */ 57 struct list_head list; 58 /* User-visible portal configuration settings */ 59 /* This is used for any "core-affine" portals, ie. default portals 60 * associated to the corresponding cpu. -1 implies that there is no 61 * core affinity configured. 62 */ 63 int cpu; 64 /* portal interrupt line */ 65 int irq; 66 /* the unique index of this portal */ 67 u32 index; 68 /* Is this portal shared? (If so, it has coarser locking and demuxes 69 * processing on behalf of other CPUs.). 70 */ 71 int is_shared; 72 /* These are the buffer pool IDs that may be used via this portal. */ 73 struct bman_depletion mask; 74 75 }; 76 77 int bman_init_ccsr(const struct device_node *node); 78 79 struct bman_portal *bman_create_affine_portal( 80 const struct bm_portal_config *config); 81 const struct bm_portal_config *bman_destroy_affine_portal(void); 82 83 /* Set depletion thresholds associated with a buffer pool. Requires that the 84 * operating system have access to Bman CCSR (ie. compiled in support and 85 * run-time access courtesy of the device-tree). 86 */ 87 int bm_pool_set(u32 bpid, const u32 *thresholds); 88 89 /* Read the free buffer count for a given buffer */ 90 u32 bm_pool_free_buffers(u32 bpid); 91 92 #endif /* __BMAN_PRIV_H */ 93