1 /* $NetBSD: ch7006_priv.h,v 1.3 2021/12/18 23:45:27 riastradh Exp $ */
2
3 /*
4 * Copyright (C) 2009 Francisco Jerez.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sublicense, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
23 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
24 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
25 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #ifndef __DRM_I2C_CH7006_PRIV_H__
30 #define __DRM_I2C_CH7006_PRIV_H__
31
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_encoder_slave.h>
34 #include <drm/drm_probe_helper.h>
35 #include <drm/i2c/ch7006.h>
36
37 typedef int64_t fixed;
38 #define fixed1 (1LL << 32)
39
40 enum ch7006_tv_norm {
41 TV_NORM_PAL,
42 TV_NORM_PAL_M,
43 TV_NORM_PAL_N,
44 TV_NORM_PAL_NC,
45 TV_NORM_PAL_60,
46 TV_NORM_NTSC_M,
47 TV_NORM_NTSC_J,
48 NUM_TV_NORMS
49 };
50
51 struct ch7006_tv_norm_info {
52 fixed vrefresh;
53 int vdisplay;
54 int vtotal;
55 int hvirtual;
56
57 fixed subc_freq;
58 fixed black_level;
59
60 uint32_t dispmode;
61 int voffset;
62 };
63
64 struct ch7006_mode {
65 struct drm_display_mode mode;
66
67 int enc_hdisp;
68 int enc_vdisp;
69
70 fixed subc_coeff;
71 uint32_t dispmode;
72
73 uint32_t valid_scales;
74 uint32_t valid_norms;
75 };
76
77 struct ch7006_state {
78 uint8_t regs[0x26];
79 };
80
81 struct ch7006_priv {
82 struct ch7006_encoder_params params;
83 const struct ch7006_mode *mode;
84
85 struct ch7006_state state;
86 struct ch7006_state saved_state;
87
88 struct drm_property *scale_property;
89
90 int select_subconnector;
91 int subconnector;
92 int hmargin;
93 int vmargin;
94 enum ch7006_tv_norm norm;
95 int brightness;
96 int contrast;
97 int flicker;
98 int scale;
99
100 int chip_version;
101 int last_dpms;
102 };
103
104 #define to_ch7006_priv(x) \
105 ((struct ch7006_priv *)to_encoder_slave(x)->slave_priv)
106
107 extern int ch7006_debug;
108 extern char *ch7006_tv_norm;
109 extern int ch7006_scale;
110
111 extern const char * const ch7006_tv_norm_names[];
112 extern const struct ch7006_tv_norm_info ch7006_tv_norms[];
113 extern const struct ch7006_mode ch7006_modes[];
114
115 const struct ch7006_mode *ch7006_lookup_mode(struct drm_encoder *encoder,
116 const struct drm_display_mode *drm_mode);
117
118 void ch7006_setup_levels(struct drm_encoder *encoder);
119 void ch7006_setup_subcarrier(struct drm_encoder *encoder);
120 void ch7006_setup_pll(struct drm_encoder *encoder);
121 void ch7006_setup_power_state(struct drm_encoder *encoder);
122 void ch7006_setup_properties(struct drm_encoder *encoder);
123
124 void ch7006_write(struct i2c_client *client, uint8_t addr, uint8_t val);
125 uint8_t ch7006_read(struct i2c_client *client, uint8_t addr);
126
127 void ch7006_state_load(struct i2c_client *client,
128 struct ch7006_state *state);
129 void ch7006_state_save(struct i2c_client *client,
130 struct ch7006_state *state);
131
132 /* Some helper macros */
133
134 #define ch7006_dbg(client, format, ...) do { \
135 if (ch7006_debug) \
136 dev_printk(KERN_DEBUG, &client->dev, \
137 "%s: " format, __func__, ## __VA_ARGS__); \
138 } while (0)
139 #define ch7006_info(client, format, ...) \
140 dev_info(&client->dev, format, __VA_ARGS__)
141 #define ch7006_err(client, format, ...) \
142 dev_err(&client->dev, format, __VA_ARGS__)
143
144 #define __mask(src, bitfield) \
145 (((2 << (1 ? bitfield)) - 1) & ~((1 << (0 ? bitfield)) - 1))
146 #define mask(bitfield) __mask(bitfield)
147
148 #define __bitf(src, bitfield, x) \
149 (((x) >> (src) << (0 ? bitfield)) & __mask(src, bitfield))
150 #define bitf(bitfield, x) __bitf(bitfield, x)
151 #define bitfs(bitfield, s) __bitf(bitfield, bitfield##_##s)
152 #define setbitf(state, reg, bitfield, x) \
153 state->regs[reg] = (state->regs[reg] & ~mask(reg##_##bitfield)) \
154 | bitf(reg##_##bitfield, x)
155
156 #define __unbitf(src, bitfield, x) \
157 ((x & __mask(src, bitfield)) >> (0 ? bitfield) << (src))
158 #define unbitf(bitfield, x) __unbitf(bitfield, x)
159
interpolate(int y0,int y1,int y2,int x)160 static inline int interpolate(int y0, int y1, int y2, int x)
161 {
162 return y1 + (x < 50 ? y1 - y0 : y2 - y1) * (x - 50) / 50;
163 }
164
round_fixed(fixed x)165 static inline int32_t round_fixed(fixed x)
166 {
167 return (x + fixed1/2) >> 32;
168 }
169
170 #define ch7006_load_reg(client, state, reg) ch7006_write(client, reg, state->regs[reg])
171 #define ch7006_save_reg(client, state, reg) state->regs[reg] = ch7006_read(client, reg)
172
173 /* Fixed hardware specs */
174
175 #define CH7006_FREQ0 14318
176 #define CH7006_MAXN 650
177 #define CH7006_MAXM 315
178
179 /* Register definitions */
180
181 #define CH7006_DISPMODE 0x00
182 #define CH7006_DISPMODE_INPUT_RES 0, 7:5
183 #define CH7006_DISPMODE_INPUT_RES_512x384 0x0
184 #define CH7006_DISPMODE_INPUT_RES_720x400 0x1
185 #define CH7006_DISPMODE_INPUT_RES_640x400 0x2
186 #define CH7006_DISPMODE_INPUT_RES_640x480 0x3
187 #define CH7006_DISPMODE_INPUT_RES_800x600 0x4
188 #define CH7006_DISPMODE_INPUT_RES_NATIVE 0x5
189 #define CH7006_DISPMODE_OUTPUT_STD 0, 4:3
190 #define CH7006_DISPMODE_OUTPUT_STD_PAL 0x0
191 #define CH7006_DISPMODE_OUTPUT_STD_NTSC 0x1
192 #define CH7006_DISPMODE_OUTPUT_STD_PAL_M 0x2
193 #define CH7006_DISPMODE_OUTPUT_STD_NTSC_J 0x3
194 #define CH7006_DISPMODE_SCALING_RATIO 0, 2:0
195 #define CH7006_DISPMODE_SCALING_RATIO_5_4 0x0
196 #define CH7006_DISPMODE_SCALING_RATIO_1_1 0x1
197 #define CH7006_DISPMODE_SCALING_RATIO_7_8 0x2
198 #define CH7006_DISPMODE_SCALING_RATIO_5_6 0x3
199 #define CH7006_DISPMODE_SCALING_RATIO_3_4 0x4
200 #define CH7006_DISPMODE_SCALING_RATIO_7_10 0x5
201
202 #define CH7006_FFILTER 0x01
203 #define CH7006_FFILTER_TEXT 0, 5:4
204 #define CH7006_FFILTER_LUMA 0, 3:2
205 #define CH7006_FFILTER_CHROMA 0, 1:0
206 #define CH7006_FFILTER_CHROMA_NO_DCRAWL 0x3
207
208 #define CH7006_BWIDTH 0x03
209 #define CH7006_BWIDTH_5L_FFILER (1 << 7)
210 #define CH7006_BWIDTH_CVBS_NO_CHROMA (1 << 6)
211 #define CH7006_BWIDTH_CHROMA 0, 5:4
212 #define CH7006_BWIDTH_SVIDEO_YPEAK (1 << 3)
213 #define CH7006_BWIDTH_SVIDEO_LUMA 0, 2:1
214 #define CH7006_BWIDTH_CVBS_LUMA 0, 0:0
215
216 #define CH7006_INPUT_FORMAT 0x04
217 #define CH7006_INPUT_FORMAT_DAC_GAIN (1 << 6)
218 #define CH7006_INPUT_FORMAT_RGB_PASS_THROUGH (1 << 5)
219 #define CH7006_INPUT_FORMAT_FORMAT 0, 3:0
220 #define CH7006_INPUT_FORMAT_FORMAT_RGB16 0x0
221 #define CH7006_INPUT_FORMAT_FORMAT_YCrCb24m16 0x1
222 #define CH7006_INPUT_FORMAT_FORMAT_RGB24m16 0x2
223 #define CH7006_INPUT_FORMAT_FORMAT_RGB15 0x3
224 #define CH7006_INPUT_FORMAT_FORMAT_RGB24m12C 0x4
225 #define CH7006_INPUT_FORMAT_FORMAT_RGB24m12I 0x5
226 #define CH7006_INPUT_FORMAT_FORMAT_RGB24m8 0x6
227 #define CH7006_INPUT_FORMAT_FORMAT_RGB16m8 0x7
228 #define CH7006_INPUT_FORMAT_FORMAT_RGB15m8 0x8
229 #define CH7006_INPUT_FORMAT_FORMAT_YCrCb24m8 0x9
230
231 #define CH7006_CLKMODE 0x06
232 #define CH7006_CLKMODE_SUBC_LOCK (1 << 7)
233 #define CH7006_CLKMODE_MASTER (1 << 6)
234 #define CH7006_CLKMODE_POS_EDGE (1 << 4)
235 #define CH7006_CLKMODE_XCM 0, 3:2
236 #define CH7006_CLKMODE_PCM 0, 1:0
237
238 #define CH7006_START_ACTIVE 0x07
239 #define CH7006_START_ACTIVE_0 0, 7:0
240
241 #define CH7006_POV 0x08
242 #define CH7006_POV_START_ACTIVE_8 8, 2:2
243 #define CH7006_POV_HPOS_8 8, 1:1
244 #define CH7006_POV_VPOS_8 8, 0:0
245
246 #define CH7006_BLACK_LEVEL 0x09
247 #define CH7006_BLACK_LEVEL_0 0, 7:0
248
249 #define CH7006_HPOS 0x0a
250 #define CH7006_HPOS_0 0, 7:0
251
252 #define CH7006_VPOS 0x0b
253 #define CH7006_VPOS_0 0, 7:0
254
255 #define CH7006_INPUT_SYNC 0x0d
256 #define CH7006_INPUT_SYNC_EMBEDDED (1 << 3)
257 #define CH7006_INPUT_SYNC_OUTPUT (1 << 2)
258 #define CH7006_INPUT_SYNC_PVSYNC (1 << 1)
259 #define CH7006_INPUT_SYNC_PHSYNC (1 << 0)
260
261 #define CH7006_POWER 0x0e
262 #define CH7006_POWER_SCART (1 << 4)
263 #define CH7006_POWER_RESET (1 << 3)
264 #define CH7006_POWER_LEVEL 0, 2:0
265 #define CH7006_POWER_LEVEL_CVBS_OFF 0x0
266 #define CH7006_POWER_LEVEL_POWER_OFF 0x1
267 #define CH7006_POWER_LEVEL_SVIDEO_OFF 0x2
268 #define CH7006_POWER_LEVEL_NORMAL 0x3
269 #define CH7006_POWER_LEVEL_FULL_POWER_OFF 0x4
270
271 #define CH7006_DETECT 0x10
272 #define CH7006_DETECT_SVIDEO_Y_TEST (1 << 3)
273 #define CH7006_DETECT_SVIDEO_C_TEST (1 << 2)
274 #define CH7006_DETECT_CVBS_TEST (1 << 1)
275 #define CH7006_DETECT_SENSE (1 << 0)
276
277 #define CH7006_CONTRAST 0x11
278 #define CH7006_CONTRAST_0 0, 2:0
279
280 #define CH7006_PLLOV 0x13
281 #define CH7006_PLLOV_N_8 8, 2:1
282 #define CH7006_PLLOV_M_8 8, 0:0
283
284 #define CH7006_PLLM 0x14
285 #define CH7006_PLLM_0 0, 7:0
286
287 #define CH7006_PLLN 0x15
288 #define CH7006_PLLN_0 0, 7:0
289
290 #define CH7006_BCLKOUT 0x17
291
292 #define CH7006_SUBC_INC0 0x18
293 #define CH7006_SUBC_INC0_28 28, 3:0
294
295 #define CH7006_SUBC_INC1 0x19
296 #define CH7006_SUBC_INC1_24 24, 3:0
297
298 #define CH7006_SUBC_INC2 0x1a
299 #define CH7006_SUBC_INC2_20 20, 3:0
300
301 #define CH7006_SUBC_INC3 0x1b
302 #define CH7006_SUBC_INC3_GPIO1_VAL (1 << 7)
303 #define CH7006_SUBC_INC3_GPIO0_VAL (1 << 6)
304 #define CH7006_SUBC_INC3_POUT_3_3V (1 << 5)
305 #define CH7006_SUBC_INC3_POUT_INV (1 << 4)
306 #define CH7006_SUBC_INC3_16 16, 3:0
307
308 #define CH7006_SUBC_INC4 0x1c
309 #define CH7006_SUBC_INC4_GPIO1_IN (1 << 7)
310 #define CH7006_SUBC_INC4_GPIO0_IN (1 << 6)
311 #define CH7006_SUBC_INC4_DS_INPUT (1 << 4)
312 #define CH7006_SUBC_INC4_12 12, 3:0
313
314 #define CH7006_SUBC_INC5 0x1d
315 #define CH7006_SUBC_INC5_8 8, 3:0
316
317 #define CH7006_SUBC_INC6 0x1e
318 #define CH7006_SUBC_INC6_4 4, 3:0
319
320 #define CH7006_SUBC_INC7 0x1f
321 #define CH7006_SUBC_INC7_0 0, 3:0
322
323 #define CH7006_PLL_CONTROL 0x20
324 #define CH7006_PLL_CONTROL_CPI (1 << 5)
325 #define CH7006_PLL_CONTROL_CAPACITOR (1 << 4)
326 #define CH7006_PLL_CONTROL_7STAGES (1 << 3)
327 #define CH7006_PLL_CONTROL_DIGITAL_5V (1 << 2)
328 #define CH7006_PLL_CONTROL_ANALOG_5V (1 << 1)
329 #define CH7006_PLL_CONTROL_MEMORY_5V (1 << 0)
330
331 #define CH7006_CALC_SUBC_INC0 0x21
332 #define CH7006_CALC_SUBC_INC0_24 24, 4:3
333 #define CH7006_CALC_SUBC_INC0_HYST 0, 2:1
334 #define CH7006_CALC_SUBC_INC0_AUTO (1 << 0)
335
336 #define CH7006_CALC_SUBC_INC1 0x22
337 #define CH7006_CALC_SUBC_INC1_16 16, 7:0
338
339 #define CH7006_CALC_SUBC_INC2 0x23
340 #define CH7006_CALC_SUBC_INC2_8 8, 7:0
341
342 #define CH7006_CALC_SUBC_INC3 0x24
343 #define CH7006_CALC_SUBC_INC3_0 0, 7:0
344
345 #define CH7006_VERSION_ID 0x25
346
347 #endif
348