1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 */ 31 32 #include <sys/cdefs.h> 33 /* 34 * Broadcom Common PCIe-G2 Support. 35 * 36 * This base driver implementation is shared by the bhnd_pcib_g2 (root complex) 37 * and bhnd_pci_hostb_g2 (host bridge) drivers. 38 */ 39 40 #include <sys/param.h> 41 #include <sys/malloc.h> 42 #include <sys/kernel.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/systm.h> 46 47 #include <machine/bus.h> 48 #include <sys/rman.h> 49 #include <machine/resource.h> 50 51 #include <dev/bhnd/bhnd.h> 52 #include <dev/mdio/mdio.h> 53 54 #include "bhnd_pcie2_reg.h" 55 #include "bhnd_pcie2_var.h" 56 57 static struct bhnd_device_quirk bhnd_pcie2_quirks[]; 58 59 #define BHND_PCIE_DEV(_core, _desc, ...) \ 60 BHND_DEVICE(BCM, _core, _desc, bhnd_pcie2_quirks, ## __VA_ARGS__) 61 62 static const struct bhnd_device bhnd_pcie2_devs[] = { 63 BHND_PCIE_DEV(PCIE2, "PCIe-G2 Host-PCI bridge", BHND_DF_HOSTB), 64 BHND_PCIE_DEV(PCIE2, "PCIe-G2 PCI-BHND bridge", BHND_DF_SOC), 65 66 BHND_DEVICE_END 67 }; 68 69 /* Device quirks tables */ 70 static struct bhnd_device_quirk bhnd_pcie2_quirks[] = { 71 BHND_DEVICE_QUIRK_END 72 }; 73 74 int 75 bhnd_pcie2_generic_probe(device_t dev) 76 { 77 const struct bhnd_device *id; 78 79 id = bhnd_device_lookup(dev, bhnd_pcie2_devs, 80 sizeof(bhnd_pcie2_devs[0])); 81 if (id == NULL) 82 return (ENXIO); 83 84 bhnd_set_custom_core_desc(dev, id->desc); 85 return (BUS_PROBE_DEFAULT); 86 } 87 88 int 89 bhnd_pcie2_generic_attach(device_t dev) 90 { 91 struct bhnd_pcie2_softc *sc; 92 93 sc = device_get_softc(dev); 94 sc->dev = dev; 95 sc->quirks = bhnd_device_quirks(dev, bhnd_pcie2_devs, 96 sizeof(bhnd_pcie2_devs[0])); 97 98 /* Allocate bus resources */ 99 sc->mem_res = bhnd_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, 100 RF_ACTIVE); 101 if (sc->mem_res == NULL) 102 return (ENXIO); 103 104 BHND_PCIE2_LOCK_INIT(sc); 105 106 /* Probe and attach children */ 107 bus_attach_children(dev); 108 109 return (0); 110 } 111 112 int 113 bhnd_pcie2_generic_detach(device_t dev) 114 { 115 struct bhnd_pcie2_softc *sc; 116 int error; 117 118 sc = device_get_softc(dev); 119 120 if ((error = bus_generic_detach(dev))) 121 return (error); 122 123 bhnd_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem_res); 124 125 BHND_PCIE2_LOCK_DESTROY(sc); 126 127 return (0); 128 } 129 130 static struct resource_list * 131 bhnd_pcie2_get_resource_list(device_t dev, device_t child) 132 { 133 struct bhnd_pcie2_devinfo *dinfo; 134 135 if (device_get_parent(child) != dev) 136 return (NULL); 137 138 dinfo = device_get_ivars(child); 139 return (&dinfo->resources); 140 } 141 142 static device_t 143 bhnd_pcie2_add_child(device_t dev, u_int order, const char *name, int unit) 144 { 145 struct bhnd_pcie2_devinfo *dinfo; 146 device_t child; 147 148 child = device_add_child_ordered(dev, order, name, unit); 149 if (child == NULL) 150 return (NULL); 151 152 dinfo = malloc(sizeof(struct bhnd_pcie2_devinfo), M_DEVBUF, M_NOWAIT); 153 if (dinfo == NULL) { 154 device_delete_child(dev, child); 155 return (NULL); 156 } 157 158 resource_list_init(&dinfo->resources); 159 160 device_set_ivars(child, dinfo); 161 return (child); 162 } 163 164 static void 165 bhnd_pcie2_child_deleted(device_t dev, device_t child) 166 { 167 struct bhnd_pcie2_devinfo *dinfo; 168 169 if (device_get_parent(child) != dev) 170 return; 171 172 dinfo = device_get_ivars(child); 173 if (dinfo != NULL) { 174 resource_list_free(&dinfo->resources); 175 free(dinfo, M_DEVBUF); 176 } 177 178 device_set_ivars(child, NULL); 179 } 180 181 int 182 bhnd_pcie2_generic_suspend(device_t dev) 183 { 184 return (bus_generic_suspend(dev)); 185 } 186 187 int 188 bhnd_pcie2_generic_resume(device_t dev) 189 { 190 return (bus_generic_resume(dev)); 191 } 192 193 /** 194 * Read a 32-bit PCIe TLP/DLLP/PLP protocol register. 195 * 196 * @param sc The bhndb_pci driver state. 197 * @param addr The protocol register offset. 198 */ 199 uint32_t 200 bhnd_pcie2_read_proto_reg(struct bhnd_pcie2_softc *sc, uint32_t addr) 201 { 202 // TODO 203 return (ENXIO); 204 } 205 206 /** 207 * Write a 32-bit PCIe TLP/DLLP/PLP protocol register value. 208 * 209 * @param sc The bhndb_pci driver state. 210 * @param addr The protocol register offset. 211 * @param val The value to write to @p addr. 212 */ 213 void 214 bhnd_pcie2_write_proto_reg(struct bhnd_pcie2_softc *sc, uint32_t addr, 215 uint32_t val) 216 { 217 // TODO 218 panic("unimplemented"); 219 } 220 221 int 222 bhnd_pcie2_mdio_read(struct bhnd_pcie2_softc *sc, int phy, int reg) 223 { 224 // TODO 225 return (ENXIO); 226 } 227 228 int 229 bhnd_pcie2_mdio_write(struct bhnd_pcie2_softc *sc, int phy, int reg, int val) 230 { 231 // TODO 232 return (ENXIO); 233 } 234 235 int 236 bhnd_pcie2_mdio_read_ext(struct bhnd_pcie2_softc *sc, int phy, int devaddr, 237 int reg) 238 { 239 // TODO 240 return (ENXIO); 241 } 242 243 int 244 bhnd_pcie2_mdio_write_ext(struct bhnd_pcie2_softc *sc, int phy, int devaddr, 245 int reg, int val) 246 { 247 // TODO 248 return (ENXIO); 249 } 250 251 static device_method_t bhnd_pcie2_methods[] = { 252 /* Device interface */ 253 DEVMETHOD(device_probe, bhnd_pcie2_generic_probe), 254 DEVMETHOD(device_attach, bhnd_pcie2_generic_attach), 255 DEVMETHOD(device_detach, bhnd_pcie2_generic_detach), 256 DEVMETHOD(device_suspend, bhnd_pcie2_generic_suspend), 257 DEVMETHOD(device_resume, bhnd_pcie2_generic_resume), 258 259 /* Bus interface */ 260 DEVMETHOD(bus_add_child, bhnd_pcie2_add_child), 261 DEVMETHOD(bus_child_deleted, bhnd_pcie2_child_deleted), 262 DEVMETHOD(bus_print_child, bus_generic_print_child), 263 DEVMETHOD(bus_get_resource_list, bhnd_pcie2_get_resource_list), 264 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 265 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 266 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 267 268 DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), 269 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 270 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 271 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 272 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), 273 274 DEVMETHOD_END 275 }; 276 277 DEFINE_CLASS_0(bhnd_pcie2, bhnd_pcie2_driver, bhnd_pcie2_methods, 278 sizeof(struct bhnd_pcie2_softc)); 279 MODULE_DEPEND(bhnd_pcie2, bhnd, 1, 1, 1); 280 MODULE_DEPEND(bhnd_pcie2, pci, 1, 1, 1); 281 MODULE_VERSION(bhnd_pcie2, 1); 282