xref: /netbsd-src/sys/arch/m68k/fpe/fpu_subr.c (revision 77f57d5580661f5662eefd224684330f0b94143e)
1 /*	$NetBSD: fpu_subr.c,v 1.12 2013/04/21 02:50:48 isaki Exp $ */
2 
3 /*
4  * Copyright (c) 1992, 1993
5  *	The Regents of the University of California.  All rights reserved.
6  *
7  * This software was developed by the Computer Systems Engineering group
8  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
9  * contributed to Berkeley.
10  *
11  * All advertising materials mentioning features or use of this software
12  * must display the following acknowledgement:
13  *	This product includes software developed by the University of
14  *	California, Lawrence Berkeley Laboratory.
15  *
16  * Redistribution and use in source and binary forms, with or without
17  * modification, are permitted provided that the following conditions
18  * are met:
19  * 1. Redistributions of source code must retain the above copyright
20  *    notice, this list of conditions and the following disclaimer.
21  * 2. Redistributions in binary form must reproduce the above copyright
22  *    notice, this list of conditions and the following disclaimer in the
23  *    documentation and/or other materials provided with the distribution.
24  * 3. Neither the name of the University nor the names of its contributors
25  *    may be used to endorse or promote products derived from this software
26  *    without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38  * SUCH DAMAGE.
39  *
40  *	@(#)fpu_subr.c	8.1 (Berkeley) 6/11/93
41  */
42 
43 /*
44  * FPU subroutines.
45  */
46 
47 #include <sys/cdefs.h>
48 __KERNEL_RCSID(0, "$NetBSD: fpu_subr.c,v 1.12 2013/04/21 02:50:48 isaki Exp $");
49 
50 #include <sys/types.h>
51 #include <sys/systm.h>
52 
53 #include <machine/reg.h>
54 
55 #include "fpu_emulate.h"
56 #include "fpu_arith.h"
57 
58 /*
59  * m68020 or later has a BFFFO instruction, therefore use it.
60  * Otherwise, use C version.
61  */
62 static inline int
bfffo(uint32_t src)63 bfffo(uint32_t src)
64 {
65 	int offset;
66 #if defined(__m68k__) && !defined(__mc68010__)
67 	__asm volatile("bfffo %1{#0:#32},%0" : "=d"(offset) : "g"(src));
68 #else
69 	int width = 32;
70 	for (offset = 0; width-- > 0 && (int)src >= 0; src <<= 1) {
71 		offset++;
72 	}
73 #endif
74 	return offset;
75 }
76 
77 /*
78  * Shift the given number right rsh bits.  Any bits that `fall off' will get
79  * shoved into the sticky field; we return the resulting sticky.  Note that
80  * shifting NaNs is legal (this will never shift all bits out); a NaN's
81  * sticky field is ignored anyway.
82  */
83 int
fpu_shr(struct fpn * fp,int rsh)84 fpu_shr(struct fpn *fp, int rsh)
85 {
86 	uint32_t m0, m1, m2, s;
87 	int lsh;
88 
89 #ifdef DIAGNOSTIC
90 	if (rsh < 0 || (fp->fp_class != FPC_NUM && !ISNAN(fp)))
91 		panic("fpu_rightshift 1");
92 #endif
93 
94 	m0 = fp->fp_mant[0];
95 	m1 = fp->fp_mant[1];
96 	m2 = fp->fp_mant[2];
97 
98 	/* If shifting all the bits out, take a shortcut. */
99 	if (rsh >= FP_NMANT) {
100 #ifdef DIAGNOSTIC
101 		if ((m0 | m1 | m2) == 0)
102 			panic("fpu_rightshift 2");
103 #endif
104 		fp->fp_mant[0] = 0;
105 		fp->fp_mant[1] = 0;
106 		fp->fp_mant[2] = 0;
107 #ifdef notdef
108 		if ((m0 | m1 | m2) == 0)
109 			fp->fp_class = FPC_ZERO;
110 		else
111 #endif
112 			fp->fp_sticky = 1;
113 		return (1);
114 	}
115 
116 	/* Squish out full words. */
117 	s = fp->fp_sticky;
118 	if (rsh >= 32 * 2) {
119 		s |= m2 | m1;
120 		m2 = m0, m1 = 0, m0 = 0;
121 	} else if (rsh >= 32) {
122 		s |= m2;
123 		m2 = m1, m1 = m0, m0 = 0;
124 	}
125 
126 	/* Handle any remaining partial word. */
127 	if ((rsh &= 31) != 0) {
128 		lsh = 32 - rsh;
129 		s |= m2 << lsh;
130 		m2 = (m2 >> rsh) | (m1 << lsh);
131 		m1 = (m1 >> rsh) | (m0 << lsh);
132 		m0 >>= rsh;
133 	}
134 	fp->fp_mant[0] = m0;
135 	fp->fp_mant[1] = m1;
136 	fp->fp_mant[2] = m2;
137 	fp->fp_sticky = s;
138 	return (s);
139 }
140 
141 /*
142  * Force a number to be normal, i.e., make its fraction have all zero
143  * bits before FP_1, then FP_1, then all 1 bits.  This is used for denorms
144  * and (sometimes) for intermediate results.
145  *
146  * Internally, this may use a `supernormal' -- a number whose fp_mant
147  * is greater than or equal to 2.0 -- so as a side effect you can hand it
148  * a supernormal and it will fix it (provided fp->fp_mant[2] == 0).
149  */
150 void
fpu_norm(struct fpn * fp)151 fpu_norm(struct fpn *fp)
152 {
153 	uint32_t m0, m1, m2, sup, nrm;
154 	int lsh, rsh, exp;
155 
156 	exp = fp->fp_exp;
157 	m0 = fp->fp_mant[0];
158 	m1 = fp->fp_mant[1];
159 	m2 = fp->fp_mant[2];
160 
161 	/* Handle severe subnormals with 32-bit moves. */
162 	if (m0 == 0) {
163 		if (m1) {
164 			m0 = m1;
165 			m1 = m2;
166 			m2 = 0;
167 			exp -= 32;
168 		} else if (m2) {
169 			m0 = m2;
170 			m1 = 0;
171 			m2 = 0;
172 			exp -= 2 * 32;
173 		} else {
174 			fp->fp_class = FPC_ZERO;
175 			return;
176 		}
177 	}
178 
179 	/* Now fix any supernormal or remaining subnormal. */
180 	nrm = FP_1;
181 	sup = nrm << 1;
182 	if (m0 >= sup) {
183 		/*
184 		 * We have a supernormal number.  We need to shift it right.
185 		 * We may assume m2==0.
186 		 */
187 		rsh = bfffo(m0);
188 		rsh = 31 - rsh - FP_LG;
189 		exp += rsh;
190 		lsh = 32 - rsh;
191 		m2 = m1 << lsh;
192 		m1 = (m1 >> rsh) | (m0 << lsh);
193 		m0 = (m0 >> rsh);
194 	} else if (m0 < nrm) {
195 		/*
196 		 * We have a regular denorm (a subnormal number), and need
197 		 * to shift it left.
198 		 */
199 		lsh = bfffo(m0);
200 		lsh = FP_LG - 31 + lsh;
201 		exp -= lsh;
202 		rsh = 32 - lsh;
203 		m0 = (m0 << lsh) | (m1 >> rsh);
204 		m1 = (m1 << lsh) | (m2 >> rsh);
205 		m2 <<= lsh;
206 	}
207 
208 	fp->fp_exp = exp;
209 	fp->fp_mant[0] = m0;
210 	fp->fp_mant[1] = m1;
211 	fp->fp_mant[2] = m2;
212 }
213 
214 /*
215  * Concoct a `fresh' Quiet NaN per Appendix N.
216  * As a side effect, we set OPERR for the current exceptions.
217  */
218 struct fpn *
fpu_newnan(struct fpemu * fe)219 fpu_newnan(struct fpemu *fe)
220 {
221 	struct fpn *fp;
222 
223 	fe->fe_fpsr |= FPSR_OPERR;
224 	fp = &fe->fe_f3;
225 	fp->fp_class = FPC_QNAN;
226 	fp->fp_sign = 0;
227 	fp->fp_mant[0] = FP_1 - 1;
228 	fp->fp_mant[1] = fp->fp_mant[2] = ~0;
229 	return (fp);
230 }
231