1 /* $NetBSD: satalink.c,v 1.58 2022/09/25 17:52:25 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2003 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of Wasabi Systems, Inc.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: satalink.c,v 1.58 2022/09/25 17:52:25 thorpej Exp $");
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37
38 #include <dev/pci/pcivar.h>
39 #include <dev/pci/pcidevs.h>
40 #include <dev/pci/pciidereg.h>
41 #include <dev/pci/pciidevar.h>
42 #include <dev/pci/pciide_sii3112_reg.h>
43
44 #include <dev/ata/satareg.h>
45 #include <dev/ata/satavar.h>
46 #include <dev/ata/atareg.h>
47
48 /*
49 * Register map for BA5 register space, indexed by channel.
50 */
51 static const struct {
52 bus_addr_t ba5_IDEDMA_CMD;
53 bus_addr_t ba5_IDEDMA_CTL;
54 bus_addr_t ba5_IDEDMA_TBL;
55 bus_addr_t ba5_IDEDMA_CMD2;
56 bus_addr_t ba5_IDEDMA_CTL2;
57 bus_addr_t ba5_IDE_TF0;
58 bus_addr_t ba5_IDE_TF1;
59 bus_addr_t ba5_IDE_TF2;
60 bus_addr_t ba5_IDE_TF3;
61 bus_addr_t ba5_IDE_TF4;
62 bus_addr_t ba5_IDE_TF5;
63 bus_addr_t ba5_IDE_TF6;
64 bus_addr_t ba5_IDE_TF7;
65 bus_addr_t ba5_IDE_TF8;
66 bus_addr_t ba5_IDE_RAD;
67 bus_addr_t ba5_IDE_TF9;
68 bus_addr_t ba5_IDE_TF10;
69 bus_addr_t ba5_IDE_TF11;
70 bus_addr_t ba5_IDE_TF12;
71 bus_addr_t ba5_IDE_TF13;
72 bus_addr_t ba5_IDE_TF14;
73 bus_addr_t ba5_IDE_TF15;
74 bus_addr_t ba5_IDE_TF16;
75 bus_addr_t ba5_IDE_TF17;
76 bus_addr_t ba5_IDE_TF18;
77 bus_addr_t ba5_IDE_TF19;
78 bus_addr_t ba5_IDE_RABC;
79 bus_addr_t ba5_IDE_CMD_STS;
80 bus_addr_t ba5_IDE_CFG_STS;
81 bus_addr_t ba5_IDE_DTM;
82 bus_addr_t ba5_SControl;
83 bus_addr_t ba5_SStatus;
84 bus_addr_t ba5_SError;
85 bus_addr_t ba5_SActive; /* 3114 */
86 bus_addr_t ba5_SMisc;
87 bus_addr_t ba5_PHY_CONFIG;
88 bus_addr_t ba5_SIEN;
89 bus_addr_t ba5_SFISCfg;
90 } satalink_ba5_regmap[] = {
91 { /* Channel 0 */
92 .ba5_IDEDMA_CMD = 0x000,
93 .ba5_IDEDMA_CTL = 0x002,
94 .ba5_IDEDMA_TBL = 0x004,
95 .ba5_IDEDMA_CMD2 = 0x010,
96 .ba5_IDEDMA_CTL2 = 0x012,
97 .ba5_IDE_TF0 = 0x080, /* wd_data */
98 .ba5_IDE_TF1 = 0x081, /* wd_error */
99 .ba5_IDE_TF2 = 0x082, /* wd_seccnt */
100 .ba5_IDE_TF3 = 0x083, /* wd_sector */
101 .ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */
102 .ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */
103 .ba5_IDE_TF6 = 0x086, /* wd_sdh */
104 .ba5_IDE_TF7 = 0x087, /* wd_command */
105 .ba5_IDE_TF8 = 0x08a, /* wd_altsts */
106 .ba5_IDE_RAD = 0x08c,
107 .ba5_IDE_TF9 = 0x091, /* Features 2 */
108 .ba5_IDE_TF10 = 0x092, /* Sector Count 2 */
109 .ba5_IDE_TF11 = 0x093, /* Start Sector 2 */
110 .ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */
111 .ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */
112 .ba5_IDE_TF14 = 0x096, /* Device/Head 2 */
113 .ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */
114 .ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */
115 .ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */
116 .ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */
117 .ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */
118 .ba5_IDE_RABC = 0x09c,
119 .ba5_IDE_CMD_STS = 0x0a0,
120 .ba5_IDE_CFG_STS = 0x0a1,
121 .ba5_IDE_DTM = 0x0b4,
122 .ba5_SControl = 0x100,
123 .ba5_SStatus = 0x104,
124 .ba5_SError = 0x108,
125 .ba5_SActive = 0x10c,
126 .ba5_SMisc = 0x140,
127 .ba5_PHY_CONFIG = 0x144,
128 .ba5_SIEN = 0x148,
129 .ba5_SFISCfg = 0x14c,
130 },
131 { /* Channel 1 */
132 .ba5_IDEDMA_CMD = 0x008,
133 .ba5_IDEDMA_CTL = 0x00a,
134 .ba5_IDEDMA_TBL = 0x00c,
135 .ba5_IDEDMA_CMD2 = 0x018,
136 .ba5_IDEDMA_CTL2 = 0x01a,
137 .ba5_IDE_TF0 = 0x0c0, /* wd_data */
138 .ba5_IDE_TF1 = 0x0c1, /* wd_error */
139 .ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */
140 .ba5_IDE_TF3 = 0x0c3, /* wd_sector */
141 .ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */
142 .ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */
143 .ba5_IDE_TF6 = 0x0c6, /* wd_sdh */
144 .ba5_IDE_TF7 = 0x0c7, /* wd_command */
145 .ba5_IDE_TF8 = 0x0ca, /* wd_altsts */
146 .ba5_IDE_RAD = 0x0cc,
147 .ba5_IDE_TF9 = 0x0d1, /* Features 2 */
148 .ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */
149 .ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */
150 .ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */
151 .ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */
152 .ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */
153 .ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */
154 .ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */
155 .ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */
156 .ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */
157 .ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */
158 .ba5_IDE_RABC = 0x0dc,
159 .ba5_IDE_CMD_STS = 0x0e0,
160 .ba5_IDE_CFG_STS = 0x0e1,
161 .ba5_IDE_DTM = 0x0f4,
162 .ba5_SControl = 0x180,
163 .ba5_SStatus = 0x184,
164 .ba5_SError = 0x188,
165 .ba5_SActive = 0x18c,
166 .ba5_SMisc = 0x1c0,
167 .ba5_PHY_CONFIG = 0x1c4,
168 .ba5_SIEN = 0x1c8,
169 .ba5_SFISCfg = 0x1cc,
170 },
171 { /* Channel 2 (3114) */
172 .ba5_IDEDMA_CMD = 0x200,
173 .ba5_IDEDMA_CTL = 0x202,
174 .ba5_IDEDMA_TBL = 0x204,
175 .ba5_IDEDMA_CMD2 = 0x210,
176 .ba5_IDEDMA_CTL2 = 0x212,
177 .ba5_IDE_TF0 = 0x280, /* wd_data */
178 .ba5_IDE_TF1 = 0x281, /* wd_error */
179 .ba5_IDE_TF2 = 0x282, /* wd_seccnt */
180 .ba5_IDE_TF3 = 0x283, /* wd_sector */
181 .ba5_IDE_TF4 = 0x284, /* wd_cyl_lo */
182 .ba5_IDE_TF5 = 0x285, /* wd_cyl_hi */
183 .ba5_IDE_TF6 = 0x286, /* wd_sdh */
184 .ba5_IDE_TF7 = 0x287, /* wd_command */
185 .ba5_IDE_TF8 = 0x28a, /* wd_altsts */
186 .ba5_IDE_RAD = 0x28c,
187 .ba5_IDE_TF9 = 0x291, /* Features 2 */
188 .ba5_IDE_TF10 = 0x292, /* Sector Count 2 */
189 .ba5_IDE_TF11 = 0x293, /* Start Sector 2 */
190 .ba5_IDE_TF12 = 0x294, /* Cylinder Low 2 */
191 .ba5_IDE_TF13 = 0x295, /* Cylinder High 2 */
192 .ba5_IDE_TF14 = 0x296, /* Device/Head 2 */
193 .ba5_IDE_TF15 = 0x297, /* Cmd Sts 2 */
194 .ba5_IDE_TF16 = 0x298, /* Sector Count 2 ext */
195 .ba5_IDE_TF17 = 0x299, /* Start Sector 2 ext */
196 .ba5_IDE_TF18 = 0x29a, /* Cyl Low 2 ext */
197 .ba5_IDE_TF19 = 0x29b, /* Cyl High 2 ext */
198 .ba5_IDE_RABC = 0x29c,
199 .ba5_IDE_CMD_STS = 0x2a0,
200 .ba5_IDE_CFG_STS = 0x2a1,
201 .ba5_IDE_DTM = 0x2b4,
202 .ba5_SControl = 0x300,
203 .ba5_SStatus = 0x304,
204 .ba5_SError = 0x308,
205 .ba5_SActive = 0x30c,
206 .ba5_SMisc = 0x340,
207 .ba5_PHY_CONFIG = 0x344,
208 .ba5_SIEN = 0x348,
209 .ba5_SFISCfg = 0x34c,
210 },
211 { /* Channel 3 (3114) */
212 .ba5_IDEDMA_CMD = 0x208,
213 .ba5_IDEDMA_CTL = 0x20a,
214 .ba5_IDEDMA_TBL = 0x20c,
215 .ba5_IDEDMA_CMD2 = 0x218,
216 .ba5_IDEDMA_CTL2 = 0x21a,
217 .ba5_IDE_TF0 = 0x2c0, /* wd_data */
218 .ba5_IDE_TF1 = 0x2c1, /* wd_error */
219 .ba5_IDE_TF2 = 0x2c2, /* wd_seccnt */
220 .ba5_IDE_TF3 = 0x2c3, /* wd_sector */
221 .ba5_IDE_TF4 = 0x2c4, /* wd_cyl_lo */
222 .ba5_IDE_TF5 = 0x2c5, /* wd_cyl_hi */
223 .ba5_IDE_TF6 = 0x2c6, /* wd_sdh */
224 .ba5_IDE_TF7 = 0x2c7, /* wd_command */
225 .ba5_IDE_TF8 = 0x2ca, /* wd_altsts */
226 .ba5_IDE_RAD = 0x2cc,
227 .ba5_IDE_TF9 = 0x2d1, /* Features 2 */
228 .ba5_IDE_TF10 = 0x2d2, /* Sector Count 2 */
229 .ba5_IDE_TF11 = 0x2d3, /* Start Sector 2 */
230 .ba5_IDE_TF12 = 0x2d4, /* Cylinder Low 2 */
231 .ba5_IDE_TF13 = 0x2d5, /* Cylinder High 2 */
232 .ba5_IDE_TF14 = 0x2d6, /* Device/Head 2 */
233 .ba5_IDE_TF15 = 0x2d7, /* Cmd Sts 2 */
234 .ba5_IDE_TF16 = 0x2d8, /* Sector Count 2 ext */
235 .ba5_IDE_TF17 = 0x2d9, /* Start Sector 2 ext */
236 .ba5_IDE_TF18 = 0x2da, /* Cyl Low 2 ext */
237 .ba5_IDE_TF19 = 0x2db, /* Cyl High 2 ext */
238 .ba5_IDE_RABC = 0x2dc,
239 .ba5_IDE_CMD_STS = 0x2e0,
240 .ba5_IDE_CFG_STS = 0x2e1,
241 .ba5_IDE_DTM = 0x2f4,
242 .ba5_SControl = 0x380,
243 .ba5_SStatus = 0x384,
244 .ba5_SError = 0x388,
245 .ba5_SActive = 0x38c,
246 .ba5_SMisc = 0x3c0,
247 .ba5_PHY_CONFIG = 0x3c4,
248 .ba5_SIEN = 0x3c8,
249 .ba5_SFISCfg = 0x3cc,
250 },
251 };
252
253 #define ba5_SIS 0x214 /* summary interrupt status */
254
255 /* Interrupt steering bit in BA5[0x200]. */
256 #define IDEDMA_CMD_INT_STEER (1U << 1)
257
258 static int satalink_match(device_t, cfdata_t, void *);
259 static void satalink_attach(device_t, device_t, void *);
260
261 CFATTACH_DECL_NEW(satalink, sizeof(struct pciide_softc),
262 satalink_match, satalink_attach, pciide_detach, NULL);
263
264 static void sii3112_chip_map(struct pciide_softc*,
265 const struct pci_attach_args*);
266 static void sii3114_chip_map(struct pciide_softc*,
267 const struct pci_attach_args*);
268 static void sii3112_drv_probe(struct ata_channel*);
269 static void sii3112_setup_channel(struct ata_channel*);
270
271 static const struct pciide_product_desc pciide_satalink_products[] = {
272 { PCI_PRODUCT_CMDTECH_3112,
273 0,
274 "Silicon Image SATALink 3112",
275 sii3112_chip_map,
276 },
277 { PCI_PRODUCT_CMDTECH_3512,
278 0,
279 "Silicon Image SATALink 3512",
280 sii3112_chip_map,
281 },
282 { PCI_PRODUCT_CMDTECH_AAR_1210SA,
283 0,
284 "Adaptec AAR-1210SA serial ATA RAID controller",
285 sii3112_chip_map,
286 },
287 { PCI_PRODUCT_CMDTECH_3114,
288 0,
289 "Silicon Image SATALink 3114",
290 sii3114_chip_map,
291 },
292 { PCI_PRODUCT_ATI_IXP_SATA_300,
293 0,
294 "ATI IXP 300 SATA",
295 sii3112_chip_map,
296 },
297 { 0,
298 0,
299 NULL,
300 NULL
301 }
302 };
303
304 static int
satalink_match(device_t parent,cfdata_t match,void * aux)305 satalink_match(device_t parent, cfdata_t match, void *aux)
306 {
307 struct pci_attach_args *pa = aux;
308
309 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) {
310 if (pciide_lookup_product(pa->pa_id, pciide_satalink_products))
311 return (2);
312 }
313 return (0);
314 }
315
316 static void
satalink_attach(device_t parent,device_t self,void * aux)317 satalink_attach(device_t parent, device_t self, void *aux)
318 {
319 struct pci_attach_args *pa = aux;
320 struct pciide_softc *sc = device_private(self);
321
322 sc->sc_wdcdev.sc_atac.atac_dev = self;
323
324 pciide_common_attach(sc, pa,
325 pciide_lookup_product(pa->pa_id, pciide_satalink_products));
326
327 }
328
329 static inline uint32_t
ba5_read_4_ind(struct pciide_softc * sc,bus_addr_t reg)330 ba5_read_4_ind(struct pciide_softc *sc, bus_addr_t reg)
331 {
332 uint32_t rv;
333 int s;
334
335 s = splbio();
336 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg);
337 rv = pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA);
338 splx(s);
339
340 return (rv);
341 }
342
343 static inline uint32_t
ba5_read_4(struct pciide_softc * sc,bus_addr_t reg)344 ba5_read_4(struct pciide_softc *sc, bus_addr_t reg)
345 {
346
347 if (__predict_true(sc->sc_ba5_en != 0))
348 return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg));
349
350 return (ba5_read_4_ind(sc, reg));
351 }
352
353 #define BA5_READ_4(sc, chan, reg) \
354 ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg)
355
356 static inline void
ba5_write_4_ind(struct pciide_softc * sc,bus_addr_t reg,uint32_t val)357 ba5_write_4_ind(struct pciide_softc *sc, bus_addr_t reg, uint32_t val)
358 {
359 int s;
360
361 s = splbio();
362 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg);
363 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val);
364 splx(s);
365 }
366
367 static inline void
ba5_write_4(struct pciide_softc * sc,bus_addr_t reg,uint32_t val)368 ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val)
369 {
370
371 if (__predict_true(sc->sc_ba5_en != 0))
372 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val);
373 else
374 ba5_write_4_ind(sc, reg, val);
375 }
376
377 #define BA5_WRITE_4(sc, chan, reg, val) \
378 ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val))
379
380 /*
381 * When the Silicon Image 3112 retries a PCI memory read command,
382 * it may retry it as a memory read multiple command under some
383 * circumstances. This can totally confuse some PCI controllers,
384 * so ensure that it will never do this by making sure that the
385 * Read Threshold (FIFO Read Request Control) field of the FIFO
386 * Valid Byte Count and Control registers for both channels (BA5
387 * offset 0x40 and 0x44) are set to be at least as large as the
388 * cacheline size register.
389 * This may also happen on the 3114 (ragge 050527)
390 */
391 static void
sii_fixup_cacheline(struct pciide_softc * sc,const struct pci_attach_args * pa,int n)392 sii_fixup_cacheline(struct pciide_softc *sc, const struct pci_attach_args *pa,
393 int n)
394 {
395 pcireg_t cls, reg;
396 int i;
397 static bus_addr_t addr[] = { 0x40, 0x44, 0x240, 0x244 };
398
399 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
400 cls = (cls >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK;
401 cls *= 4;
402 if (cls > 224) {
403 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
404 cls &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT);
405 cls |= ((224/4) << PCI_CACHELINE_SHIFT);
406 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, cls);
407 cls = 224;
408 }
409 if (cls < 32)
410 cls = 32;
411 cls = (cls + 31) / 32;
412 for (i = 0; i < n; i++) {
413 reg = ba5_read_4(sc, addr[i]);
414 if ((reg & 0x7) < cls)
415 ba5_write_4(sc, addr[i], (reg & 0x07) | cls);
416 }
417 }
418
419 static void
sii3112_chip_map(struct pciide_softc * sc,const struct pci_attach_args * pa)420 sii3112_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
421 {
422 struct pciide_channel *cp;
423 pcireg_t interface, scs_cmd, cfgctl;
424 int channel;
425
426 if (pciide_chipen(sc, pa) == 0)
427 return;
428
429 #define SII3112_RESET_BITS \
430 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \
431 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \
432 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET)
433
434 /*
435 * Reset everything and then unblock all of the interrupts.
436 */
437 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD);
438 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD,
439 scs_cmd | SII3112_RESET_BITS);
440 delay(50 * 1000);
441 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD,
442 scs_cmd & SCS_CMD_BA5_EN);
443 delay(50 * 1000);
444
445 if (scs_cmd & SCS_CMD_BA5_EN) {
446 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
447 "SATALink BA5 register space enabled\n");
448 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
449 PCI_MAPREG_TYPE_MEM|
450 PCI_MAPREG_MEM_TYPE_32BIT, 0,
451 &sc->sc_ba5_st, &sc->sc_ba5_sh,
452 NULL, &sc->sc_ba5_ss) != 0)
453 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
454 "unable to map SATALink BA5 register space\n");
455 else
456 sc->sc_ba5_en = 1;
457 } else {
458 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
459 "SATALink BA5 register space disabled\n");
460
461 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag,
462 SII3112_PCI_CFGCTL);
463 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL,
464 cfgctl | CFGCTL_BA5INDEN);
465 }
466
467 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
468 "bus-master DMA support present");
469 pciide_mapreg_dma(sc, pa);
470 aprint_verbose("\n");
471
472 /*
473 * Rev. <= 0x01 of the 3112 have a bug that can cause data
474 * corruption if DMA transfers cross an 8K boundary. This is
475 * apparently hard to tickle, but we'll go ahead and play it
476 * safe.
477 */
478 if ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMDTECH_3112 ||
479 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMDTECH_AAR_1210SA) &&
480 PCI_REVISION(pa->pa_class) <= 0x01) {
481 sc->sc_dma_maxsegsz = 8192;
482 sc->sc_dma_boundary = 8192;
483 }
484
485 sii_fixup_cacheline(sc, pa, 2);
486
487 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
488 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
489 if (sc->sc_dma_ok) {
490 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
491 sc->sc_wdcdev.irqack = pciide_irqack;
492 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
493 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
494 }
495 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel;
496
497 /* We can use SControl and SStatus to probe for drives. */
498 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe;
499
500 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
501 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
502 sc->sc_wdcdev.wdc_maxdrives = 1;
503
504 wdc_allocate_regs(&sc->sc_wdcdev);
505
506 /*
507 * The 3112 either identifies itself as a RAID storage device
508 * or a Misc storage device. Fake up the interface bits for
509 * what our driver expects.
510 */
511 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
512 interface = PCI_INTERFACE(pa->pa_class);
513 } else {
514 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
515 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
516 }
517
518 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
519 channel++) {
520 cp = &sc->pciide_channels[channel];
521 if (pciide_chansetup(sc, channel, interface) == 0)
522 continue;
523 pciide_mapchan(pa, cp, interface, pciide_pci_intr);
524 }
525 }
526
527 static void
sii3114_mapreg_dma(struct pciide_softc * sc,const struct pci_attach_args * pa)528 sii3114_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa)
529 {
530 struct pciide_channel *pc;
531 int chan, reg;
532 bus_size_t size;
533
534 sc->sc_wdcdev.dma_arg = sc;
535 sc->sc_wdcdev.dma_init = pciide_dma_init;
536 sc->sc_wdcdev.dma_start = pciide_dma_start;
537 sc->sc_wdcdev.dma_finish = pciide_dma_finish;
538
539 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
540 PCIIDE_OPTIONS_NODMA) {
541 aprint_verbose(
542 ", but unused (forced off by config file)");
543 sc->sc_dma_ok = 0;
544 return;
545 }
546
547 /*
548 * Slice off a subregion of BA5 for each of the channel's DMA
549 * registers.
550 */
551
552 sc->sc_dma_iot = sc->sc_ba5_st;
553 for (chan = 0; chan < 4; chan++) {
554 pc = &sc->pciide_channels[chan];
555 for (reg = 0; reg < IDEDMA_NREGS; reg++) {
556 size = 4;
557 if (size > (IDEDMA_SCH_OFFSET - reg))
558 size = IDEDMA_SCH_OFFSET - reg;
559 if (bus_space_subregion(sc->sc_ba5_st,
560 sc->sc_ba5_sh,
561 satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg,
562 size, &pc->dma_iohs[reg]) != 0) {
563 sc->sc_dma_ok = 0;
564 aprint_verbose(", but can't subregion offset "
565 "%lu size %lu",
566 (u_long) satalink_ba5_regmap[
567 chan].ba5_IDEDMA_CMD + reg,
568 (u_long) size);
569 return;
570 }
571 }
572 }
573
574 /* DMA registers all set up! */
575 sc->sc_dmat = pa->pa_dmat;
576 sc->sc_dma_ok = 1;
577 }
578
579 static int
sii3114_chansetup(struct pciide_softc * sc,int channel)580 sii3114_chansetup(struct pciide_softc *sc, int channel)
581 {
582 static const char *channel_names[] = {
583 "port 0",
584 "port 1",
585 "port 2",
586 "port 3",
587 };
588 struct pciide_channel *cp = &sc->pciide_channels[channel];
589
590 sc->wdc_chanarray[channel] = &cp->ata_channel;
591
592 /*
593 * We must always keep the Interrupt Steering bit set in channel 2's
594 * IDEDMA_CMD register.
595 */
596 if (channel == 2)
597 cp->idedma_cmd = IDEDMA_CMD_INT_STEER;
598
599 cp->name = channel_names[channel];
600 cp->ata_channel.ch_channel = channel;
601 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
602
603 return (1);
604 }
605
606 static void
sii3114_mapchan(struct pciide_channel * cp)607 sii3114_mapchan(struct pciide_channel *cp)
608 {
609 struct ata_channel *wdc_cp = &cp->ata_channel;
610 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp);
611 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp);
612 int i;
613
614 cp->compat = 0;
615 cp->ih = sc->sc_pci_ih;
616
617 wdr->cmd_iot = sc->sc_ba5_st;
618 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
619 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF0,
620 9, &wdr->cmd_baseioh) != 0) {
621 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
622 "couldn't subregion %s cmd base\n", cp->name);
623 goto bad;
624 }
625
626 wdr->ctl_iot = sc->sc_ba5_st;
627 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
628 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF8,
629 1, &cp->ctl_baseioh) != 0) {
630 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
631 "couldn't subregion %s ctl base\n", cp->name);
632 goto bad;
633 }
634 wdr->ctl_ioh = cp->ctl_baseioh;
635
636 for (i = 0; i < WDC_NREG; i++) {
637 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
638 i, i == 0 ? 4 : 1,
639 &wdr->cmd_iohs[i]) != 0) {
640 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
641 "couldn't subregion %s channel cmd regs\n",
642 cp->name);
643 goto bad;
644 }
645 }
646 wdc_init_shadow_regs(wdr);
647 wdr->data32iot = wdr->cmd_iot;
648 wdr->data32ioh = wdr->cmd_iohs[0];
649 wdcattach(wdc_cp);
650 return;
651
652 bad:
653 cp->ata_channel.ch_flags |= ATACH_DISABLED;
654 }
655
656 static void
sii3114_chip_map(struct pciide_softc * sc,const struct pci_attach_args * pa)657 sii3114_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
658 {
659 struct pciide_channel *cp;
660 pcireg_t scs_cmd;
661 pci_intr_handle_t intrhandle;
662 const char *intrstr;
663 int channel;
664 char intrbuf[PCI_INTRSTR_LEN];
665
666 if (pciide_chipen(sc, pa) == 0)
667 return;
668
669 #define SII3114_RESET_BITS \
670 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \
671 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \
672 SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET | \
673 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET | \
674 SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET)
675
676 /*
677 * Reset everything and then unblock all of the interrupts.
678 */
679 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD);
680 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD,
681 scs_cmd | SII3114_RESET_BITS);
682 delay(50 * 1000);
683 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD,
684 scs_cmd & SCS_CMD_M66EN);
685 delay(50 * 1000);
686
687 /*
688 * On the 3114, the BA5 register space is always enabled. In
689 * order to use the 3114 in any sane way, we must use this BA5
690 * register space, and so we consider it an error if we cannot
691 * map it.
692 *
693 * As a consequence of using BA5, our register mapping is different
694 * from a normal PCI IDE controller's, and so we are unable to use
695 * most of the common PCI IDE register mapping functions.
696 */
697 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
698 PCI_MAPREG_TYPE_MEM|
699 PCI_MAPREG_MEM_TYPE_32BIT, 0,
700 &sc->sc_ba5_st, &sc->sc_ba5_sh,
701 NULL, &sc->sc_ba5_ss) != 0) {
702 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
703 "unable to map SATALink BA5 register space\n");
704 return;
705 }
706 sc->sc_ba5_en = 1;
707
708 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
709 "%dMHz PCI bus\n", (scs_cmd & SCS_CMD_M66EN) ? 66 : 33);
710
711 /*
712 * Set the Interrupt Steering bit in the IDEDMA_CMD register of
713 * channel 2. This is required at all times for proper operation
714 * when using the BA5 register space (otherwise interrupts from
715 * all 4 channels won't work).
716 */
717 BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER);
718
719 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
720 "bus-master DMA support present");
721 sii3114_mapreg_dma(sc, pa);
722 aprint_verbose("\n");
723
724 sii_fixup_cacheline(sc, pa, 4);
725
726 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
727 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
728 if (sc->sc_dma_ok) {
729 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
730 sc->sc_wdcdev.irqack = pciide_irqack;
731 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
732 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
733 }
734 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel;
735
736 /* We can use SControl and SStatus to probe for drives. */
737 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe;
738
739 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
740 sc->sc_wdcdev.sc_atac.atac_nchannels = 4;
741 sc->sc_wdcdev.wdc_maxdrives = 1;
742
743 wdc_allocate_regs(&sc->sc_wdcdev);
744
745 /* Map and establish the interrupt handler. */
746 if (pci_intr_map(pa, &intrhandle) != 0) {
747 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
748 "couldn't map native-PCI interrupt\n");
749 return;
750 }
751 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf));
752 sc->sc_pci_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_BIO,
753 /* XXX */
754 pciide_pci_intr, sc, device_xname(sc->sc_wdcdev.sc_atac.atac_dev));
755 if (sc->sc_pci_ih != NULL) {
756 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
757 "using %s for native-PCI interrupt\n",
758 intrstr ? intrstr : "unknown interrupt");
759 } else {
760 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
761 "couldn't establish native-PCI interrupt");
762 if (intrstr != NULL)
763 aprint_error(" at %s", intrstr);
764 aprint_error("\n");
765 return;
766 }
767
768 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
769 channel++) {
770 cp = &sc->pciide_channels[channel];
771 if (sii3114_chansetup(sc, channel) == 0)
772 continue;
773 sii3114_mapchan(cp);
774 }
775 }
776
777 /* Probe the drives using SATA registers.
778 * Note we can't use wdc_sataprobe as we may not be able to map ba5
779 */
780 static void
sii3112_drv_probe(struct ata_channel * chp)781 sii3112_drv_probe(struct ata_channel *chp)
782 {
783 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
784 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp);
785 uint32_t scontrol, sstatus;
786 uint8_t /* scnt, sn, */ cl, ch;
787 int s;
788
789 ata_channel_lock(chp);
790 /*
791 * The 3112 is a 2-port part, and only has one drive per channel
792 * (each port emulates a master drive).
793 *
794 * The 3114 is similar, but has 4 channels.
795 */
796
797 /*
798 * Request communication initialization sequence, any speed.
799 * Performing this is the equivalent of an ATA Reset.
800 */
801 scontrol = SControl_DET_INIT | SControl_SPD_ANY;
802
803 /*
804 * XXX We don't yet support SATA power management; disable all
805 * power management state transitions.
806 */
807 scontrol |= SControl_IPM_NONE;
808
809 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol);
810 delay(50 * 1000);
811 scontrol &= ~SControl_DET_INIT;
812 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol);
813 delay(50 * 1000);
814
815 sstatus = BA5_READ_4(sc, chp->ch_channel, ba5_SStatus);
816 #if 0
817 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
818 "port %d: SStatus=0x%08x, SControl=0x%08x\n",
819 chp->ch_channel, sstatus,
820 BA5_READ_4(sc, chp->ch_channel, ba5_SControl));
821 #endif
822 switch (sstatus & SStatus_DET_mask) {
823 case SStatus_DET_NODEV:
824 /* No device; be silent. */
825 break;
826
827 case SStatus_DET_DEV_NE:
828 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
829 "port %d: device connected, but "
830 "communication not established\n", chp->ch_channel);
831 break;
832
833 case SStatus_DET_OFFLINE:
834 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
835 "port %d: PHY offline\n", chp->ch_channel);
836 break;
837
838 case SStatus_DET_DEV:
839 /*
840 * XXX ATAPI detection doesn't currently work. Don't
841 * XXX know why. But, it's not like the standard method
842 * XXX can detect an ATAPI device connected via a SATA/PATA
843 * XXX bridge, so at least this is no worse. --thorpej
844 */
845 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0,
846 WDSD_IBM | (0 << 4));
847 delay(10); /* 400ns delay */
848 /* Save register contents. */
849 #if 0
850 scnt = bus_space_read_1(wdr->cmd_iot,
851 wdr->cmd_iohs[wd_seccnt], 0);
852 sn = bus_space_read_1(wdr->cmd_iot,
853 wdr->cmd_iohs[wd_sector], 0);
854 #endif
855 cl = bus_space_read_1(wdr->cmd_iot,
856 wdr->cmd_iohs[wd_cyl_lo], 0);
857 ch = bus_space_read_1(wdr->cmd_iot,
858 wdr->cmd_iohs[wd_cyl_hi], 0);
859 #if 0
860 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n",
861 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), chp->ch_channel,
862 scnt, sn, cl, ch);
863 #endif
864 if (atabus_alloc_drives(chp, 1) != 0) {
865 ata_channel_unlock(chp);
866 return;
867 }
868 /*
869 * scnt and sn are supposed to be 0x1 for ATAPI, but in some
870 * cases we get wrong values here, so ignore it.
871 */
872 s = splbio();
873 if (cl == 0x14 && ch == 0xeb)
874 chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI;
875 else
876 chp->ch_drive[0].drive_type = ATA_DRIVET_ATA;
877 splx(s);
878
879 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
880 "port %d: device present, speed: %s\n",
881 chp->ch_channel,
882 sata_speed(sstatus));
883 break;
884
885 default:
886 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
887 "port %d: unknown SStatus: 0x%08x\n",
888 chp->ch_channel, sstatus);
889 }
890 ata_channel_unlock(chp);
891 }
892
893 static void
sii3112_setup_channel(struct ata_channel * chp)894 sii3112_setup_channel(struct ata_channel *chp)
895 {
896 struct ata_drive_datas *drvp;
897 int drive, s;
898 u_int32_t idedma_ctl, dtm;
899 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
900 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
901
902 /* setup DMA if needed */
903 pciide_channel_dma_setup(cp);
904
905 idedma_ctl = 0;
906 dtm = 0;
907
908 for (drive = 0; drive < 2; drive++) {
909 drvp = &chp->ch_drive[drive];
910 /* If no drive, skip */
911 if (drvp->drive_type == ATA_DRIVET_NONE)
912 continue;
913 if (drvp->drive_flags & ATA_DRIVE_UDMA) {
914 /* use Ultra/DMA */
915 s = splbio();
916 drvp->drive_flags &= ~ATA_DRIVE_DMA;
917 splx(s);
918 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
919 dtm |= DTM_IDEx_DMA;
920 } else if (drvp->drive_flags & ATA_DRIVE_DMA) {
921 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
922 dtm |= DTM_IDEx_DMA;
923 } else {
924 dtm |= DTM_IDEx_PIO;
925 }
926 }
927
928 /*
929 * Nothing to do to setup modes; it is meaningless in S-ATA
930 * (but many S-ATA drives still want to get the SET_FEATURE
931 * command).
932 */
933 if (idedma_ctl != 0) {
934 /* Add software bits in status register */
935 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
936 idedma_ctl);
937 }
938 BA5_WRITE_4(sc, chp->ch_channel, ba5_IDE_DTM, dtm);
939 }
940