xref: /netbsd-src/sys/dev/ic/arn9280.c (revision 13d4bb4cc874de96add7fc4227d38a1d656b03d1)
1 /*	$NetBSD: arn9280.c,v 1.3 2022/09/25 18:43:32 thorpej Exp $	*/
2 /*	$OpenBSD: ar9280.c,v 1.18 2012/06/10 21:23:36 kettenis Exp $	*/
3 
4 /*-
5  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
6  * Copyright (c) 2008-2009 Atheros Communications Inc.
7  *
8  * Permission to use, copy, modify, and/or distribute this software for any
9  * purpose with or without fee is hereby granted, provided that the above
10  * copyright notice and this permission notice appear in all copies.
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19  */
20 
21 /*
22  * Driver for Atheros 802.11a/g/n chipsets.
23  * Routines for AR9220, AR9223, AR9280 and AR9281 chipsets.
24  */
25 
26 #include <sys/cdefs.h>
27 __KERNEL_RCSID(0, "$NetBSD: arn9280.c,v 1.3 2022/09/25 18:43:32 thorpej Exp $");
28 
29 #include <sys/param.h>
30 #include <sys/sockio.h>
31 #include <sys/mbuf.h>
32 #include <sys/kernel.h>
33 #include <sys/socket.h>
34 #include <sys/systm.h>
35 #include <sys/queue.h>
36 #include <sys/callout.h>
37 #include <sys/conf.h>
38 #include <sys/device.h>
39 
40 #include <sys/bus.h>
41 #include <sys/endian.h>
42 #include <sys/intr.h>
43 
44 #include <net/bpf.h>
45 #include <net/if.h>
46 #include <net/if_arp.h>
47 #include <net/if_dl.h>
48 #include <net/if_ether.h>
49 #include <net/if_media.h>
50 #include <net/if_types.h>
51 
52 #include <netinet/in.h>
53 #include <netinet/in_systm.h>
54 #include <netinet/in_var.h>
55 #include <netinet/ip.h>
56 
57 #include <net80211/ieee80211_var.h>
58 #include <net80211/ieee80211_amrr.h>
59 #include <net80211/ieee80211_radiotap.h>
60 
61 #include <dev/ic/athnreg.h>
62 #include <dev/ic/athnvar.h>
63 
64 #include <dev/ic/arn5008reg.h>
65 #include <dev/ic/arn5008.h>
66 #include <dev/ic/arn5416reg.h>	/* We share the ROM layout. */
67 #include <dev/ic/arn5416.h>	/* We share the ROM layout. */
68 #include <dev/ic/arn9280reg.h>
69 #include <dev/ic/arn9280.h>
70 
71 #define Static static
72 
73 Static void	ar9280_init_from_rom(struct athn_softc *,
74 		    struct ieee80211_channel *, struct ieee80211_channel *);
75 Static void	ar9280_olpc_init(struct athn_softc *);
76 Static void	ar9280_olpc_temp_compensation(struct athn_softc *);
77 Static void	ar9280_setup(struct athn_softc *);
78 
79 PUBLIC int
ar9280_attach(struct athn_softc * sc)80 ar9280_attach(struct athn_softc *sc)
81 {
82 
83 	sc->sc_eep_base = AR5416_EEP_START_LOC;
84 	sc->sc_eep_size = sizeof(struct ar5416_eeprom);
85 	sc->sc_def_nf = AR9280_PHY_CCA_MAX_GOOD_VALUE;
86 	sc->sc_ngpiopins = (sc->sc_flags & ATHN_FLAG_USB) ? 16 : 10;
87 	sc->sc_led_pin = 1;
88 	sc->sc_workaround = AR9280_WA_DEFAULT;
89 	sc->sc_ops.setup = ar9280_setup;
90 	sc->sc_ops.swap_rom = ar5416_swap_rom;
91 	sc->sc_ops.init_from_rom = ar9280_init_from_rom;
92 	sc->sc_ops.set_txpower = ar5416_set_txpower;
93 	sc->sc_ops.set_synth = ar9280_set_synth;
94 	sc->sc_ops.spur_mitigate = ar9280_spur_mitigate;
95 	sc->sc_ops.get_spur_chans = ar5416_get_spur_chans;
96 	sc->sc_ops.olpc_init = ar9280_olpc_init;
97 	sc->sc_ops.olpc_temp_compensation = ar9280_olpc_temp_compensation;
98 	sc->sc_ini = &ar9280_2_0_ini;
99 	sc->sc_serdes = &ar9280_2_0_serdes;
100 
101 	return ar5008_attach(sc);
102 }
103 
104 Static void
ar9280_setup(struct athn_softc * sc)105 ar9280_setup(struct athn_softc *sc)
106 {
107 	const struct ar5416_eeprom *eep = sc->sc_eep;
108 	uint8_t type;
109 
110 	/* Determine if open loop power control should be used. */
111 	if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_19 &&
112 	    eep->baseEepHeader.openLoopPwrCntl)
113 		sc->sc_flags |= ATHN_FLAG_OLPC;
114 
115 	/* Determine if fast PLL clock is supported. */
116 	if (AR_SREV_9280_20(sc) &&
117 	    (sc->sc_eep_rev <= AR_EEP_MINOR_VER_16 ||
118 	     eep->baseEepHeader.fastClk5g))
119 		sc->sc_flags |= ATHN_FLAG_FAST_PLL_CLOCK;
120 
121 	/*
122 	 * Determine if initialization value for AR_AN_TOP2 must be fixed.
123 	 * This is required for some AR9220 devices such as Ubiquiti SR71-12.
124 	 */
125 	if (AR_SREV_9280_20(sc) &&
126 	    sc->sc_eep_rev > AR_EEP_MINOR_VER_10 &&
127 	    !eep->baseEepHeader.pwdclkind) {
128 		DPRINTFN(DBG_INIT, sc, "AR_AN_TOP2 fixup required\n");
129 		sc->sc_flags |= ATHN_FLAG_AN_TOP2_FIXUP;
130 	}
131 
132 	if (AR_SREV_9280_20(sc)) {
133 		/* Check if we have a valid rxGainType field in ROM. */
134 		if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_17) {
135 			/* Select initialization values based on ROM. */
136 			type = eep->baseEepHeader.rxGainType;
137 			DPRINTFN(DBG_INIT, sc, "Rx gain type=0x%x\n", type);
138 			if (type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
139 				sc->sc_rx_gain = &ar9280_2_0_rx_gain_23db_backoff;
140 			else if (type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
141 				sc->sc_rx_gain = &ar9280_2_0_rx_gain_13db_backoff;
142 			else
143 				sc->sc_rx_gain = &ar9280_2_0_rx_gain;
144 		}
145 		else
146 			sc->sc_rx_gain = &ar9280_2_0_rx_gain;
147 
148 		/* Check if we have a valid txGainType field in ROM. */
149 		if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_19) {
150 			/* Select initialization values based on ROM. */
151 			type = eep->baseEepHeader.txGainType;
152 			DPRINTFN(DBG_INIT, sc, "Tx gain type=0x%x\n", type);
153 			if (type == AR_EEP_TXGAIN_HIGH_POWER)
154 				sc->sc_tx_gain = &ar9280_2_0_tx_gain_high_power;
155 			else
156 				sc->sc_tx_gain = &ar9280_2_0_tx_gain;
157 		}
158 		else
159 			sc->sc_tx_gain = &ar9280_2_0_tx_gain;
160 	}
161 }
162 
163 PUBLIC int
ar9280_set_synth(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)164 ar9280_set_synth(struct athn_softc *sc, struct ieee80211_channel *c,
165     struct ieee80211_channel *extc)
166 {
167 	uint32_t phy, reg, ndiv = 0;
168 	uint32_t freq = c->ic_freq;
169 
170 	phy = AR_READ(sc, AR9280_PHY_SYNTH_CONTROL) & ~0x3fffffff;
171 
172 	if (IEEE80211_IS_CHAN_2GHZ(c)) {
173 		phy |= (freq << 16) / 15;
174 		phy |= AR9280_BMODE | AR9280_FRACMODE;
175 
176 		if (AR_SREV_9287_11_OR_LATER(sc)) {
177 			/* NB: Magic values from the Linux driver. */
178 			if (freq == 2484) {	/* Channel 14. */
179 				/* Japanese regulatory requirements. */
180 				AR_WRITE(sc, AR_PHY(637), 0x00000000);
181 				AR_WRITE(sc, AR_PHY(638), 0xefff0301);
182 				AR_WRITE(sc, AR_PHY(639), 0xca9228ee);
183 			}
184 			else {
185 				AR_WRITE(sc, AR_PHY(637), 0x00fffeff);
186 				AR_WRITE(sc, AR_PHY(638), 0x00f5f9ff);
187 				AR_WRITE(sc, AR_PHY(639), 0xb79f6427);
188 			}
189 		}
190 		else {
191 			reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
192 			if (freq == 2484)	/* Channel 14. */
193 				reg |= AR_PHY_CCK_TX_CTRL_JAPAN;
194 			else
195 				reg &= ~AR_PHY_CCK_TX_CTRL_JAPAN;
196 			AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
197 		}
198 	}
199 	else {
200 		if (AR_SREV_9285_10_OR_LATER(sc) ||
201 		    sc->sc_eep_rev < AR_EEP_MINOR_VER_22 ||
202 		    !((struct ar5416_base_eep_header *)sc->sc_eep)->frac_n_5g) {
203 			if ((freq % 20) == 0) {
204 				ndiv = (freq * 3) / 60;
205 				phy |= SM(AR9280_AMODE_REFSEL, 3);
206 			}
207 			else if ((freq % 10) == 0) {
208 				ndiv = (freq * 6) / 60;
209 				phy |= SM(AR9280_AMODE_REFSEL, 2);
210 			}
211 		}
212 		if (ndiv != 0) {
213 			phy |= (ndiv & 0x1ff) << 17;
214 			phy |= (ndiv & ~0x1ff) * 2;
215 		}
216 		else {
217 			phy |= (freq << 15) / 15;
218 			phy |= AR9280_FRACMODE;
219 
220 			reg = AR_READ(sc, AR_AN_SYNTH9);
221 			reg = RW(reg, AR_AN_SYNTH9_REFDIVA, 1);
222 			AR_WRITE(sc, AR_AN_SYNTH9, reg);
223 		}
224 	}
225 	AR_WRITE_BARRIER(sc);
226 	DPRINTFN(DBG_RF, sc, "AR9280_PHY_SYNTH_CONTROL=0x%08x\n", phy);
227 	AR_WRITE(sc, AR9280_PHY_SYNTH_CONTROL, phy);
228 	AR_WRITE_BARRIER(sc);
229 	return 0;
230 }
231 
232 Static void
ar9280_init_from_rom(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)233 ar9280_init_from_rom(struct athn_softc *sc, struct ieee80211_channel *c,
234     struct ieee80211_channel *extc)
235 {
236 	static const uint32_t chainoffset[] = { 0x0000, 0x2000, 0x1000 };
237 	const struct ar5416_eeprom *eep = sc->sc_eep;
238 	const struct ar5416_modal_eep_header *modal;
239 	uint32_t reg, offset;
240 	uint8_t txRxAtten;
241 	int i;
242 
243 	modal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(c)];
244 
245 	AR_WRITE(sc, AR_PHY_SWITCH_COM, modal->antCtrlCommon);
246 
247 	for (i = 0; i < AR9280_MAX_CHAINS; i++) {
248 		if (sc->sc_rxchainmask == 0x5 || sc->sc_txchainmask == 0x5)
249 			offset = chainoffset[i];
250 		else
251 			offset = i * 0x1000;
252 
253 		AR_WRITE(sc, AR_PHY_SWITCH_CHAIN_0 + offset,
254 		    modal->antCtrlChain[i]);
255 
256 		reg = AR_READ(sc, AR_PHY_TIMING_CTRL4_0 + offset);
257 		reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
258 		    modal->iqCalICh[i]);
259 		reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
260 		    modal->iqCalQCh[i]);
261 		AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0 + offset, reg);
262 
263 		if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3) {
264 			reg = AR_READ(sc, AR_PHY_GAIN_2GHZ + offset);
265 			reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
266 			    modal->bswMargin[i]);
267 			reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN1_DB,
268 			    modal->bswAtten[i]);
269 			reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
270 			    modal->xatten2Margin[i]);
271 			reg = RW(reg, AR_PHY_GAIN_2GHZ_XATTEN2_DB,
272 			    modal->xatten2Db[i]);
273 			AR_WRITE(sc, AR_PHY_GAIN_2GHZ + offset, reg);
274 		}
275 		if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3)
276 			txRxAtten = modal->txRxAttenCh[i];
277 		else	/* Workaround for ROM versions < 14.3. */
278 			txRxAtten = IEEE80211_IS_CHAN_2GHZ(c) ? 23 : 44;
279 		reg = AR_READ(sc, AR_PHY_RXGAIN + offset);
280 		reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_ATTEN,
281 		    txRxAtten);
282 		reg = RW(reg, AR9280_PHY_RXGAIN_TXRX_MARGIN,
283 		    modal->rxTxMarginCh[i]);
284 		AR_WRITE(sc, AR_PHY_RXGAIN + offset, reg);
285 	}
286 	if (IEEE80211_IS_CHAN_2GHZ(c)) {
287 		reg = AR_READ(sc, AR_AN_RF2G1_CH0);
288 		reg = RW(reg, AR_AN_RF2G1_CH0_OB, modal->ob);
289 		reg = RW(reg, AR_AN_RF2G1_CH0_DB, modal->db);
290 		AR_WRITE(sc, AR_AN_RF2G1_CH0, reg);
291 		AR_WRITE_BARRIER(sc);
292 		DELAY(100);
293 
294 		reg = AR_READ(sc, AR_AN_RF2G1_CH1);
295 		reg = RW(reg, AR_AN_RF2G1_CH1_OB, modal->ob_ch1);
296 		reg = RW(reg, AR_AN_RF2G1_CH1_DB, modal->db_ch1);
297 		AR_WRITE(sc, AR_AN_RF2G1_CH1, reg);
298 		AR_WRITE_BARRIER(sc);
299 		DELAY(100);
300 	}
301 	else {
302 		reg = AR_READ(sc, AR_AN_RF5G1_CH0);
303 		reg = RW(reg, AR_AN_RF5G1_CH0_OB5, modal->ob);
304 		reg = RW(reg, AR_AN_RF5G1_CH0_DB5, modal->db);
305 		AR_WRITE(sc, AR_AN_RF5G1_CH0, reg);
306 		AR_WRITE_BARRIER(sc);
307 		DELAY(100);
308 
309 		reg = AR_READ(sc, AR_AN_RF5G1_CH1);
310 		reg = RW(reg, AR_AN_RF5G1_CH1_OB5, modal->ob_ch1);
311 		reg = RW(reg, AR_AN_RF5G1_CH1_DB5, modal->db_ch1);
312 		AR_WRITE(sc, AR_AN_RF5G1_CH1, reg);
313 		AR_WRITE_BARRIER(sc);
314 		DELAY(100);
315 	}
316 	reg = AR_READ(sc, AR_AN_TOP2);
317 	if ((sc->sc_flags & ATHN_FLAG_USB) && IEEE80211_IS_CHAN_5GHZ(c)) {
318 		/*
319 		 * Hardcode the output voltage of x-PA bias LDO to the
320 		 * lowest value for UB94 such that the card doesn't get
321 		 * too hot.
322 		 */
323 		reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, 0);
324 	}
325 	else
326 		reg = RW(reg, AR_AN_TOP2_XPABIAS_LVL, modal->xpaBiasLvl);
327 	if (modal->flagBits & AR5416_EEP_FLAG_LOCALBIAS)
328 		reg |= AR_AN_TOP2_LOCALBIAS;
329 	else
330 		reg &= ~AR_AN_TOP2_LOCALBIAS;
331 	AR_WRITE(sc, AR_AN_TOP2, reg);
332 	AR_WRITE_BARRIER(sc);
333 	DELAY(100);
334 
335 	reg = AR_READ(sc, AR_PHY_XPA_CFG);
336 	if (modal->flagBits & AR5416_EEP_FLAG_FORCEXPAON)
337 		reg |= AR_PHY_FORCE_XPA_CFG;
338 	else
339 		reg &= ~AR_PHY_FORCE_XPA_CFG;
340 	AR_WRITE(sc, AR_PHY_XPA_CFG, reg);
341 
342 	reg = AR_READ(sc, AR_PHY_SETTLING);
343 	reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->switchSettling);
344 	AR_WRITE(sc, AR_PHY_SETTLING, reg);
345 
346 	reg = AR_READ(sc, AR_PHY_DESIRED_SZ);
347 	reg = RW(reg, AR_PHY_DESIRED_SZ_ADC, modal->adcDesiredSize);
348 	AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
349 
350 	reg =  SM(AR_PHY_RF_CTL4_TX_END_XPAA_OFF, modal->txEndToXpaOff);
351 	reg |= SM(AR_PHY_RF_CTL4_TX_END_XPAB_OFF, modal->txEndToXpaOff);
352 	reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAA_ON, modal->txFrameToXpaOn);
353 	reg |= SM(AR_PHY_RF_CTL4_FRAME_XPAB_ON, modal->txFrameToXpaOn);
354 	AR_WRITE(sc, AR_PHY_RF_CTL4, reg);
355 
356 	reg = AR_READ(sc, AR_PHY_RF_CTL3);
357 	reg = RW(reg, AR_PHY_TX_END_TO_A2_RX_ON, modal->txEndToRxOn);
358 	AR_WRITE(sc, AR_PHY_RF_CTL3, reg);
359 
360 	reg = AR_READ(sc, AR_PHY_CCA(0));
361 	reg = RW(reg, AR9280_PHY_CCA_THRESH62, modal->thresh62);
362 	AR_WRITE(sc, AR_PHY_CCA(0), reg);
363 
364 	reg = AR_READ(sc, AR_PHY_EXT_CCA0);
365 	reg = RW(reg, AR_PHY_EXT_CCA0_THRESH62, modal->thresh62);
366 	AR_WRITE(sc, AR_PHY_EXT_CCA0, reg);
367 
368 	if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_2) {
369 		reg = AR_READ(sc, AR_PHY_RF_CTL2);
370 		reg = RW(reg, AR_PHY_TX_END_DATA_START,
371 		    modal->txFrameToDataStart);
372 		reg = RW(reg, AR_PHY_TX_END_PA_ON, modal->txFrameToPaOn);
373 		AR_WRITE(sc, AR_PHY_RF_CTL2, reg);
374 	}
375 #ifndef IEEE80211_NO_HT
376 	if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_3 && extc != NULL) {
377 		/* Overwrite switch settling with HT-40 value. */
378 		reg = AR_READ(sc, AR_PHY_SETTLING);
379 		reg = RW(reg, AR_PHY_SETTLING_SWITCH, modal->swSettleHt40);
380 		AR_WRITE(sc, AR_PHY_SETTLING, reg);
381 	}
382 #endif
383 	if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_19) {
384 		reg = AR_READ(sc, AR_PHY_CCK_TX_CTRL);
385 		reg = RW(reg, AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
386 		    MS(modal->miscBits, AR5416_EEP_MISC_TX_DAC_SCALE_CCK));
387 		AR_WRITE(sc, AR_PHY_CCK_TX_CTRL, reg);
388 	}
389 	if (AR_SREV_9280_20(sc) &&
390 	    sc->sc_eep_rev >= AR_EEP_MINOR_VER_20) {
391 		reg = AR_READ(sc, AR_AN_TOP1);
392 		if (eep->baseEepHeader.dacLpMode &&
393 		    (IEEE80211_IS_CHAN_2GHZ(c) ||
394 		     !eep->baseEepHeader.dacHiPwrMode_5G))
395 			reg |= AR_AN_TOP1_DACLPMODE;
396 		else
397 			reg &= ~AR_AN_TOP1_DACLPMODE;
398 		AR_WRITE(sc, AR_AN_TOP1, reg);
399 		AR_WRITE_BARRIER(sc);
400 		DELAY(100);
401 
402 		reg = AR_READ(sc, AR_PHY_FRAME_CTL);
403 		reg = RW(reg, AR_PHY_FRAME_CTL_TX_CLIP,
404 		    MS(modal->miscBits, AR5416_EEP_MISC_TX_CLIP));
405 		AR_WRITE(sc, AR_PHY_FRAME_CTL, reg);
406 
407 		reg = AR_READ(sc, AR_PHY_TX_PWRCTRL9);
408 		reg = RW(reg, AR_PHY_TX_DESIRED_SCALE_CCK,
409 		    eep->baseEepHeader.desiredScaleCCK);
410 		AR_WRITE(sc, AR_PHY_TX_PWRCTRL9, reg);
411 	}
412 	AR_WRITE_BARRIER(sc);
413 }
414 
415 PUBLIC void
ar9280_olpc_get_pdadcs(struct athn_softc * sc,struct ieee80211_channel * c,int chain,uint8_t * boundaries,uint8_t * pdadcs,uint8_t * txgain)416 ar9280_olpc_get_pdadcs(struct athn_softc *sc, struct ieee80211_channel *c,
417     int chain, uint8_t *boundaries, uint8_t *pdadcs, uint8_t *txgain)
418 {
419 	const struct ar5416_eeprom *eep = sc->sc_eep;
420 	const struct ar_cal_data_per_freq_olpc *pierdata;
421 	const uint8_t *pierfreq;
422 	uint8_t fbin, pcdac, pwr, idx;
423 	int i, lo, hi, npiers;
424 
425 	if (IEEE80211_IS_CHAN_2GHZ(c)) {
426 		pierfreq = eep->calFreqPier2G;
427 		pierdata = (const struct ar_cal_data_per_freq_olpc *)
428 		    eep->calPierData2G[chain];
429 		npiers = AR5416_NUM_2G_CAL_PIERS;
430 	}
431 	else {
432 		pierfreq = eep->calFreqPier5G;
433 		pierdata = (const struct ar_cal_data_per_freq_olpc *)
434 		    eep->calPierData5G[chain];
435 		npiers = AR5416_NUM_5G_CAL_PIERS;
436 	}
437 	/* Find channel in ROM pier table. */
438 	fbin = athn_chan2fbin(c);
439 	athn_get_pier_ival(fbin, pierfreq, npiers, &lo, &hi);
440 
441 	/* Get average. */
442 	pwr = (pierdata[lo].pwrPdg[0][0] + pierdata[hi].pwrPdg[0][0]) / 2;
443 	pwr /= 2;	/* Convert to dB. */
444 
445 	/* Find power control digital-to-analog converter (PCDAC) value. */
446 	pcdac = pierdata[hi].pcdac[0][0];
447 	for (idx = 0; idx < AR9280_TX_GAIN_TABLE_SIZE - 1; idx++)
448 		if (pcdac <= sc->sc_tx_gain_tbl[idx])
449 			break;
450 	*txgain = idx;
451 
452 	DPRINTFN(DBG_RF, sc,
453 	    "fbin=%d lo=%d hi=%d pwr=%d pcdac=%d txgain=%d\n",
454 	    fbin, lo, hi, pwr, pcdac, idx);
455 
456 	/* Fill phase domain analog-to-digital converter (PDADC) table. */
457 	for (i = 0; i < AR_NUM_PDADC_VALUES; i++)
458 		pdadcs[i] = (i < pwr) ? 0x00 : 0xff;
459 
460 	for (i = 0; i < AR_PD_GAINS_IN_MASK; i++)
461 		boundaries[i] = AR9280_PD_GAIN_BOUNDARY_DEFAULT;
462 }
463 
464 PUBLIC void
ar9280_spur_mitigate(struct athn_softc * sc,struct ieee80211_channel * c,struct ieee80211_channel * extc)465 ar9280_spur_mitigate(struct athn_softc *sc, struct ieee80211_channel *c,
466     struct ieee80211_channel *extc)
467 {
468 	const struct ar_spur_chan *spurchans;
469 	int spur, bin, spur_delta_phase, spur_freq_sd, spur_subchannel_sd;
470 	int spur_off, range, i;
471 
472 	/* NB: Always clear. */
473 	AR_CLRBITS(sc, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
474 
475 	range = (extc != NULL) ? 19 : 10;
476 
477 	spurchans = sc->sc_ops.get_spur_chans(sc, IEEE80211_IS_CHAN_2GHZ(c));
478 	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
479 		spur = spurchans[i].spurChan;
480 		if (spur == AR_NO_SPUR)
481 			return;	/* XXX disable if it was enabled! */
482 		spur /= 10;
483 		if (IEEE80211_IS_CHAN_2GHZ(c))
484 			spur += AR_BASE_FREQ_2GHZ;
485 		else
486 			spur += AR_BASE_FREQ_5GHZ;
487 		spur -= c->ic_freq;
488 		if (abs(spur) < range)
489 			break;
490 	}
491 	if (i == AR_EEPROM_MODAL_SPURS)
492 		return;	/* XXX disable if it was enabled! */
493 	DPRINTFN(DBG_RF, sc, "enabling spur mitigation\n");
494 
495 	AR_SETBITS(sc, AR_PHY_TIMING_CTRL4_0,
496 	    AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
497 	    AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
498 	    AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
499 	    AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
500 
501 	AR_WRITE(sc, AR_PHY_SPUR_REG,
502 	    AR_PHY_SPUR_REG_MASK_RATE_CNTL |
503 	    AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
504 	    AR_PHY_SPUR_REG_MASK_RATE_SELECT |
505 	    AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
506 	    SM(AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, AR_SPUR_RSSI_THRESH));
507 
508 #ifndef IEEE80211_NO_HT
509 	if (extc != NULL) {
510 		spur_delta_phase = (spur * 262144) / 10;
511 		if (spur < 0) {
512 			spur_subchannel_sd = 1;
513 			spur_off = spur + 10;
514 		}
515 		else {
516 			spur_subchannel_sd = 0;
517 			spur_off = spur - 10;
518 		}
519 	}
520 	else
521 #endif
522 	{
523 		spur_delta_phase = (spur * 524288) / 10;
524 		spur_subchannel_sd = 0;
525 		spur_off = spur;
526 	}
527 	if (IEEE80211_IS_CHAN_2GHZ(c))
528 		spur_freq_sd = (spur_off * 2048) / 44;
529 	else
530 		spur_freq_sd = (spur_off * 2048) / 40;
531 
532 	AR_WRITE(sc, AR_PHY_TIMING11,
533 	    AR_PHY_TIMING11_USE_SPUR_IN_AGC |
534 	    SM(AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd) |
535 	    SM(AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase));
536 
537 	AR_WRITE(sc, AR_PHY_SFCORR_EXT,
538 	    SM(AR_PHY_SFCORR_SPUR_SUBCHNL_SD, spur_subchannel_sd));
539 	AR_WRITE_BARRIER(sc);
540 
541 	bin = spur * 320;
542 	ar5008_set_viterbi_mask(sc, bin);
543 }
544 
545 PUBLIC void
ar9280_reset_rx_gain(struct athn_softc * sc,struct ieee80211_channel * c)546 ar9280_reset_rx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
547 {
548 	const struct athn_gain *prog = sc->sc_rx_gain;
549 	const uint32_t *pvals;
550 	int i;
551 
552 	if (IEEE80211_IS_CHAN_2GHZ(c))
553 		pvals = prog->vals_2g;
554 	else
555 		pvals = prog->vals_5g;
556 	for (i = 0; i < prog->nregs; i++)
557 		AR_WRITE(sc, prog->regs[i], pvals[i]);
558 }
559 
560 PUBLIC void
ar9280_reset_tx_gain(struct athn_softc * sc,struct ieee80211_channel * c)561 ar9280_reset_tx_gain(struct athn_softc *sc, struct ieee80211_channel *c)
562 {
563 	const struct athn_gain *prog = sc->sc_tx_gain;
564 	const uint32_t *pvals;
565 	int i;
566 
567 	if (IEEE80211_IS_CHAN_2GHZ(c))
568 		pvals = prog->vals_2g;
569 	else
570 		pvals = prog->vals_5g;
571 	for (i = 0; i < prog->nregs; i++)
572 		AR_WRITE(sc, prog->regs[i], pvals[i]);
573 }
574 
575 Static void
ar9280_olpc_init(struct athn_softc * sc)576 ar9280_olpc_init(struct athn_softc *sc)
577 {
578 	uint32_t reg;
579 	int i;
580 
581 	/* Save original Tx gain values. */
582 	for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
583 		reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
584 		sc->sc_tx_gain_tbl[i] = MS(reg, AR_PHY_TX_GAIN);
585 	}
586 	/* Initial Tx gain temperature compensation. */
587 	sc->sc_tcomp = 0;
588 }
589 
590 Static void
ar9280_olpc_temp_compensation(struct athn_softc * sc)591 ar9280_olpc_temp_compensation(struct athn_softc *sc)
592 {
593 	const struct ar5416_eeprom *eep = sc->sc_eep;
594 	int8_t pdadc, txgain, tcomp;
595 	uint32_t reg;
596 	int i;
597 
598 	reg = AR_READ(sc, AR_PHY_TX_PWRCTRL4);
599 	pdadc = MS(reg, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
600 	DPRINTFN(DBG_RF, sc, "PD Avg Out=%d\n", pdadc);
601 
602 	if (sc->sc_pdadc == 0 || pdadc == 0)
603 		return;	/* No frames transmitted yet. */
604 
605 	/* Compute Tx gain temperature compensation. */
606 	if (sc->sc_eep_rev >= AR_EEP_MINOR_VER_20 &&
607 	    eep->baseEepHeader.dacHiPwrMode_5G)
608 		tcomp = (pdadc - sc->sc_pdadc + 4) / 8;
609 	else
610 		tcomp = (pdadc - sc->sc_pdadc + 5) / 10;
611 	DPRINTFN(DBG_RF, sc, "OLPC temp compensation=%d\n", tcomp);
612 
613 	if (tcomp == sc->sc_tcomp)
614 		return;	/* Don't rewrite the same values. */
615 	sc->sc_tcomp = tcomp;
616 
617 	/* Adjust Tx gain values. */
618 	for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
619 		txgain = sc->sc_tx_gain_tbl[i] - tcomp;
620 		if (txgain < 0)
621 			txgain = 0;
622 		reg = AR_READ(sc, AR_PHY_TX_GAIN_TBL(i));
623 		reg = RW(reg, AR_PHY_TX_GAIN, txgain);
624 		AR_WRITE(sc, AR_PHY_TX_GAIN_TBL(i), reg);
625 	}
626 	AR_WRITE_BARRIER(sc);
627 }
628