1 /* $NetBSD: amr.c,v 1.68 2024/02/02 22:00:33 andvar Exp $ */
2
3 /*-
4 * Copyright (c) 2002, 2003 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Andrew Doran.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*-
33 * Copyright (c) 1999,2000 Michael Smith
34 * Copyright (c) 2000 BSDi
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions
39 * are met:
40 * 1. Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * 2. Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in the
44 * documentation and/or other materials provided with the distribution.
45 *
46 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
47 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
48 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
49 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
50 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
51 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
52 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
53 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
54 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
55 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
56 * SUCH DAMAGE.
57 *
58 * from FreeBSD: amr_pci.c,v 1.5 2000/08/30 07:52:40 msmith Exp
59 * from FreeBSD: amr.c,v 1.16 2000/08/30 07:52:40 msmith Exp
60 */
61
62 /*
63 * Driver for AMI RAID controllers.
64 */
65
66 #include <sys/cdefs.h>
67 __KERNEL_RCSID(0, "$NetBSD: amr.c,v 1.68 2024/02/02 22:00:33 andvar Exp $");
68
69 #include <sys/param.h>
70 #include <sys/systm.h>
71 #include <sys/kernel.h>
72 #include <sys/device.h>
73 #include <sys/queue.h>
74 #include <sys/proc.h>
75 #include <sys/buf.h>
76 #include <sys/malloc.h>
77 #include <sys/conf.h>
78 #include <sys/kthread.h>
79 #include <sys/kauth.h>
80 #include <sys/mutex.h>
81 #include <sys/condvar.h>
82 #include <sys/module.h>
83
84 #include <machine/endian.h>
85 #include <sys/bus.h>
86
87 #include <dev/pci/pcidevs.h>
88 #include <dev/pci/pcivar.h>
89 #include <dev/pci/amrreg.h>
90 #include <dev/pci/amrvar.h>
91 #include <dev/pci/amrio.h>
92
93 #include "locators.h"
94
95 #include "ioconf.h"
96
97 static void amr_attach(device_t, device_t, void *);
98 static void amr_ccb_dump(struct amr_softc *, struct amr_ccb *);
99 static void *amr_enquire(struct amr_softc *, u_int8_t, u_int8_t, u_int8_t,
100 void *);
101 static int amr_init(struct amr_softc *, const char *,
102 struct pci_attach_args *pa);
103 static int amr_intr(void *);
104 static int amr_match(device_t, cfdata_t, void *);
105 static int amr_rescan(device_t, const char *, const int *);
106 static int amr_print(void *, const char *);
107 static void amr_shutdown(void *);
108 static void amr_teardown(struct amr_softc *);
109 static void amr_quartz_thread(void *);
110 static void amr_std_thread(void *);
111
112 static int amr_quartz_get_work(struct amr_softc *,
113 struct amr_mailbox_resp *);
114 static int amr_quartz_submit(struct amr_softc *, struct amr_ccb *);
115 static int amr_std_get_work(struct amr_softc *, struct amr_mailbox_resp *);
116 static int amr_std_submit(struct amr_softc *, struct amr_ccb *);
117
118 static dev_type_open(amropen);
119 static dev_type_close(amrclose);
120 static dev_type_ioctl(amrioctl);
121
122 CFATTACH_DECL3_NEW(amr, sizeof(struct amr_softc),
123 amr_match, amr_attach, NULL, NULL, amr_rescan, NULL, 0);
124
125 const struct cdevsw amr_cdevsw = {
126 .d_open = amropen,
127 .d_close = amrclose,
128 .d_read = noread,
129 .d_write = nowrite,
130 .d_ioctl = amrioctl,
131 .d_stop = nostop,
132 .d_tty = notty,
133 .d_poll = nopoll,
134 .d_mmap = nommap,
135 .d_kqfilter = nokqfilter,
136 .d_discard = nodiscard,
137 .d_flag = D_OTHER
138 };
139
140 extern struct cfdriver amr_cd;
141
142 #define AT_QUARTZ 0x01 /* `Quartz' chipset */
143 #define AT_SIG 0x02 /* Check for signature */
144
145 static struct amr_pci_type {
146 u_short apt_vendor;
147 u_short apt_product;
148 u_short apt_flags;
149 } const amr_pci_type[] = {
150 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID, 0 },
151 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID2, 0 },
152 { PCI_VENDOR_AMI, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ },
153 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ },
154 { PCI_VENDOR_INTEL, PCI_PRODUCT_AMI_MEGARAID3, AT_QUARTZ | AT_SIG },
155 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ },
156 { PCI_VENDOR_INTEL, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ },
157 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ },
158 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI, AT_QUARTZ },
159 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4DI_2, AT_QUARTZ },
160 { PCI_VENDOR_DELL, PCI_PRODUCT_DELL_PERC_4ESI, AT_QUARTZ },
161 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_PERC_4SC, AT_QUARTZ },
162 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320X, AT_QUARTZ },
163 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_320E, AT_QUARTZ },
164 { PCI_VENDOR_SYMBIOS, PCI_PRODUCT_SYMBIOS_MEGARAID_300X, AT_QUARTZ },
165 };
166
167 static struct amr_typestr {
168 const char *at_str;
169 int at_sig;
170 } const amr_typestr[] = {
171 { "Series 431", AMR_SIG_431 },
172 { "Series 438", AMR_SIG_438 },
173 { "Series 466", AMR_SIG_466 },
174 { "Series 467", AMR_SIG_467 },
175 { "Series 490", AMR_SIG_490 },
176 { "Series 762", AMR_SIG_762 },
177 { "HP NetRAID (T5)", AMR_SIG_T5 },
178 { "HP NetRAID (T7)", AMR_SIG_T7 },
179 };
180
181 static struct {
182 const char *ds_descr;
183 int ds_happy;
184 } const amr_dstate[] = {
185 { "offline", 0 },
186 { "degraded", 1 },
187 { "optimal", 1 },
188 { "online", 1 },
189 { "failed", 0 },
190 { "rebuilding", 1 },
191 { "hotspare", 0 },
192 };
193
194 static void *amr_sdh;
195
196 static kcondvar_t thread_cv;
197 static kmutex_t thread_mutex;
198
199 static int amr_max_segs;
200 int amr_max_xfer;
201
202 static inline u_int8_t
amr_inb(struct amr_softc * amr,int off)203 amr_inb(struct amr_softc *amr, int off)
204 {
205 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1,
206 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ);
207 return (bus_space_read_1(amr->amr_iot, amr->amr_ioh, off));
208 }
209
210 static inline u_int32_t
amr_inl(struct amr_softc * amr,int off)211 amr_inl(struct amr_softc *amr, int off)
212 {
213 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4,
214 BUS_SPACE_BARRIER_WRITE | BUS_SPACE_BARRIER_READ);
215 return (bus_space_read_4(amr->amr_iot, amr->amr_ioh, off));
216 }
217
218 static inline void
amr_outb(struct amr_softc * amr,int off,u_int8_t val)219 amr_outb(struct amr_softc *amr, int off, u_int8_t val)
220 {
221 bus_space_write_1(amr->amr_iot, amr->amr_ioh, off, val);
222 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 1,
223 BUS_SPACE_BARRIER_WRITE);
224 }
225
226 static inline void
amr_outl(struct amr_softc * amr,int off,u_int32_t val)227 amr_outl(struct amr_softc *amr, int off, u_int32_t val)
228 {
229 bus_space_write_4(amr->amr_iot, amr->amr_ioh, off, val);
230 bus_space_barrier(amr->amr_iot, amr->amr_ioh, off, 4,
231 BUS_SPACE_BARRIER_WRITE);
232 }
233
234 /*
235 * Match a supported device.
236 */
237 static int
amr_match(device_t parent,cfdata_t match,void * aux)238 amr_match(device_t parent, cfdata_t match, void *aux)
239 {
240 struct pci_attach_args *pa;
241 pcireg_t s;
242 int i;
243
244 pa = (struct pci_attach_args *)aux;
245
246 /*
247 * Don't match the device if it's operating in I2O mode. In this
248 * case it should be handled by the `iop' driver.
249 */
250 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_I2O)
251 return (0);
252
253 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++)
254 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor &&
255 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product)
256 break;
257
258 if (i == sizeof(amr_pci_type) / sizeof(amr_pci_type[0]))
259 return (0);
260
261 if ((amr_pci_type[i].apt_flags & AT_SIG) == 0)
262 return (1);
263
264 s = pci_conf_read(pa->pa_pc, pa->pa_tag, AMR_QUARTZ_SIG_REG) & 0xffff;
265 return (s == AMR_QUARTZ_SIG0 || s == AMR_QUARTZ_SIG1);
266 }
267
268 /*
269 * Attach a supported device.
270 */
271 static void
amr_attach(device_t parent,device_t self,void * aux)272 amr_attach(device_t parent, device_t self, void *aux)
273 {
274 struct pci_attach_args *pa;
275 const struct amr_pci_type *apt;
276 struct amr_softc *amr;
277 pci_chipset_tag_t pc;
278 pci_intr_handle_t ih;
279 const char *intrstr;
280 pcireg_t reg;
281 int rseg, i, size, rv, memreg, ioreg;
282 struct amr_ccb *ac;
283 char intrbuf[PCI_INTRSTR_LEN];
284
285 aprint_naive(": RAID controller\n");
286
287 amr = device_private(self);
288 amr->amr_dv = self;
289
290 mutex_init(&amr->amr_mutex, MUTEX_DEFAULT, IPL_BIO);
291
292 pa = (struct pci_attach_args *)aux;
293 pc = pa->pa_pc;
294
295 for (i = 0; i < sizeof(amr_pci_type) / sizeof(amr_pci_type[0]); i++)
296 if (PCI_VENDOR(pa->pa_id) == amr_pci_type[i].apt_vendor &&
297 PCI_PRODUCT(pa->pa_id) == amr_pci_type[i].apt_product)
298 break;
299 apt = amr_pci_type + i;
300
301 memreg = ioreg = 0;
302 for (i = 0x10; i <= 0x14; i += 4) {
303 reg = pci_conf_read(pc, pa->pa_tag, i);
304 switch (PCI_MAPREG_TYPE(reg)) {
305 case PCI_MAPREG_TYPE_MEM:
306 if (PCI_MAPREG_MEM_SIZE(reg) != 0)
307 memreg = i;
308 break;
309 case PCI_MAPREG_TYPE_IO:
310 if (PCI_MAPREG_IO_SIZE(reg) != 0)
311 ioreg = i;
312 break;
313 }
314 }
315
316 if (memreg && pci_mapreg_map(pa, memreg, PCI_MAPREG_TYPE_MEM, 0,
317 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0)
318 ;
319 else if (ioreg && pci_mapreg_map(pa, ioreg, PCI_MAPREG_TYPE_IO, 0,
320 &amr->amr_iot, &amr->amr_ioh, NULL, &amr->amr_ios) == 0)
321 ;
322 else {
323 aprint_error("can't map control registers\n");
324 amr_teardown(amr);
325 return;
326 }
327
328 amr->amr_flags |= AMRF_PCI_REGS;
329 amr->amr_dmat = pa->pa_dmat;
330 amr->amr_pc = pa->pa_pc;
331
332 /* Enable the device. */
333 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
334 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
335 reg | PCI_COMMAND_MASTER_ENABLE);
336
337 /* Map and establish the interrupt. */
338 if (pci_intr_map(pa, &ih)) {
339 aprint_error("can't map interrupt\n");
340 amr_teardown(amr);
341 return;
342 }
343 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
344 amr->amr_ih = pci_intr_establish_xname(pc, ih, IPL_BIO, amr_intr, amr,
345 device_xname(self));
346 if (amr->amr_ih == NULL) {
347 aprint_error("can't establish interrupt");
348 if (intrstr != NULL)
349 aprint_error(" at %s", intrstr);
350 aprint_error("\n");
351 amr_teardown(amr);
352 return;
353 }
354 amr->amr_flags |= AMRF_PCI_INTR;
355
356 /*
357 * Allocate space for the mailbox and S/G lists. Some controllers
358 * don't like S/G lists to be located below 0x2000, so we allocate
359 * enough slop to enable us to compensate.
360 *
361 * The standard mailbox structure needs to be aligned on a 16-byte
362 * boundary. The 64-bit mailbox has one extra field, 4 bytes in
363 * size, which precedes the standard mailbox.
364 */
365 size = AMR_SGL_SIZE * AMR_MAX_CMDS + 0x2000;
366 amr->amr_dmasize = size;
367
368 if ((rv = bus_dmamem_alloc(amr->amr_dmat, size, PAGE_SIZE, 0,
369 &amr->amr_dmaseg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
370 aprint_error_dev(amr->amr_dv,
371 "unable to allocate buffer, rv = %d\n", rv);
372 amr_teardown(amr);
373 return;
374 }
375 amr->amr_flags |= AMRF_DMA_ALLOC;
376
377 if ((rv = bus_dmamem_map(amr->amr_dmat, &amr->amr_dmaseg, rseg, size,
378 (void **)&amr->amr_mbox,
379 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
380 aprint_error_dev(amr->amr_dv, "unable to map buffer, rv = %d\n",
381 rv);
382 amr_teardown(amr);
383 return;
384 }
385 amr->amr_flags |= AMRF_DMA_MAP;
386
387 if ((rv = bus_dmamap_create(amr->amr_dmat, size, 1, size, 0,
388 BUS_DMA_NOWAIT, &amr->amr_dmamap)) != 0) {
389 aprint_error_dev(amr->amr_dv,
390 "unable to create buffer DMA map, rv = %d\n", rv);
391 amr_teardown(amr);
392 return;
393 }
394 amr->amr_flags |= AMRF_DMA_CREATE;
395
396 if ((rv = bus_dmamap_load(amr->amr_dmat, amr->amr_dmamap,
397 amr->amr_mbox, size, NULL, BUS_DMA_NOWAIT)) != 0) {
398 aprint_error_dev(amr->amr_dv,
399 "unable to load buffer DMA map, rv = %d\n", rv);
400 amr_teardown(amr);
401 return;
402 }
403 amr->amr_flags |= AMRF_DMA_LOAD;
404
405 memset(amr->amr_mbox, 0, size);
406
407 amr->amr_mbox_paddr = amr->amr_dmamap->dm_segs[0].ds_addr;
408 amr->amr_sgls_paddr = (amr->amr_mbox_paddr + 0x1fff) & ~0x1fff;
409 amr->amr_sgls = (struct amr_sgentry *)((char *)amr->amr_mbox +
410 amr->amr_sgls_paddr - amr->amr_dmamap->dm_segs[0].ds_addr);
411
412 /*
413 * Allocate and initialise the command control blocks.
414 */
415 ac = malloc(sizeof(*ac) * AMR_MAX_CMDS, M_DEVBUF, M_WAITOK | M_ZERO);
416 amr->amr_ccbs = ac;
417 SLIST_INIT(&amr->amr_ccb_freelist);
418 TAILQ_INIT(&amr->amr_ccb_active);
419 amr->amr_flags |= AMRF_CCBS;
420
421 if (amr_max_xfer == 0) {
422 amr_max_xfer = uimin(((AMR_MAX_SEGS - 1) * PAGE_SIZE), MAXPHYS);
423 amr_max_segs = (amr_max_xfer + (PAGE_SIZE * 2) - 1) / PAGE_SIZE;
424 }
425
426 for (i = 0; i < AMR_MAX_CMDS; i++, ac++) {
427 rv = bus_dmamap_create(amr->amr_dmat, amr_max_xfer,
428 amr_max_segs, amr_max_xfer, 0,
429 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &ac->ac_xfer_map);
430 if (rv != 0)
431 break;
432
433 ac->ac_ident = i;
434 cv_init(&ac->ac_cv, "amr1ccb");
435 mutex_init(&ac->ac_mutex, MUTEX_DEFAULT, IPL_NONE);
436 amr_ccb_free(amr, ac);
437 }
438 if (i != AMR_MAX_CMDS) {
439 aprint_error_dev(amr->amr_dv, "memory exhausted\n");
440 amr_teardown(amr);
441 return;
442 }
443
444 /*
445 * Take care of model-specific tasks.
446 */
447 if ((apt->apt_flags & AT_QUARTZ) != 0) {
448 amr->amr_submit = amr_quartz_submit;
449 amr->amr_get_work = amr_quartz_get_work;
450 } else {
451 amr->amr_submit = amr_std_submit;
452 amr->amr_get_work = amr_std_get_work;
453
454 /* Notify the controller of the mailbox location. */
455 amr_outl(amr, AMR_SREG_MBOX, (u_int32_t)amr->amr_mbox_paddr + 16);
456 amr_outb(amr, AMR_SREG_MBOX_ENABLE, AMR_SMBOX_ENABLE_ADDR);
457
458 /* Clear outstanding interrupts and enable interrupts. */
459 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR);
460 amr_outb(amr, AMR_SREG_TOGL,
461 amr_inb(amr, AMR_SREG_TOGL) | AMR_STOGL_ENABLE);
462 }
463
464 /*
465 * Retrieve parameters, and tell the world about us.
466 */
467 amr->amr_enqbuf = malloc(AMR_ENQUIRY_BUFSIZE, M_DEVBUF, M_WAITOK);
468 amr->amr_flags |= AMRF_ENQBUF;
469 amr->amr_maxqueuecnt = i;
470 aprint_normal(": AMI RAID ");
471 if (amr_init(amr, intrstr, pa) != 0) {
472 amr_teardown(amr);
473 return;
474 }
475
476 /*
477 * Cap the maximum number of outstanding commands. AMI's Linux
478 * driver doesn't trust the controller's reported value, and lockups
479 * have been seen when we do.
480 */
481 amr->amr_maxqueuecnt = uimin(amr->amr_maxqueuecnt, AMR_MAX_CMDS);
482 if (amr->amr_maxqueuecnt > i)
483 amr->amr_maxqueuecnt = i;
484
485 /* Set our `shutdownhook' before we start any device activity. */
486 if (amr_sdh == NULL)
487 amr_sdh = shutdownhook_establish(amr_shutdown, NULL);
488
489 /* Attach sub-devices. */
490 amr_rescan(self, NULL, NULL);
491
492 SIMPLEQ_INIT(&amr->amr_ccb_queue);
493
494 cv_init(&thread_cv, "amrwdog");
495 mutex_init(&thread_mutex, MUTEX_DEFAULT, IPL_NONE);
496
497 if ((apt->apt_flags & AT_QUARTZ) == 0) {
498 rv = kthread_create(PRI_NONE, KTHREAD_MPSAFE, NULL,
499 amr_std_thread, amr, &amr->amr_thread,
500 "%s", device_xname(amr->amr_dv));
501 } else {
502 rv = kthread_create(PRI_NONE, KTHREAD_MPSAFE, NULL,
503 amr_quartz_thread, amr, &amr->amr_thread,
504 "%s", device_xname(amr->amr_dv));
505 }
506 if (rv != 0)
507 aprint_error_dev(amr->amr_dv, "unable to create thread (%d)",
508 rv);
509 else
510 amr->amr_flags |= AMRF_THREAD;
511 }
512
513 static int
amr_rescan(device_t self,const char * ifattr,const int * ulocs)514 amr_rescan(device_t self, const char *ifattr, const int *ulocs)
515 {
516 int j;
517 int locs[AMRCF_NLOCS];
518 struct amr_attach_args amra;
519 struct amr_softc *amr;
520
521 amr = device_private(self);
522 for (j = 0; j < amr->amr_numdrives; j++) {
523 if (amr->amr_drive[j].al_dv)
524 continue;
525 if (amr->amr_drive[j].al_size == 0)
526 continue;
527 amra.amra_unit = j;
528
529 locs[AMRCF_UNIT] = j;
530
531 amr->amr_drive[j].al_dv =
532 config_found(amr->amr_dv, &amra, amr_print,
533 CFARGS(.submatch = config_stdsubmatch,
534 .iattr = ifattr,
535 .locators = locs));
536 }
537 return 0;
538 }
539
540 /*
541 * Free up resources.
542 */
543 static void
amr_teardown(struct amr_softc * amr)544 amr_teardown(struct amr_softc *amr)
545 {
546 struct amr_ccb *ac;
547 int fl;
548
549 fl = amr->amr_flags;
550
551 if ((fl & AMRF_THREAD) != 0) {
552 amr->amr_flags |= AMRF_THREAD_EXIT;
553 mutex_enter(&thread_mutex);
554 cv_broadcast(&thread_cv);
555 mutex_exit(&thread_mutex);
556 while ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) {
557 mutex_enter(&thread_mutex);
558 cv_wait(&thread_cv, &thread_mutex);
559 mutex_exit(&thread_mutex);
560 }
561 }
562 if ((fl & AMRF_CCBS) != 0) {
563 SLIST_FOREACH(ac, &amr->amr_ccb_freelist, ac_chain.slist) {
564 bus_dmamap_destroy(amr->amr_dmat, ac->ac_xfer_map);
565 }
566 free(amr->amr_ccbs, M_DEVBUF);
567 }
568 if ((fl & AMRF_ENQBUF) != 0)
569 free(amr->amr_enqbuf, M_DEVBUF);
570 if ((fl & AMRF_DMA_LOAD) != 0)
571 bus_dmamap_unload(amr->amr_dmat, amr->amr_dmamap);
572 if ((fl & AMRF_DMA_MAP) != 0)
573 bus_dmamem_unmap(amr->amr_dmat, (void *)amr->amr_mbox,
574 amr->amr_dmasize);
575 if ((fl & AMRF_DMA_ALLOC) != 0)
576 bus_dmamem_free(amr->amr_dmat, &amr->amr_dmaseg, 1);
577 if ((fl & AMRF_DMA_CREATE) != 0)
578 bus_dmamap_destroy(amr->amr_dmat, amr->amr_dmamap);
579 if ((fl & AMRF_PCI_INTR) != 0)
580 pci_intr_disestablish(amr->amr_pc, amr->amr_ih);
581 if ((fl & AMRF_PCI_REGS) != 0)
582 bus_space_unmap(amr->amr_iot, amr->amr_ioh, amr->amr_ios);
583 }
584
585 /*
586 * Print autoconfiguration message for a sub-device.
587 */
588 static int
amr_print(void * aux,const char * pnp)589 amr_print(void *aux, const char *pnp)
590 {
591 struct amr_attach_args *amra;
592
593 amra = (struct amr_attach_args *)aux;
594
595 if (pnp != NULL)
596 aprint_normal("block device at %s", pnp);
597 aprint_normal(" unit %d", amra->amra_unit);
598 return (UNCONF);
599 }
600
601 /*
602 * Retrieve operational parameters and describe the controller.
603 */
604 static int
amr_init(struct amr_softc * amr,const char * intrstr,struct pci_attach_args * pa)605 amr_init(struct amr_softc *amr, const char *intrstr,
606 struct pci_attach_args *pa)
607 {
608 struct amr_adapter_info *aa;
609 struct amr_prodinfo *ap;
610 struct amr_enquiry *ae;
611 struct amr_enquiry3 *aex;
612 const char *prodstr;
613 u_int i, sig, ishp;
614 char sbuf[64];
615
616 /*
617 * Try to get 40LD product info, which tells us what the card is
618 * labelled as.
619 */
620 ap = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_PRODUCT_INFO, 0,
621 amr->amr_enqbuf);
622 if (ap != NULL) {
623 aprint_normal("<%.80s>\n", ap->ap_product);
624 if (intrstr != NULL)
625 aprint_normal_dev(amr->amr_dv, "interrupting at %s\n",
626 intrstr);
627 aprint_normal_dev(amr->amr_dv,
628 "firmware %.16s, BIOS %.16s, %dMB RAM\n",
629 ap->ap_firmware, ap->ap_bios, le16toh(ap->ap_memsize));
630
631 amr->amr_maxqueuecnt = ap->ap_maxio;
632
633 /*
634 * Fetch and record state of logical drives.
635 */
636 aex = amr_enquire(amr, AMR_CMD_CONFIG, AMR_CONFIG_ENQ3,
637 AMR_CONFIG_ENQ3_SOLICITED_FULL, amr->amr_enqbuf);
638 if (aex == NULL) {
639 aprint_error_dev(amr->amr_dv, "ENQUIRY3 failed\n");
640 return (-1);
641 }
642
643 if (aex->ae_numldrives > __arraycount(aex->ae_drivestate)) {
644 aprint_error_dev(amr->amr_dv, "Inquiry returned more "
645 "drives (%d) than the array can handle (%zu)\n",
646 aex->ae_numldrives,
647 __arraycount(aex->ae_drivestate));
648 aex->ae_numldrives = __arraycount(aex->ae_drivestate);
649 }
650 if (aex->ae_numldrives > AMR_MAX_UNITS) {
651 aprint_error_dev(amr->amr_dv,
652 "adjust AMR_MAX_UNITS to %d (currently %d)\n",
653 AMR_MAX_UNITS, amr->amr_numdrives);
654 amr->amr_numdrives = AMR_MAX_UNITS;
655 } else
656 amr->amr_numdrives = aex->ae_numldrives;
657
658 for (i = 0; i < amr->amr_numdrives; i++) {
659 amr->amr_drive[i].al_size =
660 le32toh(aex->ae_drivesize[i]);
661 amr->amr_drive[i].al_state = aex->ae_drivestate[i];
662 amr->amr_drive[i].al_properties = aex->ae_driveprop[i];
663 }
664
665 return (0);
666 }
667
668 /*
669 * Try 8LD extended ENQUIRY to get the controller signature. Once
670 * found, search for a product description.
671 */
672 ae = amr_enquire(amr, AMR_CMD_EXT_ENQUIRY2, 0, 0, amr->amr_enqbuf);
673 if (ae != NULL) {
674 i = 0;
675 sig = le32toh(ae->ae_signature);
676
677 while (i < sizeof(amr_typestr) / sizeof(amr_typestr[0])) {
678 if (amr_typestr[i].at_sig == sig)
679 break;
680 i++;
681 }
682 if (i == sizeof(amr_typestr) / sizeof(amr_typestr[0])) {
683 snprintf(sbuf, sizeof(sbuf),
684 "unknown ENQUIRY2 sig (0x%08x)", sig);
685 prodstr = sbuf;
686 } else
687 prodstr = amr_typestr[i].at_str;
688 } else {
689 ae = amr_enquire(amr, AMR_CMD_ENQUIRY, 0, 0, amr->amr_enqbuf);
690 if (ae == NULL) {
691 aprint_error_dev(amr->amr_dv,
692 "unsupported controller\n");
693 return (-1);
694 }
695
696 switch (PCI_PRODUCT(pa->pa_id)) {
697 case PCI_PRODUCT_AMI_MEGARAID:
698 prodstr = "Series 428";
699 break;
700 case PCI_PRODUCT_AMI_MEGARAID2:
701 prodstr = "Series 434";
702 break;
703 default:
704 snprintf(sbuf, sizeof(sbuf),
705 "unknown PCI dev (0x%04x)",
706 PCI_PRODUCT(pa->pa_id));
707 prodstr = sbuf;
708 break;
709 }
710 }
711
712 /*
713 * HP NetRaid controllers have a special encoding of the firmware
714 * and BIOS versions. The AMI version seems to have it as strings
715 * whereas the HP version does it with a leading uppercase character
716 * and two binary numbers.
717 */
718 aa = &ae->ae_adapter;
719
720 if (aa->aa_firmware[2] >= 'A' && aa->aa_firmware[2] <= 'Z' &&
721 aa->aa_firmware[1] < ' ' && aa->aa_firmware[0] < ' ' &&
722 aa->aa_bios[2] >= 'A' && aa->aa_bios[2] <= 'Z' &&
723 aa->aa_bios[1] < ' ' && aa->aa_bios[0] < ' ') {
724 if (le32toh(ae->ae_signature) == AMR_SIG_438) {
725 /* The AMI 438 is a NetRaid 3si in HP-land. */
726 prodstr = "HP NetRaid 3si";
727 }
728 ishp = 1;
729 } else
730 ishp = 0;
731
732 aprint_normal("<%s>\n", prodstr);
733 if (intrstr != NULL)
734 aprint_normal_dev(amr->amr_dv, "interrupting at %s\n",
735 intrstr);
736
737 if (ishp)
738 aprint_normal_dev(amr->amr_dv, "firmware <%c.%02d.%02d>, "
739 "BIOS <%c.%02d.%02d>, %dMB RAM\n", aa->aa_firmware[2],
740 aa->aa_firmware[1], aa->aa_firmware[0], aa->aa_bios[2],
741 aa->aa_bios[1], aa->aa_bios[0], aa->aa_memorysize);
742 else
743 aprint_normal_dev(amr->amr_dv, "firmware <%.4s>, BIOS <%.4s>, "
744 "%dMB RAM\n", aa->aa_firmware, aa->aa_bios,
745 aa->aa_memorysize);
746
747 amr->amr_maxqueuecnt = aa->aa_maxio;
748
749 /*
750 * Record state of logical drives.
751 */
752 if (ae->ae_ldrv.al_numdrives > __arraycount(ae->ae_ldrv.al_size)) {
753 aprint_error_dev(amr->amr_dv, "Inquiry returned more drives "
754 "(%d) than the array can handle (%zu)\n",
755 ae->ae_ldrv.al_numdrives,
756 __arraycount(ae->ae_ldrv.al_size));
757 ae->ae_ldrv.al_numdrives = __arraycount(ae->ae_ldrv.al_size);
758 }
759 if (ae->ae_ldrv.al_numdrives > AMR_MAX_UNITS) {
760 aprint_error_dev(amr->amr_dv,
761 "adjust AMR_MAX_UNITS to %d (currently %d)\n",
762 ae->ae_ldrv.al_numdrives, AMR_MAX_UNITS);
763 amr->amr_numdrives = AMR_MAX_UNITS;
764 } else
765 amr->amr_numdrives = ae->ae_ldrv.al_numdrives;
766
767 for (i = 0; i < amr->amr_numdrives; i++) {
768 amr->amr_drive[i].al_size = le32toh(ae->ae_ldrv.al_size[i]);
769 amr->amr_drive[i].al_state = ae->ae_ldrv.al_state[i];
770 amr->amr_drive[i].al_properties = ae->ae_ldrv.al_properties[i];
771 }
772
773 return (0);
774 }
775
776 /*
777 * Flush the internal cache on each configured controller. Called at
778 * shutdown time.
779 */
780 static void
amr_shutdown(void * cookie)781 amr_shutdown(void *cookie)
782 {
783 extern struct cfdriver amr_cd;
784 struct amr_softc *amr;
785 struct amr_ccb *ac;
786 int i, rv;
787
788 for (i = 0; i < amr_cd.cd_ndevs; i++) {
789 if ((amr = device_lookup_private(&amr_cd, i)) == NULL)
790 continue;
791
792 if ((rv = amr_ccb_alloc(amr, &ac)) == 0) {
793 ac->ac_cmd.mb_command = AMR_CMD_FLUSH;
794 rv = amr_ccb_poll(amr, ac, 30000);
795 amr_ccb_free(amr, ac);
796 }
797 if (rv != 0)
798 aprint_error_dev(amr->amr_dv,
799 "unable to flush cache (%d)\n", rv);
800 }
801 }
802
803 /*
804 * Interrupt service routine.
805 */
806 static int
amr_intr(void * cookie)807 amr_intr(void *cookie)
808 {
809 struct amr_softc *amr;
810 struct amr_ccb *ac;
811 struct amr_mailbox_resp mbox;
812 u_int i, forus, idx;
813
814 amr = cookie;
815 forus = 0;
816
817 mutex_spin_enter(&amr->amr_mutex);
818
819 while ((*amr->amr_get_work)(amr, &mbox) == 0) {
820 /* Iterate over completed commands in this result. */
821 for (i = 0; i < mbox.mb_nstatus; i++) {
822 idx = mbox.mb_completed[i] - 1;
823 ac = amr->amr_ccbs + idx;
824
825 if (idx >= amr->amr_maxqueuecnt) {
826 printf("%s: bad status (bogus ID: %u=%u)\n",
827 device_xname(amr->amr_dv), i, idx);
828 continue;
829 }
830
831 if ((ac->ac_flags & AC_ACTIVE) == 0) {
832 printf("%s: bad status (not active; 0x04%x)\n",
833 device_xname(amr->amr_dv), ac->ac_flags);
834 continue;
835 }
836
837 ac->ac_status = mbox.mb_status;
838 ac->ac_flags = (ac->ac_flags & ~AC_ACTIVE) |
839 AC_COMPLETE;
840 TAILQ_REMOVE(&amr->amr_ccb_active, ac, ac_chain.tailq);
841
842 if ((ac->ac_flags & AC_MOAN) != 0)
843 printf("%s: ccb %d completed\n",
844 device_xname(amr->amr_dv), ac->ac_ident);
845
846 /* Pass notification to upper layers. */
847 mutex_spin_exit(&amr->amr_mutex);
848 if (ac->ac_handler != NULL) {
849 (*ac->ac_handler)(ac);
850 } else {
851 mutex_enter(&ac->ac_mutex);
852 cv_signal(&ac->ac_cv);
853 mutex_exit(&ac->ac_mutex);
854 }
855 mutex_spin_enter(&amr->amr_mutex);
856 }
857 forus = 1;
858 }
859
860 mutex_spin_exit(&amr->amr_mutex);
861
862 if (forus)
863 amr_ccb_enqueue(amr, NULL);
864
865 return (forus);
866 }
867
868 /*
869 * Watchdog thread.
870 */
871 static void
amr_quartz_thread(void * cookie)872 amr_quartz_thread(void *cookie)
873 {
874 struct amr_softc *amr;
875 struct amr_ccb *ac;
876
877 amr = cookie;
878
879 for (;;) {
880 mutex_enter(&thread_mutex);
881 cv_timedwait(&thread_cv, &thread_mutex, AMR_WDOG_TICKS);
882 mutex_exit(&thread_mutex);
883
884 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) {
885 amr->amr_flags ^= AMRF_THREAD_EXIT;
886 mutex_enter(&thread_mutex);
887 cv_signal(&thread_cv);
888 mutex_exit(&thread_mutex);
889 kthread_exit(0);
890 }
891
892 if (amr_intr(amr) == 0)
893 amr_ccb_enqueue(amr, NULL);
894
895 mutex_spin_enter(&amr->amr_mutex);
896 ac = TAILQ_FIRST(&amr->amr_ccb_active);
897 while (ac != NULL) {
898 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime)
899 break;
900 if ((ac->ac_flags & AC_MOAN) == 0) {
901 printf("%s: ccb %d timed out; mailbox:\n",
902 device_xname(amr->amr_dv), ac->ac_ident);
903 amr_ccb_dump(amr, ac);
904 ac->ac_flags |= AC_MOAN;
905 }
906 ac = TAILQ_NEXT(ac, ac_chain.tailq);
907 }
908 mutex_spin_exit(&amr->amr_mutex);
909 }
910 }
911
912 static void
amr_std_thread(void * cookie)913 amr_std_thread(void *cookie)
914 {
915 struct amr_softc *amr;
916 struct amr_ccb *ac;
917 struct amr_logdrive *al;
918 struct amr_enquiry *ae;
919 int rv, i;
920
921 amr = cookie;
922 ae = amr->amr_enqbuf;
923
924 for (;;) {
925 mutex_enter(&thread_mutex);
926 cv_timedwait(&thread_cv, &thread_mutex, AMR_WDOG_TICKS);
927 mutex_exit(&thread_mutex);
928
929 if ((amr->amr_flags & AMRF_THREAD_EXIT) != 0) {
930 amr->amr_flags ^= AMRF_THREAD_EXIT;
931 mutex_enter(&thread_mutex);
932 cv_signal(&thread_cv);
933 mutex_exit(&thread_mutex);
934 kthread_exit(0);
935 }
936
937 if (amr_intr(amr) == 0)
938 amr_ccb_enqueue(amr, NULL);
939
940 mutex_spin_enter(&amr->amr_mutex);
941 ac = TAILQ_FIRST(&amr->amr_ccb_active);
942 while (ac != NULL) {
943 if (ac->ac_start_time + AMR_TIMEOUT > time_uptime)
944 break;
945 if ((ac->ac_flags & AC_MOAN) == 0) {
946 printf("%s: ccb %d timed out; mailbox:\n",
947 device_xname(amr->amr_dv), ac->ac_ident);
948 amr_ccb_dump(amr, ac);
949 ac->ac_flags |= AC_MOAN;
950 }
951 ac = TAILQ_NEXT(ac, ac_chain.tailq);
952 }
953 mutex_spin_exit(&amr->amr_mutex);
954
955 if ((rv = amr_ccb_alloc(amr, &ac)) != 0) {
956 printf("%s: ccb_alloc failed (%d)\n",
957 device_xname(amr->amr_dv), rv);
958 continue;
959 }
960
961 ac->ac_cmd.mb_command = AMR_CMD_ENQUIRY;
962
963 rv = amr_ccb_map(amr, ac, amr->amr_enqbuf,
964 AMR_ENQUIRY_BUFSIZE, AC_XFER_IN);
965 if (rv != 0) {
966 aprint_error_dev(amr->amr_dv, "ccb_map failed (%d)\n",
967 rv);
968 amr_ccb_free(amr, ac);
969 continue;
970 }
971
972 rv = amr_ccb_wait(amr, ac);
973 amr_ccb_unmap(amr, ac);
974 if (rv != 0) {
975 aprint_error_dev(amr->amr_dv,
976 "enquiry failed (st=%d)\n", ac->ac_status);
977 continue;
978 }
979 amr_ccb_free(amr, ac);
980
981 al = amr->amr_drive;
982 for (i = 0; i < __arraycount(ae->ae_ldrv.al_state); i++, al++) {
983 if (al->al_dv == NULL)
984 continue;
985 if (al->al_state == ae->ae_ldrv.al_state[i])
986 continue;
987
988 printf("%s: state changed: %s -> %s\n",
989 device_xname(al->al_dv),
990 amr_drive_state(al->al_state, NULL),
991 amr_drive_state(ae->ae_ldrv.al_state[i], NULL));
992
993 al->al_state = ae->ae_ldrv.al_state[i];
994 }
995 }
996 }
997
998 /*
999 * Return a text description of a logical drive's current state.
1000 */
1001 const char *
amr_drive_state(int state,int * happy)1002 amr_drive_state(int state, int *happy)
1003 {
1004 const char *str;
1005
1006 state = AMR_DRV_CURSTATE(state);
1007 if (state >= sizeof(amr_dstate) / sizeof(amr_dstate[0])) {
1008 if (happy)
1009 *happy = 1;
1010 str = "status unknown";
1011 } else {
1012 if (happy)
1013 *happy = amr_dstate[state].ds_happy;
1014 str = amr_dstate[state].ds_descr;
1015 }
1016
1017 return (str);
1018 }
1019
1020 /*
1021 * Run a generic enquiry-style command.
1022 */
1023 static void *
amr_enquire(struct amr_softc * amr,u_int8_t cmd,u_int8_t cmdsub,u_int8_t cmdqual,void * sbuf)1024 amr_enquire(struct amr_softc *amr, u_int8_t cmd, u_int8_t cmdsub,
1025 u_int8_t cmdqual, void *sbuf)
1026 {
1027 struct amr_ccb *ac;
1028 u_int8_t *mb;
1029 int rv;
1030
1031 if (amr_ccb_alloc(amr, &ac) != 0)
1032 return (NULL);
1033
1034 /* Build the command proper. */
1035 mb = (u_int8_t *)&ac->ac_cmd;
1036 mb[0] = cmd;
1037 mb[2] = cmdsub;
1038 mb[3] = cmdqual;
1039
1040 rv = amr_ccb_map(amr, ac, sbuf, AMR_ENQUIRY_BUFSIZE, AC_XFER_IN);
1041 if (rv == 0) {
1042 rv = amr_ccb_poll(amr, ac, 2000);
1043 amr_ccb_unmap(amr, ac);
1044 }
1045 amr_ccb_free(amr, ac);
1046
1047 return (rv ? NULL : sbuf);
1048 }
1049
1050 /*
1051 * Allocate and initialise a CCB.
1052 */
1053 int
amr_ccb_alloc(struct amr_softc * amr,struct amr_ccb ** acp)1054 amr_ccb_alloc(struct amr_softc *amr, struct amr_ccb **acp)
1055 {
1056 mutex_spin_enter(&amr->amr_mutex);
1057 if ((*acp = SLIST_FIRST(&amr->amr_ccb_freelist)) == NULL) {
1058 mutex_spin_exit(&amr->amr_mutex);
1059 return (EAGAIN);
1060 }
1061 SLIST_REMOVE_HEAD(&amr->amr_ccb_freelist, ac_chain.slist);
1062 mutex_spin_exit(&amr->amr_mutex);
1063
1064 return (0);
1065 }
1066
1067 /*
1068 * Free a CCB.
1069 */
1070 void
amr_ccb_free(struct amr_softc * amr,struct amr_ccb * ac)1071 amr_ccb_free(struct amr_softc *amr, struct amr_ccb *ac)
1072 {
1073 memset(&ac->ac_cmd, 0, sizeof(ac->ac_cmd));
1074 ac->ac_cmd.mb_ident = ac->ac_ident + 1;
1075 ac->ac_cmd.mb_busy = 1;
1076 ac->ac_handler = NULL;
1077 ac->ac_flags = 0;
1078
1079 mutex_spin_enter(&amr->amr_mutex);
1080 SLIST_INSERT_HEAD(&amr->amr_ccb_freelist, ac, ac_chain.slist);
1081 mutex_spin_exit(&amr->amr_mutex);
1082 }
1083
1084 /*
1085 * If a CCB is specified, enqueue it. Pull CCBs off the software queue in
1086 * the order that they were enqueued and try to submit their command blocks
1087 * to the controller for execution.
1088 */
1089 void
amr_ccb_enqueue(struct amr_softc * amr,struct amr_ccb * ac)1090 amr_ccb_enqueue(struct amr_softc *amr, struct amr_ccb *ac)
1091 {
1092 if (ac != NULL) {
1093 mutex_spin_enter(&amr->amr_mutex);
1094 SIMPLEQ_INSERT_TAIL(&amr->amr_ccb_queue, ac, ac_chain.simpleq);
1095 mutex_spin_exit(&amr->amr_mutex);
1096 }
1097
1098 while (SIMPLEQ_FIRST(&amr->amr_ccb_queue) != NULL) {
1099 mutex_spin_enter(&amr->amr_mutex);
1100 if ((ac = SIMPLEQ_FIRST(&amr->amr_ccb_queue)) != NULL) {
1101 if ((*amr->amr_submit)(amr, ac) != 0) {
1102 mutex_spin_exit(&amr->amr_mutex);
1103 break;
1104 }
1105 SIMPLEQ_REMOVE_HEAD(&amr->amr_ccb_queue,
1106 ac_chain.simpleq);
1107 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac,
1108 ac_chain.tailq);
1109 }
1110 mutex_spin_exit(&amr->amr_mutex);
1111 }
1112 }
1113
1114 /*
1115 * Map the specified CCB's data buffer onto the bus, and fill the
1116 * scatter-gather list.
1117 */
1118 int
amr_ccb_map(struct amr_softc * amr,struct amr_ccb * ac,void * data,int size,int tflag)1119 amr_ccb_map(struct amr_softc *amr, struct amr_ccb *ac, void *data, int size,
1120 int tflag)
1121 {
1122 struct amr_sgentry *sge;
1123 struct amr_mailbox_cmd *mb;
1124 int nsegs, i, rv, sgloff;
1125 bus_dmamap_t xfer;
1126 int dmaflag = 0;
1127
1128 xfer = ac->ac_xfer_map;
1129
1130 rv = bus_dmamap_load(amr->amr_dmat, xfer, data, size, NULL,
1131 BUS_DMA_NOWAIT);
1132 if (rv != 0)
1133 return (rv);
1134
1135 mb = &ac->ac_cmd;
1136 ac->ac_xfer_size = size;
1137 ac->ac_flags |= (tflag & (AC_XFER_OUT | AC_XFER_IN));
1138 sgloff = AMR_SGL_SIZE * ac->ac_ident;
1139
1140 if (tflag & AC_XFER_OUT)
1141 dmaflag |= BUS_DMASYNC_PREWRITE;
1142 if (tflag & AC_XFER_IN)
1143 dmaflag |= BUS_DMASYNC_PREREAD;
1144
1145 /* We don't need to use a scatter/gather list for just 1 segment. */
1146 nsegs = xfer->dm_nsegs;
1147 if (nsegs == 1) {
1148 mb->mb_nsgelem = 0;
1149 mb->mb_physaddr = htole32(xfer->dm_segs[0].ds_addr);
1150 ac->ac_flags |= AC_NOSGL;
1151 } else {
1152 mb->mb_nsgelem = nsegs;
1153 mb->mb_physaddr = htole32(amr->amr_sgls_paddr + sgloff);
1154
1155 sge = (struct amr_sgentry *)((char *)amr->amr_sgls + sgloff);
1156 for (i = 0; i < nsegs; i++, sge++) {
1157 sge->sge_addr = htole32(xfer->dm_segs[i].ds_addr);
1158 sge->sge_count = htole32(xfer->dm_segs[i].ds_len);
1159 }
1160 }
1161
1162 bus_dmamap_sync(amr->amr_dmat, xfer, 0, ac->ac_xfer_size, dmaflag);
1163
1164 if ((ac->ac_flags & AC_NOSGL) == 0)
1165 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, sgloff,
1166 AMR_SGL_SIZE, BUS_DMASYNC_PREWRITE);
1167
1168 return (0);
1169 }
1170
1171 /*
1172 * Unmap the specified CCB's data buffer.
1173 */
1174 void
amr_ccb_unmap(struct amr_softc * amr,struct amr_ccb * ac)1175 amr_ccb_unmap(struct amr_softc *amr, struct amr_ccb *ac)
1176 {
1177 int dmaflag = 0;
1178
1179 if (ac->ac_flags & AC_XFER_IN)
1180 dmaflag |= BUS_DMASYNC_POSTREAD;
1181 if (ac->ac_flags & AC_XFER_OUT)
1182 dmaflag |= BUS_DMASYNC_POSTWRITE;
1183
1184 if ((ac->ac_flags & AC_NOSGL) == 0)
1185 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap,
1186 AMR_SGL_SIZE * ac->ac_ident, AMR_SGL_SIZE,
1187 BUS_DMASYNC_POSTWRITE);
1188 bus_dmamap_sync(amr->amr_dmat, ac->ac_xfer_map, 0, ac->ac_xfer_size,
1189 dmaflag);
1190 bus_dmamap_unload(amr->amr_dmat, ac->ac_xfer_map);
1191 }
1192
1193 /*
1194 * Submit a command to the controller and poll on completion. Return
1195 * non-zero on timeout or error.
1196 */
1197 int
amr_ccb_poll(struct amr_softc * amr,struct amr_ccb * ac,int timo)1198 amr_ccb_poll(struct amr_softc *amr, struct amr_ccb *ac, int timo)
1199 {
1200 int rv, i;
1201
1202 mutex_spin_enter(&amr->amr_mutex);
1203 if ((rv = (*amr->amr_submit)(amr, ac)) != 0) {
1204 mutex_spin_exit(&amr->amr_mutex);
1205 return (rv);
1206 }
1207 TAILQ_INSERT_TAIL(&amr->amr_ccb_active, ac, ac_chain.tailq);
1208 mutex_spin_exit(&amr->amr_mutex);
1209
1210 for (i = timo * 10; i > 0; i--) {
1211 amr_intr(amr);
1212 if ((ac->ac_flags & AC_COMPLETE) != 0)
1213 break;
1214 DELAY(100);
1215 }
1216
1217 if (i == 0)
1218 printf("%s: polled operation timed out after %d ms\n",
1219 device_xname(amr->amr_dv), timo);
1220
1221 return ((i == 0 || ac->ac_status != 0) ? EIO : 0);
1222 }
1223
1224 /*
1225 * Submit a command to the controller and sleep on completion. Return
1226 * non-zero on error.
1227 */
1228 int
amr_ccb_wait(struct amr_softc * amr,struct amr_ccb * ac)1229 amr_ccb_wait(struct amr_softc *amr, struct amr_ccb *ac)
1230 {
1231 amr_ccb_enqueue(amr, ac);
1232 mutex_enter(&ac->ac_mutex);
1233 cv_wait(&ac->ac_cv, &ac->ac_mutex);
1234 mutex_exit(&ac->ac_mutex);
1235
1236 return (ac->ac_status != 0 ? EIO : 0);
1237 }
1238
1239 #if 0
1240 /*
1241 * Wait for the mailbox to become available.
1242 */
1243 static int
1244 amr_mbox_wait(struct amr_softc *amr)
1245 {
1246 int timo;
1247
1248 for (timo = 10000; timo != 0; timo--) {
1249 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1250 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD);
1251 if (amr->amr_mbox->mb_cmd.mb_busy == 0)
1252 break;
1253 DELAY(100);
1254 }
1255
1256 if (timo == 0)
1257 printf("%s: controller wedged\n", device_xname(amr->amr_dv));
1258
1259 return (timo != 0 ? 0 : EAGAIN);
1260 }
1261 #endif
1262
1263 /*
1264 * Tell the controller that the mailbox contains a valid command. Must be
1265 * called with interrupts blocked.
1266 */
1267 static int
amr_quartz_submit(struct amr_softc * amr,struct amr_ccb * ac)1268 amr_quartz_submit(struct amr_softc *amr, struct amr_ccb *ac)
1269 {
1270 int i = 0;
1271 u_int32_t v;
1272
1273 amr->amr_mbox->mb_poll = 0;
1274 amr->amr_mbox->mb_ack = 0;
1275
1276 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1277 sizeof(struct amr_mailbox),
1278 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1279
1280 v = amr_inl(amr, AMR_QREG_ODB);
1281 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1282 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD);
1283 while ((amr->amr_mbox->mb_cmd.mb_busy != 0) && (i++ < 10)) {
1284 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1285 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD);
1286 /* This is a no-op read that flushes pending mailbox updates */
1287 v = amr_inl(amr, AMR_QREG_ODB);
1288 DELAY(1);
1289 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1290 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD);
1291 }
1292
1293 if (amr->amr_mbox->mb_cmd.mb_busy != 0)
1294 return (EAGAIN);
1295
1296 v = amr_inl(amr, AMR_QREG_IDB);
1297 if ((v & AMR_QIDB_SUBMIT) != 0) {
1298 amr->amr_mbox->mb_cmd.mb_busy = 0;
1299 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1300 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE);
1301 printf("%s: submit failed\n", device_xname(amr->amr_dv));
1302 return (EAGAIN);
1303 }
1304
1305 amr->amr_mbox->mb_segment = 0;
1306 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd));
1307 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1308 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE);
1309
1310 ac->ac_start_time = time_uptime;
1311 ac->ac_flags |= AC_ACTIVE;
1312
1313 amr_outl(amr, AMR_QREG_IDB,
1314 (amr->amr_mbox_paddr + 16) | AMR_QIDB_SUBMIT);
1315 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1316 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTWRITE);
1317
1318 return (0);
1319 }
1320
1321 static int
amr_std_submit(struct amr_softc * amr,struct amr_ccb * ac)1322 amr_std_submit(struct amr_softc *amr, struct amr_ccb *ac)
1323 {
1324
1325 amr->amr_mbox->mb_poll = 0;
1326 amr->amr_mbox->mb_ack = 0;
1327
1328 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1329 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD);
1330
1331 if (amr->amr_mbox->mb_cmd.mb_busy != 0)
1332 return (EAGAIN);
1333
1334 if ((amr_inb(amr, AMR_SREG_MBOX_BUSY) & AMR_SMBOX_BUSY_FLAG) != 0) {
1335 amr->amr_mbox->mb_cmd.mb_busy = 0;
1336 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1337 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE);
1338 return (EAGAIN);
1339 }
1340
1341 amr->amr_mbox->mb_segment = 0;
1342 memcpy(&amr->amr_mbox->mb_cmd, &ac->ac_cmd, sizeof(ac->ac_cmd));
1343
1344 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1345 sizeof(struct amr_mailbox), BUS_DMASYNC_PREWRITE);
1346
1347 ac->ac_start_time = time_uptime;
1348 ac->ac_flags |= AC_ACTIVE;
1349 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_POST);
1350
1351 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1352 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTWRITE);
1353
1354 return (0);
1355 }
1356
1357 /*
1358 * Claim any work that the controller has completed; acknowledge completion,
1359 * save details of the completion in (mbsave). Must be called with
1360 * interrupts blocked.
1361 */
1362 static int
amr_quartz_get_work(struct amr_softc * amr,struct amr_mailbox_resp * mbsave)1363 amr_quartz_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave)
1364 {
1365 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1366 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD);
1367
1368 /* Work waiting for us? */
1369 if (amr_inl(amr, AMR_QREG_ODB) != AMR_QODB_READY)
1370 return (-1);
1371
1372 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1373 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD);
1374
1375 /* Save the mailbox, which contains a list of completed commands. */
1376 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave));
1377
1378 /* Ack the interrupt and mailbox transfer. */
1379 amr_outl(amr, AMR_QREG_ODB, AMR_QODB_READY);
1380 amr_outl(amr, AMR_QREG_IDB, (amr->amr_mbox_paddr+16) | AMR_QIDB_ACK);
1381
1382 /*
1383 * This waits for the controller to notice that we've taken the
1384 * command from it. It's very inefficient, and we shouldn't do it,
1385 * but if we remove this code, we stop completing commands under
1386 * load.
1387 *
1388 * Peter J says we shouldn't do this. The documentation says we
1389 * should. Who is right?
1390 */
1391 while ((amr_inl(amr, AMR_QREG_IDB) & AMR_QIDB_ACK) != 0)
1392 DELAY(10);
1393
1394 return (0);
1395 }
1396
1397 static int
amr_std_get_work(struct amr_softc * amr,struct amr_mailbox_resp * mbsave)1398 amr_std_get_work(struct amr_softc *amr, struct amr_mailbox_resp *mbsave)
1399 {
1400 u_int8_t istat;
1401
1402 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1403 sizeof(struct amr_mailbox), BUS_DMASYNC_PREREAD);
1404
1405 /* Check for valid interrupt status. */
1406 if (((istat = amr_inb(amr, AMR_SREG_INTR)) & AMR_SINTR_VALID) == 0)
1407 return (-1);
1408
1409 /* Ack the interrupt. */
1410 amr_outb(amr, AMR_SREG_INTR, istat);
1411
1412 bus_dmamap_sync(amr->amr_dmat, amr->amr_dmamap, 0,
1413 sizeof(struct amr_mailbox), BUS_DMASYNC_POSTREAD);
1414
1415 /* Save mailbox, which contains a list of completed commands. */
1416 memcpy(mbsave, &amr->amr_mbox->mb_resp, sizeof(*mbsave));
1417
1418 /* Ack mailbox transfer. */
1419 amr_outb(amr, AMR_SREG_CMD, AMR_SCMD_ACKINTR);
1420
1421 return (0);
1422 }
1423
1424 static void
amr_ccb_dump(struct amr_softc * amr,struct amr_ccb * ac)1425 amr_ccb_dump(struct amr_softc *amr, struct amr_ccb *ac)
1426 {
1427 int i;
1428
1429 printf("%s: ", device_xname(amr->amr_dv));
1430 for (i = 0; i < 4; i++)
1431 printf("%08x ", ((u_int32_t *)&ac->ac_cmd)[i]);
1432 printf("\n");
1433 }
1434
1435 static int
amropen(dev_t dev,int flag,int mode,struct lwp * l)1436 amropen(dev_t dev, int flag, int mode, struct lwp *l)
1437 {
1438 struct amr_softc *amr;
1439
1440 if ((amr = device_lookup_private(&amr_cd, minor(dev))) == NULL)
1441 return (ENXIO);
1442 if ((amr->amr_flags & AMRF_OPEN) != 0)
1443 return (EBUSY);
1444
1445 amr->amr_flags |= AMRF_OPEN;
1446 return (0);
1447 }
1448
1449 static int
amrclose(dev_t dev,int flag,int mode,struct lwp * l)1450 amrclose(dev_t dev, int flag, int mode, struct lwp *l)
1451 {
1452 struct amr_softc *amr;
1453
1454 amr = device_lookup_private(&amr_cd, minor(dev));
1455 amr->amr_flags &= ~AMRF_OPEN;
1456 return (0);
1457 }
1458
1459 /* used below to correct for a firmware bug */
1460 static unsigned long
amrioctl_buflen(unsigned long len)1461 amrioctl_buflen(unsigned long len)
1462 {
1463 if (len <= 4 * 1024)
1464 return (4 * 1024);
1465 if (len <= 8 * 1024)
1466 return (8 * 1024);
1467 if (len <= 32 * 1024)
1468 return (32 * 1024);
1469 if (len <= 64 * 1024)
1470 return (64 * 1024);
1471 return (len);
1472 }
1473
1474 static int
amrioctl(dev_t dev,u_long cmd,void * data,int flag,struct lwp * l)1475 amrioctl(dev_t dev, u_long cmd, void *data, int flag,
1476 struct lwp *l)
1477 {
1478 struct amr_softc *amr;
1479 struct amr_user_ioctl *au;
1480 struct amr_ccb *ac;
1481 struct amr_mailbox_ioctl *mbi;
1482 unsigned long au_length;
1483 uint8_t *au_cmd;
1484 int error;
1485 void *dp = NULL, *au_buffer;
1486
1487 amr = device_lookup_private(&amr_cd, minor(dev));
1488
1489 /* This should be compatible with the FreeBSD interface */
1490
1491 switch (cmd) {
1492 case AMR_IO_VERSION:
1493 *(int *)data = AMR_IO_VERSION_NUMBER;
1494 return 0;
1495 case AMR_IO_COMMAND:
1496 error = kauth_authorize_device_passthru(l->l_cred, dev,
1497 KAUTH_REQ_DEVICE_RAWIO_PASSTHRU_ALL, data);
1498 if (error)
1499 return (error);
1500
1501 au = (struct amr_user_ioctl *)data;
1502 au_cmd = au->au_cmd;
1503 au_buffer = au->au_buffer;
1504 au_length = au->au_length;
1505 break;
1506 default:
1507 return ENOTTY;
1508 }
1509
1510 if (au_cmd[0] == AMR_CMD_PASS) {
1511 /* not yet */
1512 return EOPNOTSUPP;
1513 }
1514
1515 if (au_length <= 0 || au_length > MAXPHYS || au_cmd[0] == 0x06)
1516 return (EINVAL);
1517
1518 /*
1519 * allocate kernel memory for data, doing I/O directly to user
1520 * buffer isn't that easy. Correct allocation size for a bug
1521 * in at least some versions of the device firmware, by using
1522 * the amrioctl_buflen() function, defined above.
1523 */
1524 dp = malloc(amrioctl_buflen(au_length), M_DEVBUF, M_WAITOK|M_ZERO);
1525 if (dp == NULL)
1526 return ENOMEM;
1527 if ((error = copyin(au_buffer, dp, au_length)) != 0)
1528 goto out;
1529
1530 /* direct command to controller */
1531 while (amr_ccb_alloc(amr, &ac) != 0) {
1532 mutex_enter(&thread_mutex);
1533 error = cv_timedwait_sig(&thread_cv, &thread_mutex, hz);
1534 mutex_exit(&thread_mutex);
1535 if (error == EINTR)
1536 goto out;
1537 }
1538
1539 mbi = (struct amr_mailbox_ioctl *)&ac->ac_cmd;
1540 mbi->mb_command = au_cmd[0];
1541 mbi->mb_channel = au_cmd[1];
1542 mbi->mb_param = au_cmd[2];
1543 mbi->mb_pad[0] = au_cmd[3];
1544 mbi->mb_drive = au_cmd[4];
1545 error = amr_ccb_map(amr, ac, dp, (int)au_length,
1546 AC_XFER_IN | AC_XFER_OUT);
1547 if (error == 0) {
1548 error = amr_ccb_wait(amr, ac);
1549 amr_ccb_unmap(amr, ac);
1550 if (error == 0)
1551 error = copyout(dp, au_buffer, au_length);
1552
1553 }
1554 amr_ccb_free(amr, ac);
1555 out:
1556 free(dp, M_DEVBUF);
1557 return (error);
1558 }
1559
1560 MODULE(MODULE_CLASS_DRIVER, amr, "pci");
1561
1562 #ifdef _MODULE
1563 #include "ioconf.c"
1564 #endif
1565
1566 static int
amr_modcmd(modcmd_t cmd,void * opaque)1567 amr_modcmd(modcmd_t cmd, void *opaque)
1568 {
1569 int error = 0;
1570
1571 #ifdef _MODULE
1572 switch (cmd) {
1573 case MODULE_CMD_INIT:
1574 error = config_init_component(cfdriver_ioconf_amr,
1575 cfattach_ioconf_amr, cfdata_ioconf_amr);
1576 break;
1577 case MODULE_CMD_FINI:
1578 error = config_fini_component(cfdriver_ioconf_amr,
1579 cfattach_ioconf_amr, cfdata_ioconf_amr);
1580 break;
1581 default:
1582 error = ENOTTY;
1583 break;
1584 }
1585 #endif
1586
1587 return error;
1588 }
1589