1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2014 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "amdgpu_amdkfd.h" 25 #include "amd_pcie.h" 26 #include "amd_shared.h" 27 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_dma_buf.h" 31 #include <linux/module.h> 32 #include <linux/dma-buf.h> 33 #include "amdgpu_xgmi.h" 34 #include <uapi/linux/kfd_ioctl.h> 35 #include "amdgpu_ras.h" 36 #include "amdgpu_umc.h" 37 #include "amdgpu_reset.h" 38 39 /* Total memory size in system memory and all GPU VRAM. Used to 40 * estimate worst case amount of memory to reserve for page tables 41 */ 42 uint64_t amdgpu_amdkfd_total_mem_size; 43 44 static bool kfd_initialized; 45 46 int amdgpu_amdkfd_init(void) 47 { 48 #ifdef __linux__ 49 struct sysinfo si; 50 int ret; 51 52 si_meminfo(&si); 53 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; 54 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 55 #else 56 int ret; 57 58 amdgpu_amdkfd_total_mem_size = ptoa(physmem); 59 #endif 60 ret = kgd2kfd_init(); 61 kfd_initialized = !ret; 62 63 return ret; 64 } 65 66 void amdgpu_amdkfd_fini(void) 67 { 68 if (kfd_initialized) { 69 kgd2kfd_exit(); 70 kfd_initialized = false; 71 } 72 } 73 74 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 75 { 76 bool vf = amdgpu_sriov_vf(adev); 77 78 if (!kfd_initialized) 79 return; 80 81 adev->kfd.dev = kgd2kfd_probe(adev, vf); 82 } 83 84 /** 85 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 86 * setup amdkfd 87 * 88 * @adev: amdgpu_device pointer 89 * @aperture_base: output returning doorbell aperture base physical address 90 * @aperture_size: output returning doorbell aperture size in bytes 91 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 92 * 93 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 94 * takes doorbells required for its own rings and reports the setup to amdkfd. 95 * amdgpu reserved doorbells are at the start of the doorbell aperture. 96 */ 97 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 98 phys_addr_t *aperture_base, 99 size_t *aperture_size, 100 size_t *start_offset) 101 { 102 /* 103 * The first num_kernel_doorbells are used by amdgpu. 104 * amdkfd takes whatever's left in the aperture. 105 */ 106 if (adev->enable_mes) { 107 /* 108 * With MES enabled, we only need to initialize 109 * the base address. The size and offset are 110 * not initialized as AMDGPU manages the whole 111 * doorbell space. 112 */ 113 *aperture_base = adev->doorbell.base; 114 *aperture_size = 0; 115 *start_offset = 0; 116 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells * 117 sizeof(u32)) { 118 *aperture_base = adev->doorbell.base; 119 *aperture_size = adev->doorbell.size; 120 *start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32); 121 } else { 122 *aperture_base = 0; 123 *aperture_size = 0; 124 *start_offset = 0; 125 } 126 } 127 128 129 static void amdgpu_amdkfd_reset_work(struct work_struct *work) 130 { 131 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 132 kfd.reset_work); 133 134 struct amdgpu_reset_context reset_context; 135 136 memset(&reset_context, 0, sizeof(reset_context)); 137 138 reset_context.method = AMD_RESET_METHOD_NONE; 139 reset_context.reset_req_dev = adev; 140 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 141 142 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 143 } 144 145 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 146 { 147 int i; 148 int last_valid_bit; 149 150 amdgpu_amdkfd_gpuvm_init_mem_limits(); 151 152 if (adev->kfd.dev) { 153 struct kgd2kfd_shared_resources gpu_resources = { 154 .compute_vmid_bitmap = 155 ((1 << AMDGPU_NUM_VMID) - 1) - 156 ((1 << adev->vm_manager.first_kfd_vmid) - 1), 157 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 158 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 159 .gpuvm_size = min(adev->vm_manager.max_pfn 160 << AMDGPU_GPU_PAGE_SHIFT, 161 AMDGPU_GMC_HOLE_START), 162 .drm_render_minor = adev_to_drm(adev)->render->index, 163 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 164 .enable_mes = adev->enable_mes, 165 }; 166 167 /* this is going to have a few of the MSBs set that we need to 168 * clear 169 */ 170 bitmap_complement(gpu_resources.cp_queue_bitmap, 171 adev->gfx.mec_bitmap[0].queue_bitmap, 172 KGD_MAX_QUEUES); 173 174 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 175 * nbits is not compile time constant 176 */ 177 last_valid_bit = 1 /* only first MEC can have compute queues */ 178 * adev->gfx.mec.num_pipe_per_mec 179 * adev->gfx.mec.num_queue_per_pipe; 180 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i) 181 clear_bit(i, gpu_resources.cp_queue_bitmap); 182 183 amdgpu_doorbell_get_kfd_info(adev, 184 &gpu_resources.doorbell_physical_address, 185 &gpu_resources.doorbell_aperture_size, 186 &gpu_resources.doorbell_start_offset); 187 188 /* Since SOC15, BIF starts to statically use the 189 * lower 12 bits of doorbell addresses for routing 190 * based on settings in registers like 191 * SDMA0_DOORBELL_RANGE etc.. 192 * In order to route a doorbell to CP engine, the lower 193 * 12 bits of its address has to be outside the range 194 * set for SDMA, VCN, and IH blocks. 195 */ 196 if (adev->asic_type >= CHIP_VEGA10) { 197 gpu_resources.non_cp_doorbells_start = 198 adev->doorbell_index.first_non_cp; 199 gpu_resources.non_cp_doorbells_end = 200 adev->doorbell_index.last_non_cp; 201 } 202 203 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, 204 &gpu_resources); 205 206 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 207 208 INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work); 209 } 210 } 211 212 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev) 213 { 214 if (adev->kfd.dev) { 215 kgd2kfd_device_exit(adev->kfd.dev); 216 adev->kfd.dev = NULL; 217 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size; 218 } 219 } 220 221 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 222 const void *ih_ring_entry) 223 { 224 if (adev->kfd.dev) 225 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 226 } 227 228 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm) 229 { 230 if (adev->kfd.dev) 231 kgd2kfd_suspend(adev->kfd.dev, run_pm); 232 } 233 234 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm) 235 { 236 int r = 0; 237 238 if (adev->kfd.dev) 239 r = kgd2kfd_resume(adev->kfd.dev, run_pm); 240 241 return r; 242 } 243 244 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev) 245 { 246 int r = 0; 247 248 if (adev->kfd.dev) 249 r = kgd2kfd_pre_reset(adev->kfd.dev); 250 251 return r; 252 } 253 254 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 255 { 256 int r = 0; 257 258 if (adev->kfd.dev) 259 r = kgd2kfd_post_reset(adev->kfd.dev); 260 261 return r; 262 } 263 264 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) 265 { 266 if (amdgpu_device_should_recover_gpu(adev)) 267 amdgpu_reset_domain_schedule(adev->reset_domain, 268 &adev->kfd.reset_work); 269 } 270 271 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, 272 void **mem_obj, uint64_t *gpu_addr, 273 void **cpu_ptr, bool cp_mqd_gfx9) 274 { 275 struct amdgpu_bo *bo = NULL; 276 struct amdgpu_bo_param bp; 277 int r; 278 void *cpu_ptr_tmp = NULL; 279 280 memset(&bp, 0, sizeof(bp)); 281 bp.size = size; 282 bp.byte_align = PAGE_SIZE; 283 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 284 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 285 bp.type = ttm_bo_type_kernel; 286 bp.resv = NULL; 287 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 288 289 if (cp_mqd_gfx9) 290 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9; 291 292 r = amdgpu_bo_create(adev, &bp, &bo); 293 if (r) { 294 dev_err(adev->dev, 295 "failed to allocate BO for amdkfd (%d)\n", r); 296 return r; 297 } 298 299 /* map the buffer */ 300 r = amdgpu_bo_reserve(bo, true); 301 if (r) { 302 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 303 goto allocate_mem_reserve_bo_failed; 304 } 305 306 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 307 if (r) { 308 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 309 goto allocate_mem_pin_bo_failed; 310 } 311 312 r = amdgpu_ttm_alloc_gart(&bo->tbo); 313 if (r) { 314 dev_err(adev->dev, "%p bind failed\n", bo); 315 goto allocate_mem_kmap_bo_failed; 316 } 317 318 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 319 if (r) { 320 dev_err(adev->dev, 321 "(%d) failed to map bo to kernel for amdkfd\n", r); 322 goto allocate_mem_kmap_bo_failed; 323 } 324 325 *mem_obj = bo; 326 *gpu_addr = amdgpu_bo_gpu_offset(bo); 327 *cpu_ptr = cpu_ptr_tmp; 328 329 amdgpu_bo_unreserve(bo); 330 331 return 0; 332 333 allocate_mem_kmap_bo_failed: 334 amdgpu_bo_unpin(bo); 335 allocate_mem_pin_bo_failed: 336 amdgpu_bo_unreserve(bo); 337 allocate_mem_reserve_bo_failed: 338 amdgpu_bo_unref(&bo); 339 340 return r; 341 } 342 343 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj) 344 { 345 struct amdgpu_bo **bo = (struct amdgpu_bo **) mem_obj; 346 347 amdgpu_bo_reserve(*bo, true); 348 amdgpu_bo_kunmap(*bo); 349 amdgpu_bo_unpin(*bo); 350 amdgpu_bo_unreserve(*bo); 351 amdgpu_bo_unref(bo); 352 } 353 354 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 355 void **mem_obj) 356 { 357 struct amdgpu_bo *bo = NULL; 358 struct amdgpu_bo_user *ubo; 359 struct amdgpu_bo_param bp; 360 int r; 361 362 memset(&bp, 0, sizeof(bp)); 363 bp.size = size; 364 bp.byte_align = 1; 365 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 366 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 367 bp.type = ttm_bo_type_device; 368 bp.resv = NULL; 369 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 370 371 r = amdgpu_bo_create_user(adev, &bp, &ubo); 372 if (r) { 373 dev_err(adev->dev, 374 "failed to allocate gws BO for amdkfd (%d)\n", r); 375 return r; 376 } 377 378 bo = &ubo->bo; 379 *mem_obj = bo; 380 return 0; 381 } 382 383 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj) 384 { 385 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 386 387 amdgpu_bo_unref(&bo); 388 } 389 390 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 391 enum kgd_engine_type type) 392 { 393 switch (type) { 394 case KGD_ENGINE_PFP: 395 return adev->gfx.pfp_fw_version; 396 397 case KGD_ENGINE_ME: 398 return adev->gfx.me_fw_version; 399 400 case KGD_ENGINE_CE: 401 return adev->gfx.ce_fw_version; 402 403 case KGD_ENGINE_MEC1: 404 return adev->gfx.mec_fw_version; 405 406 case KGD_ENGINE_MEC2: 407 return adev->gfx.mec2_fw_version; 408 409 case KGD_ENGINE_RLC: 410 return adev->gfx.rlc_fw_version; 411 412 case KGD_ENGINE_SDMA1: 413 return adev->sdma.instance[0].fw_version; 414 415 case KGD_ENGINE_SDMA2: 416 return adev->sdma.instance[1].fw_version; 417 418 default: 419 return 0; 420 } 421 422 return 0; 423 } 424 425 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 426 struct kfd_local_mem_info *mem_info, 427 struct amdgpu_xcp *xcp) 428 { 429 memset(mem_info, 0, sizeof(*mem_info)); 430 431 if (xcp) { 432 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size) 433 mem_info->local_mem_size_public = 434 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 435 else 436 mem_info->local_mem_size_private = 437 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 438 } else { 439 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 440 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 441 adev->gmc.visible_vram_size; 442 } 443 mem_info->vram_width = adev->gmc.vram_width; 444 445 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n", 446 &adev->gmc.aper_base, 447 mem_info->local_mem_size_public, 448 mem_info->local_mem_size_private); 449 450 if (adev->pm.dpm_enabled) { 451 if (amdgpu_emu_mode == 1) 452 mem_info->mem_clk_max = 0; 453 else 454 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 455 } else 456 mem_info->mem_clk_max = 100; 457 } 458 459 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev) 460 { 461 if (adev->gfx.funcs->get_gpu_clock_counter) 462 return adev->gfx.funcs->get_gpu_clock_counter(adev); 463 return 0; 464 } 465 466 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev) 467 { 468 /* the sclk is in quantas of 10kHz */ 469 if (adev->pm.dpm_enabled) 470 return amdgpu_dpm_get_sclk(adev, false) / 100; 471 else 472 return 100; 473 } 474 475 void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev, struct kfd_cu_info *cu_info) 476 { 477 struct amdgpu_cu_info acu_info = adev->gfx.cu_info; 478 479 memset(cu_info, 0, sizeof(*cu_info)); 480 if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap)) 481 return; 482 483 cu_info->cu_active_number = acu_info.number; 484 cu_info->cu_ao_mask = acu_info.ao_cu_mask; 485 memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0], 486 sizeof(cu_info->cu_bitmap)); 487 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines; 488 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 489 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 490 cu_info->simd_per_cu = acu_info.simd_per_cu; 491 cu_info->max_waves_per_simd = acu_info.max_waves_per_simd; 492 cu_info->wave_front_size = acu_info.wave_front_size; 493 cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu; 494 cu_info->lds_size = acu_info.lds_size; 495 } 496 497 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 498 struct amdgpu_device **dmabuf_adev, 499 uint64_t *bo_size, void *metadata_buffer, 500 size_t buffer_size, uint32_t *metadata_size, 501 uint32_t *flags, int8_t *xcp_id) 502 { 503 struct dma_buf *dma_buf; 504 struct drm_gem_object *obj; 505 struct amdgpu_bo *bo; 506 uint64_t metadata_flags; 507 int r = -EINVAL; 508 509 dma_buf = dma_buf_get(dma_buf_fd); 510 if (IS_ERR(dma_buf)) 511 return PTR_ERR(dma_buf); 512 513 if (dma_buf->ops != &amdgpu_dmabuf_ops) 514 /* Can't handle non-graphics buffers */ 515 goto out_put; 516 517 obj = dma_buf->priv; 518 if (obj->dev->driver != adev_to_drm(adev)->driver) 519 /* Can't handle buffers from different drivers */ 520 goto out_put; 521 522 adev = drm_to_adev(obj->dev); 523 bo = gem_to_amdgpu_bo(obj); 524 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 525 AMDGPU_GEM_DOMAIN_GTT))) 526 /* Only VRAM and GTT BOs are supported */ 527 goto out_put; 528 529 r = 0; 530 if (dmabuf_adev) 531 *dmabuf_adev = adev; 532 if (bo_size) 533 *bo_size = amdgpu_bo_size(bo); 534 if (metadata_buffer) 535 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 536 metadata_size, &metadata_flags); 537 if (flags) { 538 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 539 KFD_IOC_ALLOC_MEM_FLAGS_VRAM 540 : KFD_IOC_ALLOC_MEM_FLAGS_GTT; 541 542 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 543 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC; 544 } 545 if (xcp_id) 546 *xcp_id = bo->xcp_id; 547 548 out_put: 549 dma_buf_put(dma_buf); 550 return r; 551 } 552 553 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst, 554 struct amdgpu_device *src) 555 { 556 struct amdgpu_device *peer_adev = src; 557 struct amdgpu_device *adev = dst; 558 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev); 559 560 if (ret < 0) { 561 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n", 562 adev->gmc.xgmi.physical_node_id, 563 peer_adev->gmc.xgmi.physical_node_id, ret); 564 ret = 0; 565 } 566 return (uint8_t)ret; 567 } 568 569 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst, 570 struct amdgpu_device *src, 571 bool is_min) 572 { 573 struct amdgpu_device *adev = dst, *peer_adev; 574 int num_links; 575 576 if (adev->asic_type != CHIP_ALDEBARAN) 577 return 0; 578 579 if (src) 580 peer_adev = src; 581 582 /* num links returns 0 for indirect peers since indirect route is unknown. */ 583 num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev); 584 if (num_links < 0) { 585 DRM_ERROR("amdgpu: failed to get xgmi num links between node %d and %d. ret = %d\n", 586 adev->gmc.xgmi.physical_node_id, 587 peer_adev->gmc.xgmi.physical_node_id, num_links); 588 num_links = 0; 589 } 590 591 /* Aldebaran xGMI DPM is defeatured so assume x16 x 25Gbps for bandwidth. */ 592 return (num_links * 16 * 25000)/BITS_PER_BYTE; 593 } 594 595 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) 596 { 597 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) : 598 fls(adev->pm.pcie_mlw_mask)) - 1; 599 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask & 600 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) : 601 fls(adev->pm.pcie_gen_mask & 602 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1; 603 uint32_t num_lanes_mask = 1 << num_lanes_shift; 604 uint32_t gen_speed_mask = 1 << gen_speed_shift; 605 int num_lanes_factor = 0, gen_speed_mbits_factor = 0; 606 607 switch (num_lanes_mask) { 608 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1: 609 num_lanes_factor = 1; 610 break; 611 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2: 612 num_lanes_factor = 2; 613 break; 614 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4: 615 num_lanes_factor = 4; 616 break; 617 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8: 618 num_lanes_factor = 8; 619 break; 620 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12: 621 num_lanes_factor = 12; 622 break; 623 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16: 624 num_lanes_factor = 16; 625 break; 626 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32: 627 num_lanes_factor = 32; 628 break; 629 } 630 631 switch (gen_speed_mask) { 632 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1: 633 gen_speed_mbits_factor = 2500; 634 break; 635 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2: 636 gen_speed_mbits_factor = 5000; 637 break; 638 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3: 639 gen_speed_mbits_factor = 8000; 640 break; 641 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4: 642 gen_speed_mbits_factor = 16000; 643 break; 644 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5: 645 gen_speed_mbits_factor = 32000; 646 break; 647 } 648 649 return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE; 650 } 651 652 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 653 enum kgd_engine_type engine, 654 uint32_t vmid, uint64_t gpu_addr, 655 uint32_t *ib_cmd, uint32_t ib_len) 656 { 657 struct amdgpu_job *job; 658 struct amdgpu_ib *ib; 659 struct amdgpu_ring *ring; 660 struct dma_fence *f = NULL; 661 int ret; 662 663 switch (engine) { 664 case KGD_ENGINE_MEC1: 665 ring = &adev->gfx.compute_ring[0]; 666 break; 667 case KGD_ENGINE_SDMA1: 668 ring = &adev->sdma.instance[0].ring; 669 break; 670 case KGD_ENGINE_SDMA2: 671 ring = &adev->sdma.instance[1].ring; 672 break; 673 default: 674 pr_err("Invalid engine in IB submission: %d\n", engine); 675 ret = -EINVAL; 676 goto err; 677 } 678 679 ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &job); 680 if (ret) 681 goto err; 682 683 ib = &job->ibs[0]; 684 memset(ib, 0, sizeof(struct amdgpu_ib)); 685 686 ib->gpu_addr = gpu_addr; 687 ib->ptr = ib_cmd; 688 ib->length_dw = ib_len; 689 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 690 job->vmid = vmid; 691 job->num_ibs = 1; 692 693 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 694 695 if (ret) { 696 DRM_ERROR("amdgpu: failed to schedule IB.\n"); 697 goto err_ib_sched; 698 } 699 700 /* Drop the initial kref_init count (see drm_sched_main as example) */ 701 dma_fence_put(f); 702 ret = dma_fence_wait(f, false); 703 704 err_ib_sched: 705 amdgpu_job_free(job); 706 err: 707 return ret; 708 } 709 710 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle) 711 { 712 /* Temporary workaround to fix issues observed in some 713 * compute applications when GFXOFF is enabled on GFX11. 714 */ 715 if (IP_VERSION_MAJ(adev->ip_versions[GC_HWIP][0]) == 11) { 716 pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled"); 717 amdgpu_gfx_off_ctrl(adev, idle); 718 } 719 amdgpu_dpm_switch_power_profile(adev, 720 PP_SMC_POWER_PROFILE_COMPUTE, 721 !idle); 722 } 723 724 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 725 { 726 if (adev->kfd.dev) 727 return vmid >= adev->vm_manager.first_kfd_vmid; 728 729 return false; 730 } 731 732 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev, 733 uint16_t vmid) 734 { 735 if (adev->family == AMDGPU_FAMILY_AI) { 736 int i; 737 738 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) 739 amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0); 740 } else { 741 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 0); 742 } 743 744 return 0; 745 } 746 747 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 748 uint16_t pasid, 749 enum TLB_FLUSH_TYPE flush_type, 750 uint32_t inst) 751 { 752 bool all_hub = false; 753 754 if (adev->family == AMDGPU_FAMILY_AI || 755 adev->family == AMDGPU_FAMILY_RV) 756 all_hub = true; 757 758 return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub, inst); 759 } 760 761 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev) 762 { 763 return adev->have_atomics_support; 764 } 765 766 void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev) 767 { 768 amdgpu_device_flush_hdp(adev, NULL); 769 } 770 771 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset) 772 { 773 amdgpu_umc_poison_handler(adev, reset); 774 } 775 776 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, 777 uint32_t *payload) 778 { 779 int ret; 780 781 /* Device or IH ring is not ready so bail. */ 782 ret = amdgpu_ih_wait_on_checkpoint_process_ts(adev, &adev->irq.ih); 783 if (ret) 784 return ret; 785 786 /* Send payload to fence KFD interrupts */ 787 amdgpu_amdkfd_interrupt(adev, payload); 788 789 return 0; 790 } 791 792 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev) 793 { 794 if (adev->gfx.ras && adev->gfx.ras->query_utcl2_poison_status) 795 return adev->gfx.ras->query_utcl2_poison_status(adev); 796 else 797 return false; 798 } 799 800 int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev) 801 { 802 return kgd2kfd_check_and_lock_kfd(); 803 } 804 805 void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev) 806 { 807 kgd2kfd_unlock_kfd(); 808 } 809 810 811 u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id) 812 { 813 u64 tmp; 814 s8 mem_id = KFD_XCP_MEM_ID(adev, xcp_id); 815 816 if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) { 817 tmp = adev->gmc.mem_partitions[mem_id].size; 818 do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition); 819 return ALIGN_DOWN(tmp, PAGE_SIZE); 820 } else { 821 return adev->gmc.real_vram_size; 822 } 823 } 824 825 int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, 826 u32 inst) 827 { 828 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; 829 struct amdgpu_ring *kiq_ring = &kiq->ring; 830 struct amdgpu_ring_funcs *ring_funcs; 831 struct amdgpu_ring *ring; 832 int r = 0; 833 834 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 835 return -EINVAL; 836 837 ring_funcs = kzalloc(sizeof(*ring_funcs), GFP_KERNEL); 838 if (!ring_funcs) 839 return -ENOMEM; 840 841 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 842 if (!ring) { 843 r = -ENOMEM; 844 goto free_ring_funcs; 845 } 846 847 ring_funcs->type = AMDGPU_RING_TYPE_COMPUTE; 848 ring->doorbell_index = doorbell_off; 849 ring->funcs = ring_funcs; 850 851 spin_lock(&kiq->ring_lock); 852 853 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 854 spin_unlock(&kiq->ring_lock); 855 r = -ENOMEM; 856 goto free_ring; 857 } 858 859 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0); 860 861 if (kiq_ring->sched.ready && !adev->job_hang) 862 r = amdgpu_ring_test_helper(kiq_ring); 863 864 spin_unlock(&kiq->ring_lock); 865 866 free_ring: 867 kfree(ring); 868 869 free_ring_funcs: 870 kfree(ring_funcs); 871 872 return r; 873 } 874