xref: /plan9/sys/src/9/teg2/caches-v7.c (revision 3de6a9c0b3d5cf34fc4090d0bf1930d83799a7fd)
1 /*
2  * caches defined by arm v7 architecture
3  */
4 #include "u.h"
5 #include "../port/lib.h"
6 #include "mem.h"
7 #include "dat.h"
8 #include "fns.h"
9 #include "../port/error.h"
10 #include "io.h"
11 #include "arm.h"
12 
13 static char *
l1iptype(uint type)14 l1iptype(uint type)
15 {
16 	static char *types[] = {
17 		"reserved",
18 		"asid-tagged VIVT",
19 		"VIPT",
20 		"PIPT",
21 	};
22 
23 	if (type >= nelem(types) || types[type] == nil)
24 		return "GOK";
25 	return types[type];
26 }
27 
28 static char *catype[] = {
29 	"none,",
30 	"i,",
31 	"d,",
32 	"split i&d,",
33 	"unified,",
34 	"gok,",
35 	"gok,",
36 	"gok,",
37 };
38 
39 void
cacheinfo(int level,Memcache * cp,int ext,int type)40 cacheinfo(int level, Memcache *cp, int ext, int type)
41 {
42 	ulong setsways;
43 
44 	memset(cp, 0, sizeof *cp);
45 	if (type == Nocache)
46 		return;
47 	cp->level = level;
48 	cp->type = type;
49 	cp->external = ext;
50 	if (level == 2) {			/* external PL310 */
51 		allcache->info(cp);
52 		setsways = cp->setsways;
53 	} else {
54 		/* select internal cache level */
55 		cpwrsc(CpIDcssel, CpID, CpIDid, 0, (level - 1) << 1);
56 
57 		setsways = cprdsc(CpIDcsize, CpID, CpIDid, 0);
58 		cp->l1ip = cpctget();
59 		cp->nways = ((setsways >> 3)  & MASK(10)) + 1;
60 		cp->nsets = ((setsways >> 13) & MASK(15)) + 1;
61 		cp->log2linelen = (setsways & MASK(2)) + 2 + 2;
62 	}
63 	cp->linelen = 1 << cp->log2linelen;
64 	cp->setsways = setsways;
65 	cp->setsh = cp->log2linelen;
66 	cp->waysh = 32 - log2(cp->nways);
67 }
68 
69 void
allcacheinfo(Memcache * mc)70 allcacheinfo(Memcache *mc)
71 {
72 	int n;
73 	ulong lvl;
74 
75 	lvl = cprdsc(CpIDcsize, CpID, CpIDidct, CpIDclvlid);
76 	n = 1;
77 	for (lvl &= MASK(21); lvl; lvl >>= 3)
78 		cacheinfo(n, &mc[n], Intcache, lvl & MASK(3));
79 //	cacheinfo(2, &mc[2], Extcache, Unified);		/* PL310 */
80 }
81 
82 void
prcachecfg(void)83 prcachecfg(void)
84 {
85 	int cache;
86 	Memcache *mc;
87 
88 	for (cache = 1; cache < 8 && cachel[cache].type; cache++) {
89 		mc = &cachel[cache];
90 		iprint("l%d: %s %-10s %2d ways %4d sets %d bytes/line; can W[",
91 			mc->level, mc->external? "ext": "int", catype[mc->type],
92 			mc->nways, mc->nsets, mc->linelen);
93 		if (mc->linelen != CACHELINESZ)
94 			iprint(" *should* be %d", CACHELINESZ);
95 		if (mc->setsways & Cawt)
96 			iprint("T");
97 		if (mc->setsways & Cawb)
98 			iprint("B");
99 		if (mc->setsways & Cawa)
100 			iprint("A");
101 		iprint("]");
102 		if (cache == 1)
103 			iprint("; l1-i %s", l1iptype((mc->l1ip >> 14) & MASK(2)));
104 		iprint("\n");
105 	}
106 }
107