1 /* 2 * Time. 3 * 4 * HZ should divide 1000 evenly, ideally. 5 * 100, 125, 200, 250 and 333 are okay. 6 */ 7 #define HZ 100 /* clock frequency */ 8 #define MS2HZ (1000/HZ) /* millisec per clock tick */ 9 #define TK2SEC(t) ((t)/HZ) /* ticks to seconds */ 10 11 enum { 12 Mhz = 1000 * 1000, 13 Dogsectimeout = 4, /* must be ≤ 34 s. to fit in a ulong */ 14 }; 15 16 /* 17 * More accurate time 18 */ 19 #define MS2TMR(t) ((ulong)(((uvlong)(t) * m->cpuhz)/1000)) 20 #define US2TMR(t) ((ulong)(((uvlong)(t) * m->cpuhz)/1000000)) 21 22 #define CONSOLE 0 23 24 typedef struct Conf Conf; 25 typedef struct Confmem Confmem; 26 typedef struct FPsave FPsave; 27 typedef struct ISAConf ISAConf; 28 typedef struct Isolated Isolated; 29 typedef struct Label Label; 30 typedef struct Lock Lock; 31 typedef struct Lowmemcache Lowmemcache; 32 typedef struct Memcache Memcache; 33 typedef struct MMMU MMMU; 34 typedef struct Mach Mach; 35 typedef u32int Mreg; /* Msr - bloody UART */ 36 typedef struct Notsave Notsave; 37 typedef struct Page Page; 38 typedef struct Pcisiz Pcisiz; 39 typedef struct Pcidev Pcidev; 40 typedef struct PhysUart PhysUart; 41 typedef struct PMMU PMMU; 42 typedef struct Proc Proc; 43 typedef u32int PTE; 44 typedef struct Soc Soc; 45 typedef struct Uart Uart; 46 typedef struct Ureg Ureg; 47 typedef uvlong Tval; 48 49 #pragma incomplete Pcidev 50 #pragma incomplete Ureg 51 52 #define MAXSYSARG 5 /* for mount(fd, mpt, flag, arg, srv) */ 53 54 /* 55 * parameters for sysproc.c 56 */ 57 #define AOUT_MAGIC (E_MAGIC) 58 59 struct Lock 60 { 61 ulong key; 62 u32int sr; 63 uintptr pc; 64 Proc* p; 65 Mach* m; 66 int isilock; 67 }; 68 69 struct Label 70 { 71 uintptr sp; 72 uintptr pc; 73 }; 74 75 enum { 76 Maxfpregs = 32, /* could be 16 or 32, see Mach.fpnregs */ 77 Nfpctlregs = 16, 78 }; 79 80 /* 81 * emulated or vfp3 floating point 82 */ 83 struct FPsave 84 { 85 ulong status; 86 ulong control; 87 /* 88 * vfp3 with ieee fp regs; uvlong is sufficient for hardware but 89 * each must be able to hold an Internal from fpi.h for sw emulation. 90 */ 91 ulong regs[Maxfpregs][3]; 92 93 int fpstate; 94 uintptr pc; /* of failed fp instr. */ 95 }; 96 97 /* 98 * FPsave.fpstate 99 */ 100 enum 101 { 102 FPinit, 103 FPactive, 104 FPinactive, 105 FPemu, 106 107 /* bit or'd with the state */ 108 FPillegal= 0x100, 109 }; 110 111 struct Confmem 112 { 113 uintptr base; 114 usize npage; 115 uintptr limit; 116 uintptr kbase; 117 uintptr klimit; 118 }; 119 120 struct Conf 121 { 122 ulong nmach; /* processors */ 123 ulong nproc; /* processes */ 124 Confmem mem[1]; /* physical memory */ 125 ulong npage; /* total physical pages of memory */ 126 usize upages; /* user page pool */ 127 ulong copymode; /* 0 is copy on write, 1 is copy on reference */ 128 ulong ialloc; /* max interrupt time allocation in bytes */ 129 ulong pipeqsize; /* size in bytes of pipe queues */ 130 ulong nimage; /* number of page cache image headers */ 131 ulong nswap; /* number of swap pages */ 132 int nswppo; /* max # of pageouts per segment pass */ 133 ulong hz; /* processor cycle freq */ 134 ulong mhz; 135 int monitor; /* flag */ 136 }; 137 138 /* 139 * things saved in the Proc structure during a notify 140 */ 141 struct Notsave { 142 int emptiness; 143 }; 144 145 /* 146 * MMU stuff in Mach. 147 */ 148 struct MMMU 149 { 150 PTE* mmul1; /* l1 for this processor */ 151 int mmul1lo; 152 int mmul1hi; 153 int mmupid; 154 }; 155 156 /* 157 * MMU stuff in proc 158 */ 159 #define NCOLOR 1 /* 1 level cache, don't worry about VCE's */ 160 struct PMMU 161 { 162 Page* mmul2; 163 Page* mmul2cache; /* free mmu pages */ 164 }; 165 166 #include "../port/portdat.h" 167 168 struct Mach 169 { 170 /* offsets known to asm */ 171 int machno; /* physical id of processor */ 172 uintptr splpc; /* pc of last caller to splhi */ 173 174 Proc* proc; /* current process */ 175 176 MMMU; 177 /* end of offsets known to asm */ 178 int flushmmu; /* flush current proc mmu state */ 179 180 ulong ticks; /* of the clock since boot time */ 181 Label sched; /* scheduler wakeup */ 182 Lock alarmlock; /* access to alarm list */ 183 void* alarm; /* alarms bound to this clock */ 184 int inclockintr; 185 186 Proc* readied; /* for runproc */ 187 ulong schedticks; /* next forced context switch */ 188 189 int cputype; 190 ulong delayloop; 191 192 /* stats */ 193 int tlbfault; 194 int tlbpurge; 195 int pfault; 196 int cs; 197 int syscall; 198 int load; 199 int intr; 200 uvlong fastclock; /* last sampled value */ 201 ulong spuriousintr; 202 int lastintr; 203 int ilockdepth; 204 Perf perf; /* performance counters */ 205 206 int probing; /* probeaddr() state */ 207 int trapped; 208 Lock probelock; 209 int inidlehands; 210 211 int cpumhz; 212 uvlong cpuhz; /* speed of cpu */ 213 uvlong cyclefreq; /* Frequency of user readable cycle counter */ 214 215 /* vfp3 fpu */ 216 int havefp; 217 int havefpvalid; 218 int fpon; 219 int fpconfiged; 220 int fpnregs; 221 ulong fpscr; /* sw copy */ 222 int fppid; /* pid of last fault */ 223 uintptr fppc; /* addr of last fault */ 224 int fpcnt; /* how many consecutive at that addr */ 225 226 /* save areas for exceptions, hold R0-R4 */ 227 u32int sfiq[5]; 228 u32int sirq[5]; 229 u32int sund[5]; 230 u32int sabt[5]; 231 u32int smon[5]; /* probably not needed */ 232 u32int ssys[5]; 233 234 int stack[1]; 235 }; 236 237 /* 238 * Fake kmap. 239 */ 240 typedef void KMap; 241 #define VA(k) ((uintptr)(k)) 242 #define kmap(p) (KMap*)((p)->pa|kseg0) 243 #define kunmap(k) 244 245 struct 246 { 247 Lock; 248 int machs; /* bitmap of active CPUs */ 249 int wfi; /* bitmap of CPUs in WFI state */ 250 int stopped; /* bitmap of CPUs stopped */ 251 int exiting; /* shutdown */ 252 int ispanic; /* shutdown in response to a panic */ 253 int thunderbirdsarego; /* lets the added processors continue to schedinit */ 254 }active; 255 256 extern register Mach* m; /* R10 */ 257 extern register Proc* up; /* R9 */ 258 259 /* an object guaranteed to be in its own cache line */ 260 typedef uchar Cacheline[CACHELINESZ]; 261 struct Isolated { 262 Cacheline c0; 263 ulong word; 264 Cacheline c1; 265 }; 266 267 extern Memcache cachel[]; /* arm arch v7 supports 1-7 */ 268 extern ulong intrcount[MAXMACH]; 269 extern int irqtooearly; 270 extern uintptr kseg0; 271 extern Isolated l1ptstable; 272 extern uchar *l2pages; 273 extern Mach* machaddr[MAXMACH]; 274 extern ulong memsize; 275 extern int navailcpus; 276 extern int normalprint; 277 278 /* 279 * a parsed plan9.ini line 280 */ 281 #define NISAOPT 8 282 283 struct ISAConf { 284 char *type; 285 ulong port; 286 int irq; 287 ulong dma; 288 ulong mem; 289 ulong size; 290 ulong freq; 291 292 int nopt; 293 char *opt[NISAOPT]; 294 }; 295 296 #define MACHP(n) machaddr[n] 297 298 /* 299 * Horrid. But the alternative is 'defined'. 300 */ 301 #ifdef _DBGC_ 302 #define DBGFLG (dbgflg[_DBGC_]) 303 #else 304 #define DBGFLG (0) 305 #endif /* _DBGC_ */ 306 307 int vflag; 308 extern char dbgflg[256]; 309 310 #define dbgprint print /* for now */ 311 312 /* 313 * hardware info about a device 314 */ 315 typedef struct { 316 ulong port; 317 int size; 318 } Devport; 319 320 struct DevConf 321 { 322 ulong intnum; /* interrupt number */ 323 char *type; /* card type, malloced */ 324 int nports; /* Number of ports */ 325 Devport *ports; /* The ports themselves */ 326 }; 327 328 /* characteristics of a given arm cache level */ 329 struct Memcache { 330 uint waysh; /* shifts for set/way register */ 331 uint setsh; 332 333 uint log2linelen; 334 335 uint level; /* 1 is nearest processor, 2 further away */ 336 uint type; 337 uint external; /* flag */ 338 uint l1ip; /* l1 I policy */ 339 340 uint nways; /* associativity */ 341 uint nsets; 342 uint linelen; /* bytes per cache line */ 343 uint setsways; 344 }; 345 enum Cachetype { 346 Nocache, 347 Ionly, 348 Donly, 349 Splitid, 350 Unified, 351 }; 352 enum { 353 Intcache, 354 Extcache, 355 }; 356 357 /* 358 * characteristics of cache level, kept at low, fixed address (CACHECONF). 359 * all offsets are known to cache.v7.s. 360 */ 361 struct Lowmemcache { 362 uint l1waysh; /* shifts for set/way register */ 363 uint l1setsh; 364 uint l2waysh; 365 uint l2setsh; 366 }; 367 368 /* 369 * cache capabilities. write-back vs write-through is controlled 370 * by the Buffered bit in PTEs. 371 * 372 * see cache.v7.s and Memcache in dat.h 373 */ 374 enum { 375 Cawt = 1 << 31, 376 Cawb = 1 << 30, 377 Cara = 1 << 29, 378 Cawa = 1 << 28, 379 }; 380 381 /* non-architectural L2 cache */ 382 typedef struct Cacheimpl Cacheimpl; 383 struct Cacheimpl { 384 void (*info)(Memcache *); 385 void (*on)(void); 386 void (*off)(void); 387 388 void (*inv)(void); 389 void (*wb)(void); 390 void (*wbinv)(void); 391 392 void (*invse)(void *, int); 393 void (*wbse)(void *, int); 394 void (*wbinvse)(void *, int); 395 }; 396 /* extern */ Cacheimpl *l2cache, *allcache, *nocache, *l1cache; 397 398 enum Dmamode { 399 Const, 400 Postincr, 401 Index, 402 Index2, 403 }; 404 405 /* pmu = power management unit */ 406 enum Irqs { 407 /* 408 * 1st 32 gic irqs reserved for cpu; private interrupts. 409 * 0—15 are software-generated by other cpus; 410 * 16—31 are private peripheral intrs. 411 */ 412 Cpu0irq = 0, 413 Cpu1irq, 414 /* ... */ 415 Cpu15irq = 15, 416 Glbtmrirq = 27, 417 Loctmrirq = 29, 418 Wdtmrirq = 30, 419 420 /* shared interrupts */ 421 Ctlr0base = (1+0)*32, /* primary ctlr */ 422 Tn0irq = Ctlr0base + 0, /* tegra timers */ 423 Tn1irq = Ctlr0base + 1, 424 Rtcirq = Ctlr0base + 2, 425 426 Ctlr1base = (1+1)*32, /* secondary ctlr */ 427 Uartirq = Ctlr1base + 4, 428 Tn2irq = Ctlr1base + 9, /* tegra timers */ 429 Tn3irq = Ctlr1base + 10, 430 /* +24 is cpu0_pmu_intr, +25 is cpu1_pum_intr */ 431 432 Ctlr2base = (1+2)*32, /* ternary ctlr */ 433 Extpmuirq = Ctlr2base + 22, 434 435 Ctlr3base = (1+3)*32, /* quad ctlr */ 436 Pcieirq = Ctlr3base + 2, 437 }; 438 439 struct Soc { /* addr's of SoC controllers */ 440 uintptr clkrst; 441 uintptr power; 442 uintptr exceptvec; 443 uintptr sema; 444 uintptr l2cache; 445 uintptr flow; 446 447 /* private memory region */ 448 uintptr scu; 449 uintptr intr; /* `cpu interface' */ 450 /* private-peripheral-interrupt cortex-a clocks */ 451 uintptr glbtmr; 452 uintptr loctmr; 453 454 uintptr intrdist; 455 456 uintptr uart[5]; 457 458 /* shared-peripheral-interrupt tegra2 clocks */ 459 uintptr rtc; /* real-time clock */ 460 uintptr tmr[4]; 461 uintptr µs; 462 463 uintptr pci; 464 uintptr ether; 465 466 uintptr ehci; 467 uintptr ide; 468 469 uintptr nand; 470 uintptr nor; 471 472 uintptr spi[4]; 473 uintptr twsi; 474 uintptr mmc[4]; 475 uintptr gpio[7]; 476 } soc; 477 extern Soc soc; 478