| /llvm-project/llvm/lib/IR/ |
| H A D | AutoUpgrade.cpp | 1654 upgradeX86VPERMT2Intrinsics(IRBuilder<> & Builder,CallBase & CI,bool ZeroMask,bool IndexForm) upgradeX86VPERMT2Intrinsics() argument
1797 upgradeX86ConcatShift(IRBuilder<> & Builder,CallBase & CI,bool IsShiftRight,bool ZeroMask) upgradeX86ConcatShift() argument
2757 bool ZeroMask = Name[11] == 'z'; upgradeX86IntrinsicCall() local
2762 bool ZeroMask = Name[11] == 'z'; upgradeX86IntrinsicCall() local
3778 bool ZeroMask = Name[11] == 'z'; upgradeX86IntrinsicCall() local
3806 bool ZeroMask = Name[11] == 'z'; upgradeX86IntrinsicCall() local
3835 bool ZeroMask = Name[11] == 'z'; upgradeX86IntrinsicCall() local
3842 bool ZeroMask = Name[11] == 'z'; upgradeX86IntrinsicCall() local
3872 bool ZeroMask = Name[11] == 'z'; upgradeX86IntrinsicCall() local
[all...] |
| /llvm-project/llvm/unittests/IR/ |
| H A D | PatternMatch.cpp | 1202 SmallVector<int, 16> ZeroMask; TEST_F() local
|
| /llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.cpp | 757 SmallVector<int, 16> ZeroMask(DstTy.getNumElements()); buildShuffleSplat() local
|
| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 943 APInt ZeroMask = APInt::getHighBitsSet(BitWidth, BitWidth - PossibleBits); computeKnownBitsForTargetNode() local
|
| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 13832 unsigned ZeroMask = 0x0c0c0c0c; placeSources() local
13875 unsigned ZeroMask = 0x0c0c0c0c; placeSources() local
13961 auto ZeroMask = ChainLength == 2 ? 0x0c0c0000 : 0x0c000000; fixMasks() local
|
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 5868 uint64_t ZeroMask = IsAndN ? 255 : 0; getFauxShuffleMask() local
6141 APInt ZeroMask = APInt::getHighBitsSet(2 * NumBitsPerElt, NumBitsPerElt); getFauxShuffleMask() local
6931 APInt ZeroMask = APInt::getZero(NumElems); EltsFromConsecutiveLoads() local
8819 APInt ZeroMask = APInt::getZero(NumElems); LowerBUILD_VECTOR() local
9718 APInt &ZeroMask = ExpectedIdx < Size ? ZeroV1 : ZeroV2; isTargetShuffleEquivalent() local
9876 SDValue ZeroMask = DAG.getConstant(0x80, DL, MVT::i8); lowerShuffleWithPSHUFB() local
10409 APInt ZeroMask = APInt::getHighBitsSet(NumSrcBits, NumPackedBits); matchShuffleWithPACK() local
13849 const int ZeroMask = 0x80; lowerShuffleAsBlendOfPSHUFBs() local
40546 unsigned ZeroMask = InsertPSMask & 0xF; canonicalizeShuffleWithOp() local
41236 unsigned ZeroMask = InsertPSMask & 0xF; combineTargetShuffle() local
54039 APInt ZeroMask = APInt::getHighBitsSet(NumSrcEltBits, NumSrcEltBits / 2); combineZext() local
[all...] |
| /llvm-project/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 13929 EmitScalarFMAExpr(CodeGenFunction & CGF,const CallExpr * E,MutableArrayRef<Value * > Ops,Value * Upper,bool ZeroMask=false,unsigned PTIdx=0,bool NegAcc=false) EmitScalarFMAExpr() argument
14014 EmitX86Ternlog(CodeGenFunction & CGF,bool ZeroMask,ArrayRef<Value * > Ops) EmitX86Ternlog() argument
|
| /llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 25757 SmallVector<int, 16> ZeroMask(VT.getVectorNumElements(), 0); visitVECTOR_SHUFFLE() local
[all...] |