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Searched defs:WR2_INTR_1 (Results 1 – 2 of 2) sorted by relevance

/openbsd-src/sys/arch/luna88k/dev/
H A Dsioreg.h81 #define WR2_INTR_1 0x04 /* Interrupt Priority: RxA RxB TxA TxB E/SA E/SA */ macro
/openbsd-src/sys/arch/luna88k/stand/boot/
H A Dsioreg.h129 #define WR2_INTR_1 0x04 /* Interrupt Priority: RxA RxB TxA TxB E/SA E/SA */ macro