| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 90 Register VirtReg; ///< Virtual register number. member
244 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { in findLiveVirtReg()
308 int RegAllocFast::getStackSpaceFor(Register VirtReg) { in getStackSpaceFor()
341 bool RegAllocFast::mayLiveOut(Register VirtReg) { in mayLiveOut()
385 bool RegAllocFast::mayLiveIn(Register VirtReg) { in mayLiveIn()
404 void RegAllocFast::spill(MachineBasicBlock::iterator Before, Register VirtReg, in spill()
460 void RegAllocFast::reload(MachineBasicBlock::iterator Before, Register VirtReg, in reload()
568 switch (unsigned VirtReg = RegUnitStates[Unit]) { in displacePhysReg() local
597 switch (unsigned VirtReg = RegUnitStates[FirstUnit]) { in freePhysReg() local
622 switch (unsigned VirtReg = RegUnitStates[*UI]) { in calcSpillCost() local
[all …]
|
| H A D | LiveRegMatrix.cpp | 104 void LiveRegMatrix::assign(LiveInterval &VirtReg, MCRegister PhysReg) { in assign()
121 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign()
146 bool LiveRegMatrix::checkRegMaskInterference(LiveInterval &VirtReg, in checkRegMaskInterference()
164 bool LiveRegMatrix::checkRegUnitInterference(LiveInterval &VirtReg, in checkRegUnitInterference()
186 LiveRegMatrix::checkInterference(LiveInterval &VirtReg, MCRegister PhysReg) { in checkInterference()
|
| H A D | RegAllocBasic.cpp | 164 void RABasic::LRE_WillShrinkVirtReg(Register VirtReg) { in LRE_WillShrinkVirtReg()
209 bool RABasic::spillInterferences(LiveInterval &VirtReg, MCRegister PhysReg, in spillInterferences()
261 MCRegister RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit()
|
| H A D | RegAllocGreedy.cpp | 255 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage()
674 bool RAGreedy::LRE_CanEraseVirtReg(Register VirtReg) { in LRE_CanEraseVirtReg()
689 void RAGreedy::LRE_WillShrinkVirtReg(Register VirtReg) { in LRE_WillShrinkVirtReg()
799 MCRegister RAGreedy::tryAssign(LiveInterval &VirtReg, in tryAssign()
853 Register RAGreedy::canReassign(LiveInterval &VirtReg, Register PrevReg) const { in canReassign()
918 LiveInterval &VirtReg, MCRegister PhysReg, bool IsHint, in canEvictInterference()
1015 bool RAGreedy::canEvictInterferenceInRange(const LiveInterval &VirtReg, in canEvictInterferenceInRange()
1068 const LiveInterval &VirtReg, in getCheapestEvicteeWeight()
1093 void RAGreedy::evictInterference(LiveInterval &VirtReg, MCRegister PhysReg, in evictInterference()
1150 MCRegister RAGreedy::tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, in tryEvict()
[all …]
|
| H A D | LiveIntervalUnion.cpp | 29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) { in unify()
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) { in extract()
|
| H A D | AllocationOrder.cpp | 29 AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM, in create()
|
| H A D | RegisterCoalescer.h | 64 CoalescerPair(Register VirtReg, MCRegister PhysReg, in CoalescerPair()
|
| H A D | RegAllocBase.cpp | 88 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
|
| H A D | PHIElimination.cpp | 165 unsigned VirtReg = Register::index2VirtReg(Index); in runOnMachineFunction() local
251 static bool isImplicitlyDefined(unsigned VirtReg, in isImplicitlyDefined()
|
| H A D | VirtRegMap.cpp | 326 Register VirtReg = Register::index2VirtReg(Idx); in addMBBLiveIns() local
543 Register VirtReg = MO.getReg(); in rewrite() local
|
| H A D | LiveDebugVariables.cpp | 755 void LDVImpl::mapVirtReg(Register VirtReg, UserValue *EC) { in mapVirtReg()
761 UserValue *LDVImpl::lookupVirtReg(Register VirtReg) { in lookupVirtReg()
1426 Register VirtReg = Loc.getReg(); in rewriteLocations() local
|
| H A D | MachineBasicBlock.cpp | 618 Register VirtReg = I->getOperand(0).getReg(); in addLiveIn() local
625 Register VirtReg = MRI.createVirtualRegister(RC); in addLiveIn() local
|
| H A D | TargetRegisterInfo.cpp | 422 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
|
| H A D | LiveVariables.cpp | 815 Register VirtReg = Register::index2VirtReg(R); in addNewBlock() local
|
| H A D | InlineSpiller.cpp | 576 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) { in reMaterializeFor()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreAllocateWWMRegs.cpp | 124 const Register VirtReg = MO.getReg(); in rewriteRegs() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86TileConfig.cpp | 118 Register VirtReg = Register::index2VirtReg(I); in INITIALIZE_PASS_DEPENDENCY() local
|
| H A D | X86RegisterInfo.cpp | 875 static ShapeT getTileShape(Register VirtReg, VirtRegMap *VRM, in getTileShape()
909 bool X86RegisterInfo::getRegAllocationHints(Register VirtReg, in getRegAllocationHints()
|
| H A D | X86InstrInfo.cpp | 3805 Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass); in storeRegToStackSlot() local
3833 Register VirtReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass); in loadRegFromStackSlot() local
|
| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | VirtRegMap.h | 170 Register getOriginal(Register VirtReg) const { in getOriginal()
|
| H A D | ScheduleDAGInstrs.h | 53 unsigned VirtReg; member
|
| H A D | TargetRegisterInfo.h | 1049 const LiveInterval &VirtReg) const { in shouldUseLastChanceRecoloringForVirtReg()
1064 const LiveInterval &VirtReg) const { in shouldUseDeferredSpillingForVirtReg()
|
| H A D | RegisterPressure.h | 535 bool hasUntiedDef(Register VirtReg) const { in hasUntiedDef()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.cpp | 75 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.cpp | 319 Register VirtReg, ArrayRef<MCPhysReg> Order, in getRegAllocationHints()
|