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Searched defs:VectorWidth (Results 1 – 9 of 9) sorted by relevance

/llvm-project/llvm/lib/Transforms/Scalar/
H A DScalarizeMaskedMemIntrin.cpp106 adjustForEndian(const DataLayout & DL,unsigned VectorWidth,unsigned Idx) adjustForEndian() argument
173 unsigned VectorWidth = cast<FixedVectorType>(VecType)->getNumElements(); scalarizeMaskedLoad() local
308 unsigned VectorWidth = cast<FixedVectorType>(VecType)->getNumElements(); scalarizeMaskedStore() local
425 unsigned VectorWidth = VecType->getNumElements(); scalarizeMaskedGather() local
555 unsigned VectorWidth = SrcFVTy->getNumElements(); scalarizeMaskedScatter() local
643 unsigned VectorWidth = VecType->getNumElements(); scalarizeMaskedExpandLoad() local
780 unsigned VectorWidth = VecType->getNumElements(); scalarizeMaskedCompressStore() local
885 unsigned VectorWidth = AddrType->getNumElements(); scalarizeMaskedVectorHistogram() local
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/llvm-project/llvm/lib/Target/ARM/
H A DMVETailPredication.cpp210 if (VectorWidth != 2 && VectorWidth != 4 && VectorWidth != 8 && in IsSafeActiveMask() local
380 unsigned VectorWidth = InsertVCTPIntrinsic() local
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/llvm-project/polly/lib/Transform/
H A DScheduleOptimizer.cpp383 int VectorWidth) { in isolateFullPartialTiles() argument
413 isl::schedule_node Node, unsigned DimToVectorize, int VectorWidth) { in prevectSchedBand() argument
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H A DScheduleTreeTransform.cpp547 static isl::set addExtentConstraints(isl::set Set, int VectorWidth) { in addExtentConstraints() argument
1115 int VectorWidth) { in getPartialTilePrefixes() argument
/llvm-project/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp1935 unsigned VectorWidth = addConstantComments() local
1956 unsigned VectorWidth = addConstantComments() local
H A DX86InterleavedAccess.cpp610 int Lane = (VectorWidth / 128 > 0) ? VectorWidth / 128 : 1; in group2Shuffle() local
/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp2696 extractSubVector(SDValue Vec,unsigned IdxVal,SelectionDAG & DAG,const SDLoc & DL,unsigned VectorWidth) extractSubVector() argument
/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DIRTranslator.cpp1589 unsigned VectorWidth = 0; translateGetElementPtr() local
/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp6040 if (unsigned VectorWidth = getContext().BuiltinInfo.getRequiredVectorWidth(BuiltinID)) EmitBuiltinExpr() local