/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.cpp | 248 ScaleVectorOffset(MCInst & Inst,unsigned OpNo,unsigned VectorSize,MCContext & Ctx) ScaleVectorOffset() argument 272 unsigned VectorSize = HRI.getRegSizeInBits(Hexagon::HvxVRRegClass) / 8; HexagonProcessInstruction() local [all...] |
H A D | HexagonInstrInfo.cpp | 2809 unsigned VectorSize = TRI->getSpillSize(Hexagon::HvxVRRegClass); isValidOffset() local
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/llvm-project/clang/lib/CodeGen/ |
H A D | ABIInfo.cpp | 278 isLegalVectorType(CharUnits VectorSize,llvm::Type * EltTy,unsigned NumElts) const isLegalVectorType() argument
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H A D | CGBuiltin.cpp | 7473 int VectorSize = 0; LookupNeonLLVMIntrinsic() local
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/llvm-project/llvm/lib/Target/X86/ |
H A D | X86InterleavedAccess.cpp | 438 int VectorSize = VT.getSizeInBits(); createShuffleStride() local 451 int VectorSize = VT.getSizeInBits(); setGroupSize() local
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/llvm-project/clang/lib/CodeGen/Targets/ |
H A D | ARM.cpp | 703 isLegalVectorType(CharUnits VectorSize,llvm::Type * EltTy,unsigned NumElts) const isLegalVectorType() argument
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H A D | AArch64.cpp | 506 isLegalVectorType(CharUnits VectorSize,llvm::Type * EltTy,unsigned NumElts) const isLegalVectorType() argument
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/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPULibFunc.h | 295 unsigned char VectorSize = 1; member
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/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | LegalizerInfo.h | 966 widenVectorEltsToVectorMinSize(unsigned TypeIdx,unsigned VectorSize) widenVectorEltsToVectorMinSize() argument
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/llvm-project/clang/utils/TableGen/ |
H A D | NeonEmitter.cpp | 1601 int64_t VectorSize = cast<IntInit>(Expr->getArg(0))->getValue(); emitDagShuffle() local
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/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | SROA.cpp | 2230 unsigned VectorSize = DL.getTypeSizeInBits(VTy).getFixedValue(); createAndCheckVectorTypesForPromotion() local
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/llvm-project/clang/lib/Sema/ |
H A D | SemaDeclAttr.cpp | 4312 llvm::APInt VectorSize(64, 0); AddModeAttr() local
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H A D | TreeTransform.h | 16094 IntegerLiteral *VectorSize RebuildExtVectorType() local
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