Home
last modified time | relevance | path

Searched defs:VecRegSize (Results 1 – 4 of 4) sorted by relevance

/llvm-project/llvm/lib/Transforms/Vectorize/
H A DLoadStoreVectorizer.cpp1355 unsigned VecRegSize = TTI.getLoadStoreVecRegBitWidth(AS); collectEquivalenceClasses() local
/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp2182 TypeSize VecRegSize = TypeSize::getScalable(RISCV::RVVBitsPerBlock); Select() local
H A DRISCVISelLowering.cpp10138 TypeSize VecRegSize = TypeSize::getScalable(RISCV::RVVBitsPerBlock); lowerINSERT_SUBVECTOR() local
/llvm-project/clang/lib/CodeGen/
H A DCGOpenMPRuntime.cpp10637 unsigned VecRegSize; emitX86DeclareSimdFunction() member
10844 emitAArch64DeclareSimdFunction(CodeGenModule & CGM,const FunctionDecl * FD,unsigned UserVLEN,ArrayRef<ParamAttrTy> ParamAttrs,OMPDeclareSimdDeclAttr::BranchStateTy State,StringRef MangledName,char ISA,unsigned VecRegSize,llvm::Function * Fn,SourceLocation SLoc) emitAArch64DeclareSimdFunction() argument