/llvm-project/llvm/unittests/Transforms/IPO/ |
H A D | WholeProgramDevirt.cpp | 17 VTableBits VT1; in TEST() local 62 VTableBits VT1; in TEST() local
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/llvm-project/llvm/include/llvm/IR/ |
H A D | LegacyPassNameParser.h | 89 static int ValCompare(const PassNameParser::OptionInfo *VT1, in ValCompare()
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/llvm-project/clang/test/SemaCXX/ |
H A D | attr-mode-tmpl.cpp | 28 …typedef T __attribute__((mode(V2SI))) VT1; // expected-error{{mode attribute only supported for in… in CheckPrimitiveTypes() typedef
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/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelLowering.cpp | 205 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree() argument 221 if (!getHasAlu32() || !VT1.isInteger() || !VT2.isInteger()) in isZExtFree() argument 230 if (Val.getOpcode() == ISD::LOAD && VT1.isSimple() && VT2.isSimple()) { in isZExtFree() local
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/llvm-project/libc/include/llvm-libc-macros/linux/ |
H A D | termios-macros.h | 65 #define VT1 0040000 // Vertical-tab delay type 1 macro
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/llvm-project/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.cpp | 1394 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree() argument 1406 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree() argument
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/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 2509 CreateStackTemporary(EVT VT1,EVT VT2) CreateStackTemporary() argument 10325 getVTList(EVT VT1,EVT VT2) getVTList() argument 10343 getVTList(EVT VT1,EVT VT2,EVT VT3) getVTList() argument 10363 getVTList(EVT VT1,EVT VT2,EVT VT3,EVT VT4) getVTList() argument 10587 SelectNodeTo(SDNode * N,unsigned MachineOpc,EVT VT1,EVT VT2,ArrayRef<SDValue> Ops) SelectNodeTo() argument 10593 SelectNodeTo(SDNode * N,unsigned MachineOpc,EVT VT1,EVT VT2) SelectNodeTo() argument 10599 SelectNodeTo(SDNode * N,unsigned MachineOpc,EVT VT1,EVT VT2,EVT VT3,ArrayRef<SDValue> Ops) SelectNodeTo() argument 10606 SelectNodeTo(SDNode * N,unsigned MachineOpc,EVT VT1,EVT VT2,SDValue Op1,SDValue Op2) SelectNodeTo() argument 10794 getMachineNode(unsigned Opcode,const SDLoc & dl,EVT VT1,EVT VT2,SDValue Op1,SDValue Op2) getMachineNode() argument 10802 getMachineNode(unsigned Opcode,const SDLoc & dl,EVT VT1,EVT VT2,SDValue Op1,SDValue Op2,SDValue Op3) getMachineNode() argument 10810 getMachineNode(unsigned Opcode,const SDLoc & dl,EVT VT1,EVT VT2,ArrayRef<SDValue> Ops) getMachineNode() argument 10817 getMachineNode(unsigned Opcode,const SDLoc & dl,EVT VT1,EVT VT2,EVT VT3,SDValue Op1,SDValue Op2) getMachineNode() argument 10825 getMachineNode(unsigned Opcode,const SDLoc & dl,EVT VT1,EVT VT2,EVT VT3,SDValue Op1,SDValue Op2,SDValue Op3) getMachineNode() argument 10834 getMachineNode(unsigned Opcode,const SDLoc & dl,EVT VT1,EVT VT2,EVT VT3,ArrayRef<SDValue> Ops) getMachineNode() argument 12327 EVT VT1 = N->getValueType(1); UnrollVectorOp() local [all...] |
H A D | LegalizeVectorTypes.cpp | 274 EVT VT1 = N->getValueType(1); ScalarizeVecRes_FFREXP() local 6014 EVT VT1 = getSetCCResultType(getSETCCOperandType(SETCC1)); WidenVSELECTMask() local [all...] |
H A D | LegalizeFloatTypes.cpp | 680 EVT VT1 = N->getValueType(1); SoftenFloatRes_FFREXP() local
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H A D | DAGCombiner.cpp | 10973 EVT VT0, VT1; foldABSToABD() local [all...] |
/llvm-project/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 178 if (!VT1.isSimple() || !VT1.isInteger() || in isZExtFree() local
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/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 75 for (MVT VT1 : MVT::fixedlen_vector_valuetypes()) { MipsSETargetLowering() local
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/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | TargetLowering.h | 1720 EVT VT1; getRegisterType() local 1753 EVT VT1; global() variable
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/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 2168 isTruncateFree(EVT VT1,EVT VT2) const isTruncateFree() argument
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/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 4156 EVT VT1 = Op.getValue(1).getValueType(); lowerADDSUBO_CARRY() local 15546 isTruncateFree(EVT VT1,EVT VT2) const isTruncateFree() argument 15590 isZExtFree(EVT VT1,EVT VT2) const isZExtFree() argument 15599 EVT VT1 = Val.getValueType(); isZExtFree() local 28417 EVT VT1; getRegisterTypeForCallingConv() local 28432 EVT VT1; getNumRegistersForCallingConv() local [all...] |
/llvm-project/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 34238 isTruncateFree(EVT VT1,EVT VT2) const isTruncateFree() argument 34251 isZExtFree(EVT VT1,EVT VT2) const isZExtFree() argument 34257 EVT VT1 = Val.getValueType(); isZExtFree() local 38511 MVT VT1 = V1.getSimpleValueType(); combineX86ShuffleChain() local [all...] |
/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 17398 isTruncateFree(EVT VT1,EVT VT2) const isTruncateFree() argument
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/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 19244 EVT VT1 = Val.getValueType(); isZExtFree() local
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