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Searched defs:VT (Results 1 – 25 of 208) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMachineFunctionInfo.cpp41 for (EVT VT : VTs) { in computeLegalValueVTs() local
114 for (auto VT : MFI.getParams()) in WebAssemblyFunctionInfo() local
116 for (auto VT : MFI.getResults()) in WebAssemblyFunctionInfo() local
144 for (auto VT : YamlMFI.Params) in initializeBaseYamlFields() local
146 for (auto VT : YamlMFI.Results) in initializeBaseYamlFields() local
H A DWebAssemblyMachineFunctionInfo.h81 void addParam(MVT VT) { Params.push_back(VT); } in addParam()
84 void addResult(MVT VT) { Results.push_back(VT); } in addResult()
93 void setLocal(size_t i, MVT VT) { Locals[i] = VT; } in setLocal()
94 void addLocal(MVT VT) { Locals.push_back(VT); } in addLocal()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetLowering.h432 getPreferredVectorAction(MVT VT) const { in getPreferredVectorAction()
468 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; } in isIntDivCheap()
471 virtual bool hasStandaloneRem(EVT VT) const { in hasStandaloneRem()
610 virtual unsigned getCustomCtpopCost(EVT VT, ISD::CondCode Cond) const { in getCustomCtpopCost()
626 virtual bool hasBitPreservingFPLogic(EVT VT) const { in hasBitPreservingFPLogic()
655 virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const { in convertSetCCLogicToBitwiseLogic()
664 MVT VT = MVT::getIntegerVT(NumBits); in hasFastEqualityCompare() local
768 virtual bool preferIncOfAddToSubOfNot(EVT VT) const { in preferIncOfAddToSubOfNot()
795 virtual bool enableAggressiveFMAFusion(EVT VT) const { in enableAggressiveFMAFusion()
868 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { in getRepRegClassFor()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp603 MVT VT = Node->getSimpleValueType(0); in Promote() local
640 MVT VT = Node->getOperand(IsStrict ? 1 : 0).getSimpleValueType(); in PromoteINT_TO_FP() local
678 MVT VT = Node->getSimpleValueType(0); in PromoteFP_TO_INT() local
913 EVT VT = Node->getValueType(0); in ExpandSELECT() local
973 EVT VT = Node->getValueType(0); in ExpandSEXTINREG() local
995 EVT VT = Node->getValueType(0); in ExpandANY_EXTEND_VECTOR_INREG() local
1030 EVT VT = Node->getValueType(0); in ExpandSIGN_EXTEND_VECTOR_INREG() local
1054 EVT VT = Node->getValueType(0); in ExpandZERO_EXTEND_VECTOR_INREG() local
1091 static void createBSWAPShuffleMask(EVT VT, SmallVectorImpl<int> &ShuffleMask) { in createBSWAPShuffleMask()
1099 EVT VT = Node->getValueType(0); in ExpandBSWAP() local
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H A DResourcePriorityQueue.cpp97 MVT VT = ScegN->getSimpleValueType(i); in numberRCValPredInSU() local
135 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU() local
331 MVT VT = SU->getNode()->getSimpleValueType(i); in rawRegPressureDelta() local
340 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in rawRegPressureDelta() local
479 MVT VT = ScegN->getSimpleValueType(i); in scheduledNode() local
490 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in scheduledNode() local
H A DSelectionDAG.cpp124 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType()
931 EVT VT = N->getValueType(0); in VerifySDNode() local
1007 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
1242 SDValue SelectionDAG::getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT) { in getFPExtendOrRound()
1250 const SDLoc &DL, EVT VT) { in getStrictFPExtendOrRound()
1262 SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getAnyExtOrTrunc()
1268 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getSExtOrTrunc()
1274 SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) { in getZExtOrTrunc()
1280 SDValue SelectionDAG::getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, in getBoolExtOrTrunc()
1289 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) { in getZeroExtendInReg()
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H A DDAGCombiner.cpp249 for (MVT VT : MVT::all_valuetypes()) in DAGCombiner() local
764 bool hasOperation(unsigned Opcode, EVT VT) { in hasOperation()
783 bool isTypeLegal(const EVT &VT) { in isTypeLegal()
1038 EVT VT = LoadStore->getMemoryVT(); in reassociationCanBreakAddressingModePattern() local
1058 EVT VT = N0.getValueType(); in reassociateOpsCommutative() local
1195 EVT VT = Load->getValueType(0); in ReplaceLoadWithPromotedLoad() local
1282 EVT VT = Op.getValueType(); in PromoteIntBinOp() local
1350 EVT VT = Op.getValueType(); in PromoteIntShiftOp() local
1399 EVT VT = Op.getValueType(); in PromoteExtend() local
1430 EVT VT = Op.getValueType(); in PromoteLoad() local
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H A DLegalizeTypes.h62 TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const { in getTypeAction()
67 bool isTypeLegal(EVT VT) const { in isTypeLegal()
72 bool isSimpleLegalType(EVT VT) const { in isSimpleLegalType()
76 EVT getSetCCResultType(EVT VT) const { in getSetCCResultType()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp233 static MVT scaleVectorType(MVT VT) { in scaleVectorType()
261 static void genShuffleBland(MVT VT, ArrayRef<int> Mask, in genShuffleBland()
291 static void reorderSubVector(MVT VT, SmallVectorImpl<Value *> &TransposedMatrix, in reorderSubVector()
331 MVT VT = MVT::v8i16; in interleave8bitStride4VF8() local
371 MVT VT = MVT::getVectorVT(MVT::i8, NumOfElm); in interleave8bitStride4() local
440 static void createShuffleStride(MVT VT, int Stride, in createShuffleStride()
454 static void setGroupSize(MVT VT, SmallVectorImpl<int> &SizeInfo) { in setGroupSize()
477 static void DecodePALIGNRMask(MVT VT, unsigned Imm, in DecodePALIGNRMask()
562 MVT VT = MVT::getVT(Shuffles[0]->getType()); in deinterleave8bitStride3() local
610 static void group2Shuffle(MVT VT, SmallVectorImpl<int> &Mask, in group2Shuffle()
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H A DX86FastISel.cpp296 bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) { in isTypeLegal()
322 bool X86FastISel::X86FastEmitLoad(MVT VT, X86AddressMode &AM, in X86FastEmitLoad()
487 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM, in X86FastEmitStore()
660 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val, in X86FastEmitStore()
1150 MVT VT; in X86SelectStore() local
1339 MVT VT; in X86SelectLoad() local
1358 static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) { in X86ChooseCmpOpcode()
1385 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) { in X86ChooseCmpImmediateOpcode()
1412 bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1, EVT VT, in X86FastEmitCompare()
1448 MVT VT; in X86SelectCmp() local
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H A DX86ISelLowering.cpp188 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering() local
819 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { in X86TargetLowering() local
2187 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv()
2347 EVT VT, unsigned, Align Alignment, MachineMemOperand::Flags Flags, in allowsMisalignedMemoryAccesses()
2918 EVT X86TargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT, in getTypeForExtReturn()
3872 EVT VT = getPointerTy(DAG.getDataLayout()); in EmitTailCallLoadRetAddr() local
3901 static SDValue getMOVL(SelectionDAG &DAG, const SDLoc &dl, MVT VT, SDValue V1, in getMOVL()
5178 MVT VT = MVT::getVT(I.getArgOperand(1)->getType()); in getTgtMemIntrinsic() local
5227 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT, in isFPImmLegal()
5251 EVT VT = Load->getValueType(0); in shouldReduceLoadWidth() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp473 MVT VT) { in getOUTLINE_ATOMIC()
549 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { in getSYNC()
717 for (MVT VT : MVT::fp_valuetypes()) { in initActions() local
726 for (MVT VT : MVT::all_valuetypes()) { in initActions() local
1069 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, in getVectorTypeBreakdownMVT()
1365 MVT VT = (MVT::SimpleValueType) i; in computeRegisterProperties() local
1504 EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdown()
1631 EVT VT = ValueVTs[j]; in GetReturnInfo() local
1679 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, in allowsMemoryAccessForAlignment()
1699 LLVMContext &Context, const DataLayout &DL, EVT VT, in allowsMemoryAccessForAlignment()
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H A DCallingConvLower.cpp108 MVT VT = Outs[i].VT; in CheckReturn() local
122 MVT VT = Outs[i].VT; in AnalyzeReturn() local
170 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
183 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { in AnalyzeCallResult()
198 static bool isValueTypeInRegForCC(CallingConv::ID CC, MVT VT) { in isValueTypeInRegForCC()
207 MVT VT, CCAssignFn Fn) { in getRemainingRegParmsForType()
H A DValueTypes.cpp38 EVT VT; in getExtendedIntegerVT() local
44 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, in getExtendedVectorVT()
53 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT, ElementCount EC) { in getExtendedVectorVT()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DMachineValueType.h1044 bool knownBitsGT(MVT VT) const { in knownBitsGT()
1050 bool knownBitsGE(MVT VT) const { in knownBitsGE()
1055 bool knownBitsLT(MVT VT) const { in knownBitsLT()
1061 bool knownBitsLE(MVT VT) const { in knownBitsLE()
1066 bool bitsGT(MVT VT) const { in bitsGT()
1073 bool bitsGE(MVT VT) const { in bitsGE()
1080 bool bitsLT(MVT VT) const { in bitsLT()
1087 bool bitsLE(MVT VT) const { in bitsLE()
1129 static MVT getVectorVT(MVT VT, unsigned NumElements) { in getVectorVT()
1252 static MVT getScalableVectorVT(MVT VT, unsigned NumElements) { in getScalableVectorVT()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp129 static inline EVT getPackedSVEVectorVT(EVT VT) { in getPackedSVEVectorVT()
169 static inline EVT getPromotedVTForPredicate(EVT VT) { in getPromotedVTForPredicate()
191 static inline bool isPackedVectorType(EVT VT, SelectionDAG &DAG) { in isPackedVectorType()
308 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) in AArch64TargetLowering() local
312 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) in AArch64TargetLowering() local
513 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { in AArch64TargetLowering() local
535 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { in AArch64TargetLowering() local
822 for (MVT VT : MVT::fp_valuetypes()) { in AArch64TargetLowering() local
828 for (MVT VT : MVT::integer_valuetypes()) in AArch64TargetLowering() local
1069 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { in AArch64TargetLowering() local
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H A DAArch64ISelDAGToDAG.cpp1250 EVT VT = N->getValueType(0); in SelectTable() local
1272 EVT VT = LD->getMemoryVT(); in tryIndexedLoad() local
1372 EVT VT = N->getValueType(0); in SelectLoad() local
1401 EVT VT = N->getValueType(0); in SelectPostLoad() local
1459 EVT VT = N->getValueType(0); in SelectPredicatedLoad() local
1490 EVT VT = N->getOperand(2)->getValueType(0); in SelectStore() local
1552 EVT VT = N->getOperand(2)->getValueType(0); in SelectPostStore() local
1580 EVT VT = V64Reg.getValueType(); in operator ()() local
1596 EVT VT = V128Reg.getValueType(); in NarrowVector() local
1608 EVT VT = N->getValueType(0); in SelectLoadLane() local
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H A DAArch64FastISel.cpp318 static unsigned getImplicitScaleFactor(MVT VT) { in getImplicitScaleFactor()
370 unsigned AArch64FastISel::materializeInt(const ConstantInt *CI, MVT VT) { in materializeInt()
387 unsigned AArch64FastISel::materializeFP(const ConstantFP *CFP, MVT VT) { in materializeFP()
516 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() local
537 MVT VT; in fastMaterializeFloatZero() local
958 bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
982 bool AArch64FastISel::isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed) { in isTypeSupported()
1005 bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) { in simplifyAddress()
1453 MVT VT = EVT.getSimpleVT(); in emitCmp() local
1525 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, int64_t Imm) { in emitAdd_ri_()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp111 auto addRegClassForRVV = [this](MVT VT) { in RISCVTargetLowering()
127 for (MVT VT : BoolVecVTs) in RISCVTargetLowering() local
129 for (MVT VT : IntVecVTs) in RISCVTargetLowering() local
133 for (MVT VT : F16VecVTs) in RISCVTargetLowering() local
137 for (MVT VT : F32VecVTs) in RISCVTargetLowering() local
141 for (MVT VT : F64VecVTs) in RISCVTargetLowering() local
145 auto addRegClassForFixedVectors = [this](MVT VT) { in RISCVTargetLowering()
151 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) in RISCVTargetLowering() local
155 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) in RISCVTargetLowering() local
435 for (MVT VT : BoolVecVTs) { in RISCVTargetLowering() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp38 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType()
48 EVT VT = Op.getValueType(); in numBitsUnsigned() local
54 EVT VT = Op.getValueType(); in numBitsSigned() local
122 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
128 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
148 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) { in AMDGPUTargetLowering() local
358 for (MVT VT : ScalarIntVTs) { in AMDGPUTargetLowering() local
418 for (MVT VT : VectorIntTypes) { in AMDGPUTargetLowering() local
460 for (MVT VT : FloatVectorTypes) { in AMDGPUTargetLowering() local
619 static bool opMustUseVOP3Encoding(const SDNode *N, MVT VT) { in opMustUseVOP3Encoding()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMFastISel.cpp392 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) { in ARMMoveToFPReg()
402 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) { in ARMMoveToIntReg()
415 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) { in ARMMaterializeFP()
454 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) { in ARMMaterializeInt()
523 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) { in ARMMaterializeGV()
631 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() local
649 MVT VT; in fastMaterializeAlloca() local
673 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
685 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { in isLoadTypeLegal()
802 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) { in ARMSimplifyAddress()
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H A DARMISelLowering.cpp157 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, in addTypeForNEON()
226 void ARMTargetLowering::addDRTypeForNEON(MVT VT) { in addDRTypeForNEON()
231 void ARMTargetLowering::addQRTypeForNEON(MVT VT) { in addQRTypeForNEON()
236 void ARMTargetLowering::setAllExpand(MVT VT) { in setAllExpand()
259 for (auto VT : IntTypes) { in addMVEVectorTypes() local
325 for (auto VT : FloatTypes) { in addMVEVectorTypes() local
393 for (auto VT : LongTypes) { in addMVEVectorTypes() local
437 for (auto VT : pTypes) { in addMVEVectorTypes() local
766 for (MVT VT : MVT::fixedlen_vector_valuetypes()) { in ARMTargetLowering() local
970 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) { in ARMTargetLowering() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp59 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
68 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
134 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
177 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
182 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
188 for (MVT VT : MVT::integer_valuetypes()) { in AVRTargetLowering() local
276 EVT VT = Op.getValueType(); in LowerShifts() local
423 EVT VT = Op->getValueType(0); in LowerDivRem() local
550 EVT VT = LHS.getValueType(); in getAVRCmp() local
879 EVT VT; in getPreIndexedAddressParts() local
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H A DAVRISelDAGToDAG.cpp107 MVT VT = cast<MemSDNode>(Op)->getMemoryVT().getSimpleVT(); in SelectAddr() local
124 MVT VT = LD->getMemoryVT().getSimpleVT(); in selectIndexedLoad() local
169 MVT VT) { in selectIndexedProgMemLoad()
340 EVT VT = ST->getValue().getValueType(); in select() local
368 MVT VT = LD->getMemoryVT().getSimpleVT(); in select() local
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp28 const EVT &VT) { in assign()
42 const EVT &VT) { in assignVRegs()
66 EVT VT = TLI.getValueType(DL, Args[ArgsIndex].Ty); in handle() local
139 const EVT &VT) { in assignValueToReg()
205 Register ArgsReg, const EVT &VT) { in handleSplit()
241 const EVT &VT) { in assignValueToReg()
316 Register ArgsReg, const EVT &VT) { in handleSplit()
347 static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT, in determineLocInfo()
647 EVT VT = TLI.getValueType(DL, Arg.Ty); in subTargetRegTypeForCallingConv() local

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