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Searched defs:VT (Results 1 – 25 of 128) sorted by relevance

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/minix3/external/bsd/llvm/dist/llvm/lib/Target/X86/Utils/
H A DX86ShuffleDecode.cpp66 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVSLDUPMask()
74 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVSHDUPMask()
82 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSLLDQMask()
96 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSRLDQMask()
111 void DecodePALIGNRMask(MVT VT, unsigned Imm, in DecodePALIGNRMask()
132 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSHUFMask()
148 void DecodePSHUFHWMask(MVT VT, unsigned Imm, in DecodePSHUFHWMask()
164 void DecodePSHUFLWMask(MVT VT, unsigned Imm, in DecodePSHUFLWMask()
183 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodeSHUFPMask()
205 void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeUNPCKHMask()
[all …]
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DCallingConvLower.cpp92 MVT VT = Outs[i].VT; in CheckReturn() local
106 MVT VT = Outs[i].VT; in AnalyzeReturn() local
160 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
174 void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { in AnalyzeCallResult()
184 static bool isValueTypeInRegForCC(CallingConv::ID CC, MVT VT) { in isValueTypeInRegForCC()
195 MVT VT, CCAssignFn Fn) { in getRemainingRegParmsForType()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.h47 EVT VT) const override { in isShuffleMaskLegal()
H A DMipsFastISel.cpp200 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) { in materializeInt()
238 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) { in materializeFP()
260 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) { in materializeGV()
293 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() local
331 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
343 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { in isLoadTypeLegal()
480 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr, in emitLoad()
523 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr, in emitStore()
562 MVT VT; in selectLoad() local
587 MVT VT; in selectStore() local
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/minix3/external/bsd/llvm/dist/llvm/include/llvm/Target/
H A DTargetLowering.h193 getPreferredVectorAction(EVT VT) const { in getPreferredVectorAction()
304 virtual bool enableAggressiveFMAFusion(EVT VT) const { in enableAggressiveFMAFusion()
354 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { in getRegClassFor()
367 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { in getRepRegClassFor()
374 virtual uint8_t getRepRegClassCostFor(MVT VT) const { in getRepRegClassCostFor()
381 bool isTypeLegal(EVT VT) const { in isTypeLegal()
397 LegalizeTypeAction getTypeAction(MVT VT) const { in getTypeAction()
401 void setTypeAction(MVT VT, LegalizeTypeAction Action) { in setTypeAction()
415 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const { in getTypeAction()
418 LegalizeTypeAction getTypeAction(MVT VT) const { in getTypeAction()
[all …]
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp381 MVT VT = Op.getSimpleValueType(); in Promote() local
414 EVT VT = Op.getOperand(0).getValueType(); in PromoteINT_TO_FP() local
450 EVT VT = Op.getValueType(); in PromoteFP_TO_INT() local
700 EVT VT = Op.getValueType(); in ExpandSELECT() local
754 EVT VT = Op.getValueType(); in ExpandSEXTINREG() local
777 EVT VT = Op.getValueType(); in ExpandANY_EXTEND_VECTOR_INREG() local
800 EVT VT = Op.getValueType(); in ExpandSIGN_EXTEND_VECTOR_INREG() local
824 EVT VT = Op.getValueType(); in ExpandZERO_EXTEND_VECTOR_INREG() local
853 EVT VT = Op.getValueType(); in ExpandBSWAP() local
884 EVT VT = Mask.getValueType(); in ExpandVSELECT() local
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H A DDAGCombiner.cpp408 bool isTypeLegal(const EVT &VT) { in isTypeLegal()
736 EVT VT = N0.getValueType(); in ReassociateOps() local
857 EVT VT = Load->getValueType(0); in ReplaceLoadWithPromotedLoad() local
948 EVT VT = Op.getValueType(); in PromoteIntBinOp() local
1006 EVT VT = Op.getValueType(); in PromoteIntShiftOp() local
1050 EVT VT = Op.getValueType(); in PromoteExtend() local
1079 EVT VT = Op.getValueType(); in PromoteLoad() local
1542 EVT VT = N0.getValueType(); in visitADD() local
1715 EVT VT = N0.getValueType(); in visitADDC() local
1772 static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT, in tryFoldToZero()
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H A DSelectionDAG.cpp78 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType()
721 EVT VT = N->getValueType(0); in VerifySDNode() local
790 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
981 SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) { in getAnyExtOrTrunc()
987 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) { in getSExtOrTrunc()
993 SDValue SelectionDAG::getZExtOrTrunc(SDValue Op, SDLoc DL, EVT VT) { in getZExtOrTrunc()
999 SDValue SelectionDAG::getBoolExtOrTrunc(SDValue Op, SDLoc SL, EVT VT, in getBoolExtOrTrunc()
1008 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, SDLoc DL, EVT VT) { in getZeroExtendInReg()
1020 SDValue SelectionDAG::getAnyExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) { in getAnyExtendVectorInReg()
1030 SDValue SelectionDAG::getSignExtendVectorInReg(SDValue Op, SDLoc DL, EVT VT) { in getSignExtendVectorInReg()
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H A DLegalizeTypes.h66 TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const { in getTypeAction()
71 bool isTypeLegal(EVT VT) const { in isTypeLegal()
75 EVT getSetCCResultType(EVT VT) const { in getSetCCResultType()
H A DLegalizeDAG.cpp208 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl, in ShuffleWithNarrowerEltType()
248 EVT VT = CFP->getValueType(0); in ExpandConstantFP() local
298 EVT VT = Val.getValueType(); in ExpandUnalignedStore() local
421 EVT VT = LD->getValueType(0); in ExpandUnalignedLoad() local
581 EVT VT = Tmp1.getValueType(); in PerformInsertVectorEltInMemory() local
716 MVT VT = Value.getSimpleValueType(); in LegalizeStoreOps() local
877 MVT VT = Node->getSimpleValueType(0); in LegalizeLoadOps() local
1499 EVT VT = Node->getValueType(0); in ExpandVectorBuildThroughStack() local
1611 EVT VT = Node->getValueType(0); in ExpandDYNAMIC_STACKALLOC() local
1660 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, in LegalizeSetCCCondCode()
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H A DResourcePriorityQueue.cpp96 MVT VT = ScegN->getSimpleValueType(i); in numberRCValPredInSU() local
134 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in numberRCValSuccInSU() local
334 MVT VT = SU->getNode()->getSimpleValueType(i); in rawRegPressureDelta() local
343 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in rawRegPressureDelta() local
486 MVT VT = ScegN->getSimpleValueType(i); in scheduledNode() local
497 MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo()); in scheduledNode() local
/minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType()
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) { in getEquivalentLoadRegType()
212 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
218 for (MVT VT : MVT::integer_vector_valuetypes()) { in AMDGPUTargetLowering() local
256 for (MVT VT : ScalarIntVTs) { in AMDGPUTargetLowering() local
305 for (MVT VT : VectorIntTypes) { in AMDGPUTargetLowering() local
350 for (MVT VT : FloatVectorTypes) { in AMDGPUTargetLowering() local
668 EVT VT = EVT::getEVT(InitTy); in LowerConstantInitializer() local
676 EVT VT = EVT::getEVT(CFP->getType()); in LowerConstantInitializer() local
706 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy)) in LowerConstantInitializer() local
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H A DR600ISelLowering.cpp125 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering() local
184 for (MVT VT : ScalarIntVTs) { in R600TargetLowering() local
636 EVT VT = Op.getValueType(); in LowerOperation() local
877 EVT VT = Op.getValueType(); in ReplaceNodeResults() local
886 EVT VT = Op.getValueType(); in ReplaceNodeResults() local
895 EVT VT = Op.getValueType(); in ReplaceNodeResults() local
904 EVT VT = Op.getValueType(); in ReplaceNodeResults() local
978 EVT VT = Op.getValueType(); in LowerTrig() local
1008 EVT VT = Op.getValueType(); in LowerSHLParts() local
1044 EVT VT = Op.getValueType(); in LowerSRXParts() local
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H A DSIISelLowering.cpp131 for (MVT VT : MVT::integer_valuetypes()) { in SITargetLowering() local
151 for (MVT VT : MVT::integer_vector_valuetypes()) { in SITargetLowering() local
156 for (MVT VT : MVT::fp_valuetypes()) in SITargetLowering() local
183 for (MVT VT : VecTypes) { in SITargetLowering() local
302 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT, in allowsMisalignedMemoryAccesses()
376 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, in LowerParameter()
524 MVT VT = VA.getLocVT(); in LowerFormalArguments() local
842 EVT VT = Op.getValueType(); in LowerINTRINSIC_WO_CHAIN() local
961 EVT VT = Op.getOperand(3).getValueType(); in LowerINTRINSIC_VOID() local
1042 EVT VT = Op.getValueType(); in LowerFastFDIV() local
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86FastISel.cpp296 bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) { in isTypeLegal()
324 bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, in X86FastEmitLoad()
385 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, bool ValIsKill, in X86FastEmitStore()
446 bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val, in X86FastEmitStore()
900 MVT VT; in X86SelectStore() local
1056 MVT VT; in X86SelectLoad() local
1074 static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) { in X86ChooseCmpOpcode()
1095 static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) { in X86ChooseCmpImmediateOpcode()
1112 EVT VT) { in X86FastEmitCompare()
1147 MVT VT; in X86SelectCmp() local
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H A DX86ISelLowering.cpp97 EVT VT = Vec.getValueType(); in ExtractSubVector() local
153 EVT VT = Vec.getValueType(); in InsertSubVector() local
191 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT, in Concat128BitVectors()
198 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT, in Concat256BitVectors()
303 for (MVT VT : MVT::integer_valuetypes()) in resetOperationActions() local
431 MVT VT = IntVTs[i]; in resetOperationActions() local
613 MVT VT = IntVTs[i]; in resetOperationActions() local
815 for (MVT VT : MVT::vector_valuetypes()) { in resetOperationActions() local
1010 MVT VT = (MVT::SimpleValueType)i; in resetOperationActions() local
1026 for (MVT VT : MVT::integer_vector_valuetypes()) { in resetOperationActions() local
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/minix3/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineValueType.h460 bool bitsGT(MVT VT) const { in bitsGT()
465 bool bitsGE(MVT VT) const { in bitsGE()
470 bool bitsLT(MVT VT) const { in bitsLT()
475 bool bitsLE(MVT VT) const { in bitsLE()
516 static MVT getVectorVT(MVT VT, unsigned NumElements) { in getVectorVT()
589 SimpleValueType VT; member
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.cpp119 EVT VT = Outs[i].VT; in AnalyzeReturn() local
187 EVT VT = Ins[i].VT; in AnalyzeCallResult() local
199 void Hexagon_CCState::AnalyzeCallResult(EVT VT, Hexagon_CCAssignFn Fn) { in AnalyzeCallResult()
/minix3/external/bsd/llvm/dist/llvm/lib/IR/
H A DValueTypes.cpp29 EVT VT; in getExtendedIntegerVT() local
35 EVT EVT::getExtendedVectorVT(LLVMContext &Context, EVT VT, in getExtendedVectorVT()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp942 EVT VT = N->getValueType(0); in SelectTable() local
964 EVT VT = LD->getMemoryVT(); in SelectIndexedLoad() local
1054 EVT VT = N->getValueType(0); in SelectLoad() local
1078 EVT VT = N->getValueType(0); in SelectPostLoad() local
1113 EVT VT = N->getOperand(2)->getValueType(0); in SelectStore() local
1132 EVT VT = N->getOperand(2)->getValueType(0); in SelectPostStore() local
1161 EVT VT = V64Reg.getValueType(); in operator ()() local
1176 EVT VT = V128Reg.getValueType(); in NarrowVector() local
1188 EVT VT = N->getValueType(0); in SelectLoadLane() local
1233 EVT VT = N->getValueType(0); in SelectPostLoadLane() local
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H A DAArch64ISelLowering.cpp407 for (MVT VT : MVT::fp_valuetypes()) { in AArch64TargetLowering() local
413 for (MVT VT : MVT::integer_valuetypes()) in AArch64TargetLowering() local
554 for (MVT VT : MVT::vector_valuetypes()) { in AArch64TargetLowering() local
590 void AArch64TargetLowering::addTypeForNEON(EVT VT, EVT PromotedBitwiseVT) { in addTypeForNEON()
659 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) { in addDRTypeForNEON()
664 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) { in addQRTypeForNEON()
700 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT(); in computeKnownBitsForTargetNode() local
720 MVT VT = Op.getOperand(1).getValueType().getSimpleVT(); in computeKnownBitsForTargetNode() local
1093 EVT VT = LHS.getValueType(); in emitComparison() local
1139 EVT VT = RHS.getValueType(); in getAArch64Cmp() local
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp90 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, in addTypeForNEON()
149 void ARMTargetLowering::addDRTypeForNEON(MVT VT) { in addDRTypeForNEON()
154 void ARMTargetLowering::addQRTypeForNEON(MVT VT) { in addQRTypeForNEON()
407 for (MVT VT : MVT::vector_valuetypes()) { in ARMTargetLowering() local
574 for (MVT VT : MVT::integer_vector_valuetypes()) { in ARMTargetLowering() local
623 for (MVT VT : MVT::fp_valuetypes()) { in ARMTargetLowering() local
634 for (MVT VT : MVT::integer_valuetypes()) in ARMTargetLowering() local
1184 EVT VT = N->getValueType(i); in getSchedulingPreference() local
3416 EVT VT = Op.getValueType(); in LowerXALUO() local
3443 EVT VT = Op.getValueType(); in LowerSELECT() local
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H A DARMFastISel.cpp447 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) { in ARMMoveToFPReg()
457 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) { in ARMMoveToIntReg()
470 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) { in ARMMaterializeFP()
513 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) { in ARMMaterializeInt()
583 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) { in ARMMaterializeGV()
694 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() local
712 MVT VT; in fastMaterializeAlloca() local
736 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
748 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { in isLoadTypeLegal()
864 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) { in ARMSimplifyAddress()
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp257 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal()
271 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { in isLoadTypeLegal()
398 void PPCFastISel::PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset, in PPCSimplifyAddress()
429 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, in PPCEmitLoad()
560 MVT VT; in SelectLoad() local
584 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) { in PPCEmitStore()
692 MVT VT; in SelectStore() local
1022 unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT, in PPCMoveToIntReg()
1846 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) { in PPCMaterializeFP()
1897 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) { in PPCMaterializeGV()
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp256 EVT VT = N.getValueType(); in SelectAddr() local
309 EVT VT = LD->getMemoryVT(); in isValidIndexedLoad() local
336 MVT VT = LD->getMemoryVT().getSimpleVT(); in SelectIndexedLoad() local
365 MVT VT = LD->getMemoryVT().getSimpleVT(); in SelectIndexedBinOp() local

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