1 /* $NetBSD: vega10_powertune.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef _VEGA10_POWERTUNE_H_ 26 #define _VEGA10_POWERTUNE_H_ 27 28 enum vega10_pt_config_reg_type { 29 VEGA10_CONFIGREG_MMR = 0, 30 VEGA10_CONFIGREG_SMC_IND, 31 VEGA10_CONFIGREG_DIDT_IND, 32 VEGA10_CONFIGREG_CACHE, 33 VEGA10_CONFIGREG_MAX 34 }; 35 36 enum vega10_didt_config_reg_type { 37 VEGA10_CONFIGREG_DIDT = 0, 38 VEGA10_CONFIGREG_GCCAC, 39 VEGA10_CONFIGREG_SECAC 40 }; 41 42 /* PowerContainment Features */ 43 #define POWERCONTAINMENT_FEATURE_DTE 0x00000001 44 #define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002 45 #define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004 46 47 struct vega10_pt_config_reg { 48 uint32_t offset; 49 uint32_t mask; 50 uint32_t shift; 51 uint32_t value; 52 enum vega10_pt_config_reg_type type; 53 }; 54 55 struct vega10_didt_config_reg { 56 uint32_t offset; 57 uint32_t mask; 58 uint32_t shift; 59 uint32_t value; 60 }; 61 62 struct vega10_pt_defaults { 63 uint8_t SviLoadLineEn; 64 uint8_t SviLoadLineVddC; 65 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 66 uint8_t TDC_MAWt; 67 uint8_t TdcWaterfallCtl; 68 uint8_t DTEAmbientTempBase; 69 }; 70 71 void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr); 72 int vega10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr); 73 int vega10_populate_pm_fuses(struct pp_hwmgr *hwmgr); 74 int vega10_enable_smc_cac(struct pp_hwmgr *hwmgr); 75 int vega10_enable_power_containment(struct pp_hwmgr *hwmgr); 76 int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n); 77 int vega10_power_control_set_level(struct pp_hwmgr *hwmgr); 78 int vega10_disable_power_containment(struct pp_hwmgr *hwmgr); 79 80 int vega10_enable_didt_config(struct pp_hwmgr *hwmgr); 81 int vega10_disable_didt_config(struct pp_hwmgr *hwmgr); 82 83 #endif /* _VEGA10_POWERTUNE_H_ */ 84 85