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Searched defs:V0 (Results 1 – 25 of 44) sorted by relevance

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/llvm-project/clang/test/CodeGen/
H A Dvector.cpp8 int4 test1(uint4 V0) { in test1()
16 int4 test2(float4 V0, float4 V1) { in test2()
H A Dext-vector.c282 int4 test15(uint4 V0) { in test15()
/llvm-project/clang/unittests/Analysis/FlowSensitive/
H A DDebugSupportTest.cpp49 auto *V0 = Ctx.atom(); in TEST() local
56 auto *V0 = Ctx.atom(); in TEST() local
63 auto *V0 = Ctx.atom(); in TEST() local
70 auto *V0 = Ctx.atom(); in TEST() local
77 auto V0 = Ctx.atom(); in TEST() local
87 auto V0 = Ctx.atom(); in TEST() local
/llvm-project/compiler-rt/lib/scudo/standalone/tests/
H A Dmutex_test.cpp25 T V0 = Data[0]; in write() local
35 T V0 = Data[0]; in tryWrite() local
/llvm-project/clang/test/CodeGenCXX/
H A Dptrauth-virtual-function.cpp142 class V0 : public virtual B0 { global() class
525 V0 V0; materializeConstructors() local
/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp198 SDValue V0 = N->getOperand(i + 1); in selectInlineAsm() local
383 SDNode *CSKYDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode()
/llvm-project/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp84 Register V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg() local
H A DMips16ISelDAGToDAG.cpp75 Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(MF); initGlobalBaseReg() local
/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVectorCombine.cpp560 /// cmp (ext0 V0, C), (ext1 V1, C) in foldExtExtBinop() local
542 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand(); foldExtExtCmp() local
586 Value *V0, *V1; foldExtractExtract() local
698 Value *V0, *V1; foldBitcastShuffle() local
932 Value *V0 = nullptr, *V1 = nullptr; scalarizeBinopOrCmp() local
1492 Value *V0, *V1; foldShuffleOfCastops() local
1597 Value *V0, *V1; foldShuffleOfShuffles() local
[all...]
/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp232 SDValue V0 = N->getOperand(i+1); tryInlineAsm() local
/llvm-project/llvm/unittests/ADT/
H A DBitmaskEnumTest.cpp27 enum Flags2 { V0 = 0, V1 = 1, V2 = 2, V3 = 4, V4 = 8 }; enumerator
H A DSTLExtrasTest.cpp876 const std::vector<int> V0 = {}, V1 = {1}, V2 = {1, 2}; TEST() local
886 const std::list<int> V0 = {}, V1 = {1}, V2 = {1, 2}; TEST() local
900 const std::list<int> V0 = {}, V1 = {1}, V2 = {1, 2}; TEST() local
922 const std::list<int> V0 = {}, V1 = {1}, V2 = {1, 2}; TEST() local
[all...]
H A DAPIntTest.cpp3356 __anon7fbec2830d02(const APInt &V0, const APInt &V1) TEST() argument
3370 for (unsigned V0 = 0; V0 < (1u << BitWidth); ++V0) { TEST() local
/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1853 createGPRPairNode(EVT VT,SDValue V0,SDValue V1) createGPRPairNode() argument
1864 createSRegPairNode(EVT VT,SDValue V0,SDValue V1) createSRegPairNode() argument
1875 createDRegPairNode(EVT VT,SDValue V0,SDValue V1) createDRegPairNode() argument
1886 createQRegPairNode(EVT VT,SDValue V0,SDValue V1) createQRegPairNode() argument
1897 createQuadSRegsNode(EVT VT,SDValue V0,SDValue V1,SDValue V2,SDValue V3) createQuadSRegsNode() argument
1912 createQuadDRegsNode(EVT VT,SDValue V0,SDValue V1,SDValue V2,SDValue V3) createQuadDRegsNode() argument
1927 createQuadQRegsNode(EVT VT,SDValue V0,SDValue V1,SDValue V2,SDValue V3) createQuadQRegsNode() argument
2318 SDValue V0 = N->getOperand(Vec0Idx + 0); SelectVST() local
2374 SDValue V0 = N->getOperand(Vec0Idx + 0); SelectVST() local
2493 SDValue V0 = N->getOperand(Vec0Idx + 0); SelectVLDSTLane() local
5780 SDValue V0 = N->getOperand(i+1); tryInlineAsm() local
[all...]
/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineAddSub.cpp391 Value *V0 = I->getOperand(0); in drillValueDownOneStep() local
469 Value *V0 = I->getOperand(0); in simplify() local
2279 Value *V0, *V1; visitSub() local
2962 Value *A0, *A1, *V0, *V1; visitFSub() local
[all...]
H A DInstCombineVectorOps.cpp84 Value *V0, *V1; in cheapToScalarize() local
2609 Value *V0 = Shuf.getOperand(0), *V1 = Shuf.getOperand(1); foldShuffleWithInsert() local
[all...]
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp5668 SDValue V0 = GetPromotedInteger(N->getOperand(0)); PromoteIntRes_VECTOR_SPLICE() local
5678 SDValue V0 = GetPromotedInteger(N->getOperand(0)); PromoteIntRes_VECTOR_INTERLEAVE_DEINTERLEAVE() local
5795 SDValue V0 = GetPromotedInteger(N->getOperand(0)); PromoteIntRes_VECTOR_REVERSE() local
5808 SDValue V0 = GetPromotedInteger(N->getOperand(0)); PromoteIntRes_VECTOR_SHUFFLE() local
5990 SDValue V0 = GetPromotedInteger(N->getOperand(0)); PromoteIntRes_INSERT_VECTOR_ELT() local
6018 SDValue V0 = GetPromotedInteger(N->getOperand(0)); PromoteIntOp_EXTRACT_VECTOR_ELT() local
6034 SDValue V0 = N->getOperand(0); PromoteIntOp_INSERT_SUBVECTOR() local
6047 SDValue V0 = GetPromotedInteger(N->getOperand(0)); PromoteIntOp_EXTRACT_SUBVECTOR() local
[all...]
/llvm-project/llvm/utils/PerfectShuffle/
H A DPerfectShuffle.cpp32 static inline unsigned short MakeMask(unsigned V0, unsigned V1, in MakeMask()
/llvm-project/llvm/lib/Transforms/Scalar/
H A DReassociate.cpp132 Value *V0 = I->getOperand(0); in XorOpnd() local
988 Value *V0 = Sub->getOperand(0); ShouldBreakUpSubtract() local
H A DConstraintElimination.cpp1667 Value *V0 = B.isConditionFact() ? B.Cond.Op0 : B.Inst->getOperand(0); eliminateConstraints() local
/llvm-project/llvm/unittests/Analysis/
H A DScalarEvolutionTest.cpp88 Value *V0 = new GlobalVariable(M, Ty, false, GlobalValue::ExternalLinkage, Init, "V0"); in TEST_F() local
564 const SCEV *V0 = SE.getSCEV(&*F.arg_begin()); TEST_F() local
[all...]
/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp1370 SDValue V0, V1; insertHvxSubvectorReg() local
1621 SDValue V0 = buildHvxVectorReg(A.take_front(Size/2), dl, SingleTy, DAG); LowerHvxBuildVector() local
1732 SDValue V0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfTy, LowerHvxConcatVectors() local
3530 SDValue V0 = Op.getOperand(0); combineConcatVectorsBeforeLegal() local
[all...]
H A DHexagonISelDAGToDAG.cpp2315 SDValue V0 = L0.Value; in balanceSubTree() local
2373 SDValue V0 = NewRoot.getOperand(0); balanceSubTree() local
[all...]
/llvm-project/llvm/lib/Analysis/
H A DVectorUtils.cpp976 Value *V0 = ResList[i], *V1 = ResList[i + 1]; concatenateVectors() local
/llvm-project/clang/lib/Headers/
H A Dhexagon_types.h2549 HVX_Vector V0(void) { return HEXAGON_HVX_GET_V0(data); }; V0() function
2558 HVX_Vect V0(HVX_Vector v) { return HVX_Vect(HEXAGON_HVX_PUT_V0(data, v)); }; V0() function

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