1 //===- ScheduleDAGInstrs.h - MachineInstr Scheduling ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file Implements the ScheduleDAGInstrs class, which implements scheduling 10 /// for a MachineInstr-based dependency graph. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_SCHEDULEDAGINSTRS_H 15 #define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H 16 17 #include "llvm/ADT/DenseMap.h" 18 #include "llvm/ADT/PointerIntPair.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/ADT/SparseMultiSet.h" 21 #include "llvm/ADT/identity.h" 22 #include "llvm/Analysis/AliasAnalysis.h" 23 #include "llvm/CodeGen/LiveRegUnits.h" 24 #include "llvm/CodeGen/MachineBasicBlock.h" 25 #include "llvm/CodeGen/ScheduleDAG.h" 26 #include "llvm/CodeGen/TargetRegisterInfo.h" 27 #include "llvm/CodeGen/TargetSchedule.h" 28 #include "llvm/MC/LaneBitmask.h" 29 #include <cassert> 30 #include <cstdint> 31 #include <list> 32 #include <string> 33 #include <utility> 34 #include <vector> 35 36 namespace llvm { 37 38 class AAResults; 39 class LiveIntervals; 40 class MachineFrameInfo; 41 class MachineFunction; 42 class MachineInstr; 43 class MachineLoopInfo; 44 class MachineOperand; 45 struct MCSchedClassDesc; 46 class PressureDiffs; 47 class PseudoSourceValue; 48 class RegPressureTracker; 49 class UndefValue; 50 class Value; 51 52 /// An individual mapping from virtual register number to SUnit. 53 struct VReg2SUnit { 54 unsigned VirtReg; 55 LaneBitmask LaneMask; 56 SUnit *SU; 57 58 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) 59 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} 60 61 unsigned getSparseSetIndex() const { 62 return Register::virtReg2Index(VirtReg); 63 } 64 }; 65 66 /// Mapping from virtual register to SUnit including an operand index. 67 struct VReg2SUnitOperIdx : public VReg2SUnit { 68 unsigned OperandIndex; 69 70 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, 71 unsigned OperandIndex, SUnit *SU) 72 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {} 73 }; 74 75 /// Record a physical register access. 76 /// For non-data-dependent uses, OpIdx == -1. 77 struct PhysRegSUOper { 78 SUnit *SU; 79 int OpIdx; 80 unsigned RegUnit; 81 82 PhysRegSUOper(SUnit *su, int op, unsigned R) 83 : SU(su), OpIdx(op), RegUnit(R) {} 84 85 unsigned getSparseSetIndex() const { return RegUnit; } 86 }; 87 88 /// Use a SparseMultiSet to track physical registers. Storage is only 89 /// allocated once for the pass. It can be cleared in constant time and reused 90 /// without any frees. 91 using RegUnit2SUnitsMap = 92 SparseMultiSet<PhysRegSUOper, identity<unsigned>, uint16_t>; 93 94 /// Track local uses of virtual registers. These uses are gathered by the DAG 95 /// builder and may be consulted by the scheduler to avoid iterating an entire 96 /// vreg use list. 97 using VReg2SUnitMultiMap = SparseMultiSet<VReg2SUnit, VirtReg2IndexFunctor>; 98 99 using VReg2SUnitOperIdxMultiMap = 100 SparseMultiSet<VReg2SUnitOperIdx, VirtReg2IndexFunctor>; 101 102 using ValueType = PointerUnion<const Value *, const PseudoSourceValue *>; 103 104 struct UnderlyingObject : PointerIntPair<ValueType, 1, bool> { 105 UnderlyingObject(ValueType V, bool MayAlias) 106 : PointerIntPair<ValueType, 1, bool>(V, MayAlias) {} 107 108 ValueType getValue() const { return getPointer(); } 109 bool mayAlias() const { return getInt(); } 110 }; 111 112 using UnderlyingObjectsVector = SmallVector<UnderlyingObject, 4>; 113 114 /// A ScheduleDAG for scheduling lists of MachineInstr. 115 class ScheduleDAGInstrs : public ScheduleDAG { 116 protected: 117 const MachineLoopInfo *MLI = nullptr; 118 const MachineFrameInfo &MFI; 119 120 /// TargetSchedModel provides an interface to the machine model. 121 TargetSchedModel SchedModel; 122 123 /// True if the DAG builder should remove kill flags (in preparation for 124 /// rescheduling). 125 bool RemoveKillFlags; 126 127 /// The standard DAG builder does not normally include terminators as DAG 128 /// nodes because it does not create the necessary dependencies to prevent 129 /// reordering. A specialized scheduler can override 130 /// TargetInstrInfo::isSchedulingBoundary then enable this flag to indicate 131 /// it has taken responsibility for scheduling the terminator correctly. 132 bool CanHandleTerminators = false; 133 134 /// Whether lane masks should get tracked. 135 bool TrackLaneMasks = false; 136 137 // State specific to the current scheduling region. 138 // ------------------------------------------------ 139 140 /// The block in which to insert instructions 141 MachineBasicBlock *BB = nullptr; 142 143 /// The beginning of the range to be scheduled. 144 MachineBasicBlock::iterator RegionBegin; 145 146 /// The end of the range to be scheduled. 147 MachineBasicBlock::iterator RegionEnd; 148 149 /// Instructions in this region (distance(RegionBegin, RegionEnd)). 150 unsigned NumRegionInstrs = 0; 151 152 /// After calling BuildSchedGraph, each machine instruction in the current 153 /// scheduling region is mapped to an SUnit. 154 DenseMap<MachineInstr*, SUnit*> MISUnitMap; 155 156 // State internal to DAG building. 157 // ------------------------------- 158 159 /// Defs, Uses - Remember where defs and uses of each register are as we 160 /// iterate upward through the instructions. This is allocated here instead 161 /// of inside BuildSchedGraph to avoid the need for it to be initialized and 162 /// destructed for each block. 163 RegUnit2SUnitsMap Defs; 164 RegUnit2SUnitsMap Uses; 165 166 /// Tracks the last instruction(s) in this region defining each virtual 167 /// register. There may be multiple current definitions for a register with 168 /// disjunct lanemasks. 169 VReg2SUnitMultiMap CurrentVRegDefs; 170 /// Tracks the last instructions in this region using each virtual register. 171 VReg2SUnitOperIdxMultiMap CurrentVRegUses; 172 173 mutable std::optional<BatchAAResults> AAForDep; 174 175 /// Remember a generic side-effecting instruction as we proceed. 176 /// No other SU ever gets scheduled around it (except in the special 177 /// case of a huge region that gets reduced). 178 SUnit *BarrierChain = nullptr; 179 180 public: 181 /// A list of SUnits, used in Value2SUsMap, during DAG construction. 182 /// Note: to gain speed it might be worth investigating an optimized 183 /// implementation of this data structure, such as a singly linked list 184 /// with a memory pool (SmallVector was tried but slow and SparseSet is not 185 /// applicable). 186 using SUList = std::list<SUnit *>; 187 188 /// The direction that should be used to dump the scheduled Sequence. 189 enum DumpDirection { 190 TopDown, 191 BottomUp, 192 Bidirectional, 193 NotSet, 194 }; 195 196 void setDumpDirection(DumpDirection D) { DumpDir = D; } 197 198 protected: 199 DumpDirection DumpDir = NotSet; 200 201 /// A map from ValueType to SUList, used during DAG construction, as 202 /// a means of remembering which SUs depend on which memory locations. 203 class Value2SUsMap; 204 205 /// Returns a (possibly null) pointer to the current BatchAAResults. 206 BatchAAResults *getAAForDep() const { 207 if (AAForDep.has_value()) 208 return &AAForDep.value(); 209 return nullptr; 210 } 211 212 /// Reduces maps in FIFO order, by N SUs. This is better than turning 213 /// every Nth memory SU into BarrierChain in buildSchedGraph(), since 214 /// it avoids unnecessary edges between seen SUs above the new BarrierChain, 215 /// and those below it. 216 void reduceHugeMemNodeMaps(Value2SUsMap &stores, 217 Value2SUsMap &loads, unsigned N); 218 219 /// Adds a chain edge between SUa and SUb, but only if both 220 /// AAResults and Target fail to deny the dependency. 221 void addChainDependency(SUnit *SUa, SUnit *SUb, 222 unsigned Latency = 0); 223 224 /// Adds dependencies as needed from all SUs in list to SU. 225 void addChainDependencies(SUnit *SU, SUList &SUs, unsigned Latency) { 226 for (SUnit *Entry : SUs) 227 addChainDependency(SU, Entry, Latency); 228 } 229 230 /// Adds dependencies as needed from all SUs in map, to SU. 231 void addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap); 232 233 /// Adds dependencies as needed to SU, from all SUs mapped to V. 234 void addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap, 235 ValueType V); 236 237 /// Adds barrier chain edges from all SUs in map, and then clear the map. 238 /// This is equivalent to insertBarrierChain(), but optimized for the common 239 /// case where the new BarrierChain (a global memory object) has a higher 240 /// NodeNum than all SUs in map. It is assumed BarrierChain has been set 241 /// before calling this. 242 void addBarrierChain(Value2SUsMap &map); 243 244 /// Inserts a barrier chain in a huge region, far below current SU. 245 /// Adds barrier chain edges from all SUs in map with higher NodeNums than 246 /// this new BarrierChain, and remove them from map. It is assumed 247 /// BarrierChain has been set before calling this. 248 void insertBarrierChain(Value2SUsMap &map); 249 250 /// For an unanalyzable memory access, this Value is used in maps. 251 UndefValue *UnknownValue; 252 253 254 /// Topo - A topological ordering for SUnits which permits fast IsReachable 255 /// and similar queries. 256 ScheduleDAGTopologicalSort Topo; 257 258 using DbgValueVector = 259 std::vector<std::pair<MachineInstr *, MachineInstr *>>; 260 /// Remember instruction that precedes DBG_VALUE. 261 /// These are generated by buildSchedGraph but persist so they can be 262 /// referenced when emitting the final schedule. 263 DbgValueVector DbgValues; 264 MachineInstr *FirstDbgValue = nullptr; 265 266 /// Set of live physical registers for updating kill flags. 267 LiveRegUnits LiveRegs; 268 269 public: 270 explicit ScheduleDAGInstrs(MachineFunction &mf, 271 const MachineLoopInfo *mli, 272 bool RemoveKillFlags = false); 273 274 ~ScheduleDAGInstrs() override = default; 275 276 /// Gets the machine model for instruction scheduling. 277 const TargetSchedModel *getSchedModel() const { return &SchedModel; } 278 279 /// Resolves and cache a resolved scheduling class for an SUnit. 280 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { 281 if (!SU->SchedClass && SchedModel.hasInstrSchedModel()) 282 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr()); 283 return SU->SchedClass; 284 } 285 286 /// IsReachable - Checks if SU is reachable from TargetSU. 287 bool IsReachable(SUnit *SU, SUnit *TargetSU) { 288 return Topo.IsReachable(SU, TargetSU); 289 } 290 291 /// Returns an iterator to the top of the current scheduling region. 292 MachineBasicBlock::iterator begin() const { return RegionBegin; } 293 294 /// Returns an iterator to the bottom of the current scheduling region. 295 MachineBasicBlock::iterator end() const { return RegionEnd; } 296 297 /// Creates a new SUnit and return a ptr to it. 298 SUnit *newSUnit(MachineInstr *MI); 299 300 /// Returns an existing SUnit for this MI, or nullptr. 301 SUnit *getSUnit(MachineInstr *MI) const; 302 303 /// If this method returns true, handling of the scheduling regions 304 /// themselves (in case of a scheduling boundary in MBB) will be done 305 /// beginning with the topmost region of MBB. 306 virtual bool doMBBSchedRegionsTopDown() const { return false; } 307 308 /// Prepares to perform scheduling in the given block. 309 virtual void startBlock(MachineBasicBlock *BB); 310 311 /// Cleans up after scheduling in the given block. 312 virtual void finishBlock(); 313 314 /// Initialize the DAG and common scheduler state for a new 315 /// scheduling region. This does not actually create the DAG, only clears 316 /// it. The scheduling driver may call BuildSchedGraph multiple times per 317 /// scheduling region. 318 virtual void enterRegion(MachineBasicBlock *bb, 319 MachineBasicBlock::iterator begin, 320 MachineBasicBlock::iterator end, 321 unsigned regioninstrs); 322 323 /// Called when the scheduler has finished scheduling the current region. 324 virtual void exitRegion(); 325 326 /// Builds SUnits for the current region. 327 /// If \p RPTracker is non-null, compute register pressure as a side effect. 328 /// The DAG builder is an efficient place to do it because it already visits 329 /// operands. 330 void buildSchedGraph(AAResults *AA, 331 RegPressureTracker *RPTracker = nullptr, 332 PressureDiffs *PDiffs = nullptr, 333 LiveIntervals *LIS = nullptr, 334 bool TrackLaneMasks = false); 335 336 /// Adds dependencies from instructions in the current list of 337 /// instructions being scheduled to scheduling barrier. We want to make sure 338 /// instructions which define registers that are either used by the 339 /// terminator or are live-out are properly scheduled. This is especially 340 /// important when the definition latency of the return value(s) are too 341 /// high to be hidden by the branch or when the liveout registers used by 342 /// instructions in the fallthrough block. 343 void addSchedBarrierDeps(); 344 345 /// Orders nodes according to selected style. 346 /// 347 /// Typically, a scheduling algorithm will implement schedule() without 348 /// overriding enterRegion() or exitRegion(). 349 virtual void schedule() = 0; 350 351 /// Allow targets to perform final scheduling actions at the level of the 352 /// whole MachineFunction. By default does nothing. 353 virtual void finalizeSchedule() {} 354 355 void dumpNode(const SUnit &SU) const override; 356 void dump() const override; 357 358 /// Returns a label for a DAG node that points to an instruction. 359 std::string getGraphNodeLabel(const SUnit *SU) const override; 360 361 /// Returns a label for the region of code covered by the DAG. 362 std::string getDAGName() const override; 363 364 /// Fixes register kill flags that scheduling has made invalid. 365 void fixupKills(MachineBasicBlock &MBB); 366 367 /// True if an edge can be added from PredSU to SuccSU without creating 368 /// a cycle. 369 bool canAddEdge(SUnit *SuccSU, SUnit *PredSU); 370 371 /// Add a DAG edge to the given SU with the given predecessor 372 /// dependence data. 373 /// 374 /// \returns true if the edge may be added without creating a cycle OR if an 375 /// equivalent edge already existed (false indicates failure). 376 bool addEdge(SUnit *SuccSU, const SDep &PredDep); 377 378 protected: 379 void initSUnits(); 380 void addPhysRegDataDeps(SUnit *SU, unsigned OperIdx); 381 void addPhysRegDeps(SUnit *SU, unsigned OperIdx); 382 void addVRegDefDeps(SUnit *SU, unsigned OperIdx); 383 void addVRegUseDeps(SUnit *SU, unsigned OperIdx); 384 385 /// Returns a mask for which lanes get read/written by the given (register) 386 /// machine operand. 387 LaneBitmask getLaneMaskForMO(const MachineOperand &MO) const; 388 389 /// Returns true if the def register in \p MO has no uses. 390 bool deadDefHasNoUse(const MachineOperand &MO); 391 }; 392 393 /// Creates a new SUnit and return a ptr to it. 394 inline SUnit *ScheduleDAGInstrs::newSUnit(MachineInstr *MI) { 395 #ifndef NDEBUG 396 const SUnit *Addr = SUnits.empty() ? nullptr : &SUnits[0]; 397 #endif 398 SUnits.emplace_back(MI, (unsigned)SUnits.size()); 399 assert((Addr == nullptr || Addr == &SUnits[0]) && 400 "SUnits std::vector reallocated on the fly!"); 401 return &SUnits.back(); 402 } 403 404 /// Returns an existing SUnit for this MI, or nullptr. 405 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const { 406 return MISUnitMap.lookup(MI); 407 } 408 409 } // end namespace llvm 410 411 #endif // LLVM_CODEGEN_SCHEDULEDAGINSTRS_H 412