1 /* $NetBSD: ti_otgreg.h,v 1.1 2019/10/27 16:31:26 jmcneill Exp $ */ 2 /* 3 * Copyright (c) 2013 Manuel Bouyer. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26 #define TI_OTG_NPORTS 2 27 /* USBSS registers */ 28 #define TIOTG_USBSS_OFFSET 0 29 #define TIOTG_USBSS_READ4(sc, reg) \ 30 bus_space_read_4(sc->sc_iot, sc->sc_ioh, (reg) + TIOTG_USBSS_OFFSET) 31 #define TIOTG_USBSS_WRITE4(sc, reg, val) \ 32 bus_space_write_4(sc->sc_iot, sc->sc_ioh, (reg) + TIOTG_USBSS_OFFSET, (val)) 33 34 #define USBSS_REVREG 0x00 35 #define USBSS_SYSCONFIG 0x10 36 #define USBSS_SYSCONFIG_USB0_OCP_EN_N 0x800 37 #define USBSS_SYSCONFIG_PHY0_UTMI_EN_N 0x400 38 #define USBSS_SYSCONFIG_USB1_OCP_EN_N 0x200 39 #define USBSS_SYSCONFIG_PHY1_UTMI_EN_N 0x100 40 #define USBSS_SYSCONFIG_STBYMODE_SHIFT 4 41 #define USBSS_SYSCONFIG_IDLEMODE_SHIFT 2 42 #define USBSS_SYSCONFIG_FREEEMU 0x002 43 #define USBSS_SYSCONFIG_SRESET 0x001 44 45 /* USB control registers */ 46 #define USB_CTRL_OFFSET(port) (0x1000 + (0x800 * (port))) 47 #define USB_PORT_SIZE 0x800 /* size of CTRL+PHY+CORE */ 48 #define TIOTG_USBC_READ4(sc, reg) \ 49 bus_space_read_4(sc->sc_ctrliot, sc->sc_ctrlioh, (reg)) 50 #define TIOTG_USBC_WRITE4(sc, reg, val) \ 51 bus_space_write_4(sc->sc_ctrliot, sc->sc_ctrlioh, (reg), (val)) 52 53 #define USBCTRL_REV 0x00 54 #define USBCTRL_CTRL 0x14 55 #define USBCTRL_STAT 0x18 56 #define USBCTRL_IRQ_STAT0 0x30 57 #define USBCTRL_IRQ_STAT0_RXSHIFT 16 58 #define USBCTRL_IRQ_STAT0_TXSHIFT 0 59 #define USBCTRL_IRQ_STAT1 0x34 60 #define USBCTRL_IRQ_STAT1_DRVVBUS (1 << 8) 61 #define USBCTRL_INTEN_SET0 0x38 62 #define USBCTRL_INTEN_SET1 0x3C 63 #define USBCTRL_INTEN_USB_ALL 0x1ff 64 #define USBCTRL_INTEN_USB_SOF (1 << 3) 65 #define USBCTRL_INTEN_CLR0 0x40 66 #define USBCTRL_INTEN_CLR1 0x44 67 #define USBCTRL_UTMI 0xE0 68 #define USBCTRL_UTMI_FSDATAEXT (1 << 1) 69 #define USBCTRL_MODE 0xE8 70 #define USBCTRL_MODE_IDDIG (1 << 8) 71 #define USBCTRL_MODE_IDDIGMUX (1 << 7) 72 73 #define USB_CORE_OFFSET 0x400 74 #define USB_CORE_SIZE 0x400 75