xref: /plan9-contrib/sys/src/nboot/zynq/fsbl.s (revision 529c1f209803c78c4f2cda11b13818a57f01c872) 
1#include "mem.h"
2
3#define Rb R10
4#define SET(R, V) MOVW $(V), R0 ; MOVW R0, (R)(Rb)
5#define RMW(r, m, v) MOVW (r)(Rb), R0; BIC $(m), R0; ORR $(v), R0; MOVW R0, (r)(Rb)
6
7TEXT _start(SB), $-4
8	WORD $0xea000006
9	MOVW $abort(SB), R15
10	MOVW $abort(SB), R15
11	MOVW $abort(SB), R15
12	MOVW $abort(SB), R15
13	MOVW $abort(SB), R15
14	MOVW $abort(SB), R15
15	MOVW $abort(SB), R15
16
17TEXT reloc(SB), $-4
18	MOVW $(1<<7|1<<6|0x13), R0
19	MOVW R0, CPSR
20	MOVW $STACKTOP, R13
21	MOVW $_start(SB), R0
22	MCR CpMMU, 0, R0, C(12), C(0)
23	MOVW $SLCR_BASE, Rb
24	SET(SLCR_UNLOCK, UNLOCK_KEY)
25	MOVW $0, R0
26	MCR 15, 0, R0, C(8), C(7), 0
27	MCR 15, 0, R0, C(7), C(5), 0
28	MCR 15, 0, R0, C(7), C(5), 6
29	MOVW $0xc5047a, R1
30	MCR 15, 0, R1, C(1), C(0), 0
31	DSB
32	ISB
33	CMP.S $0, R15
34	BL.LT reset(SB)
35
36	MOVW $0xf, R1
37	MOVW $0xffff0000, R3
38	MOVW $0xe58a1910, R0
39	MOVW R0, (R3)
40	MOVW $0xf57ff04f, R0
41	MOVW R0, 4(R3)
42	MOVW $0xf57ff06f, R0
43	MOVW R0, 8(R3)
44	MOVW $0xe28ef000, R0
45	MOVW R0, 12(R3)
46	MOVW $reset(SB), R14
47	DSB
48	ISB
49	MOVW R3, R15
50
51TEXT reset(SB), $-4
52	BL pllsetup(SB)
53	BL miosetup(SB)
54	BL ddrsetup(SB)
55	BL uartsetup(SB)
56	MOVW $SLCR_BASE, Rb
57	SET(SLCR_LOCK, LOCK_KEY)
58//	BL memtest(SB)
59	MOVW $setR12(SB), R12
60	BL main(SB)
61	B abort(SB)
62
63TEXT pllsetup(SB), $0
64	MOVW $SLCR_BASE, Rb
65
66	SET(ARM_PLL_CFG, ARM_PLL_CFG_VAL)
67	SET(DDR_PLL_CFG, DDR_PLL_CFG_VAL)
68	SET(IO_PLL_CFG, IO_PLL_CFG_VAL)
69
70	MOVW $(ARM_FDIV | PLL_BYPASS_FORCE), R0
71	MOVW R0, ARM_PLL_CTRL(Rb)
72	ORR $(PLL_RESET), R4
73	MOVW R4, ARM_PLL_CTRL(Rb)
74	MOVW R0, ARM_PLL_CTRL(Rb)
75
76	MOVW $(DDR_FDIV | PLL_BYPASS_FORCE), R0
77	MOVW R0, DDR_PLL_CTRL(Rb)
78	ORR $(PLL_RESET), R4
79	MOVW R4, DDR_PLL_CTRL(Rb)
80	MOVW R0, DDR_PLL_CTRL(Rb)
81
82	MOVW $(IO_FDIV | PLL_BYPASS_FORCE), R0
83	MOVW R0, IO_PLL_CTRL(Rb)
84	ORR $(PLL_RESET), R4
85	MOVW R4, IO_PLL_CTRL(Rb)
86	MOVW R0, IO_PLL_CTRL(Rb)
87
88_pllsetupl:
89	MOVW PLL_STATUS(Rb), R0
90	AND $7, R0
91	CMP.S $7, R0
92	BNE _pllsetupl
93
94	SET(ARM_PLL_CTRL, ARM_FDIV)
95	SET(DDR_PLL_CTRL, DDR_FDIV)
96	SET(IO_PLL_CTRL, IO_FDIV)
97
98	SET(ARM_CLK_CTRL, 0x1f << 24 | CPU_DIV << 8)
99	SET(UART_CLK_CTRL, UART_DIV << 8 | 3)
100	SET(DDR_CLK_CTRL, DDR_DIV3 << 20 | DDR_DIV2 << 26 | 3)
101	SET(DCI_CLK_CTRL, DCI_DIV0 << 8 | DCI_DIV1 << 20 | 1)
102	SET(GEM0_RCLK_CTRL, 1)
103	SET(GEM1_RCLK_CTRL, 0)
104	SET(GEM0_CLK_CTRL, ETH_DIV0 << 8 | ETH_DIV1 << 20 | 1)
105	SET(GEM1_CLK_CTRL, 0)
106	SET(GPIOB_CTRL, VREF_SW_EN)
107	SET(APER_CLK_CTRL, LQSPI_CLK_EN | GPIO_CLK_EN | UART0_CLK_EN | UART1_CLK_EN | I2C0_CLK_EN | SDIO1_CLK_EN | GEM0_CLK_EN | USB0_CLK_EN | USB1_CLK_EN | DMA_CLK_EN)
108	SET(SMC_CLK_CTRL, 0x3C20)
109	SET(LQSPI_CLK_CTRL, QSPI_DIV << 8 | 1)
110	SET(SDIO_CLK_CTRL, SDIO_DIV << 8 | 2)
111	SET(SPI_CLK_CTRL, 0x3F00)
112	SET(CAN_CLK_CTRL, 0x501900)
113	SET(PCAP_CLK_CTRL, PCAP_DIV << 8 | 1)
114	RET
115
116TEXT miosetup(SB), $0
117	MOVW $SLCR_BASE, Rb
118	SET(UART_RST_CTRL, 0xf)
119	SET(UART_RST_CTRL, 0)
120
121	MOVW $miodata(SB), R1
122	ADD $MIO_PIN_0, Rb, R2
123	MOVW $54, R3
124	BL copy(SB)
125
126	MOVW $0, R0
127	MOVW R0, MIO_MST_TRI0(Rb)
128	MOVW R0, MIO_MST_TRI1(Rb)
129	RET
130
131TEXT copy(SB), $0
132_copyl:
133	MOVW.P 4(R1), R0
134	MOVW.P R0, 4(R2)
135	SUB.S $1, R3
136	BNE _copyl
137	RET
138
139TEXT ddrsetup(SB), $0
140	MOVW $SLCR_BASE, Rb
141	RMW(DDRIOB_DCI_CTRL, DCI_RESET, DCI_RESET)
142	RMW(DDRIOB_DCI_CTRL, DCI_RESET, 0)
143	RMW(DDRIOB_DCI_CTRL, DDRIOB_DCI_CTRL_MASK, DCI_NREF | DCI_ENABLE | DCI_RESET)
144
145	MOVW $ddriob(SB), R1
146	ADD $DDRIOB_ADDR0, Rb, R2
147	MOVW $12, R3
148	BL copy(SB)
149
150	MOVW $ddrdata(SB), R1
151_ddrl1:
152	MOVW.P 4(R1), R2
153	ORR.S $0, R2
154	BEQ _ddrl2
155	MOVW.P 4(R1), R3
156	MOVW.P 4(R1), R4
157	AND R3, R4
158	MOVW (R2), R0
159	BIC R3, R0
160	ORR R4, R0
161	MOVW R0, (R2)
162	B _ddrl1
163_ddrl2:
164	MOVW DDRIOB_DCI_STATUS(Rb), R0
165	AND.S $(1<<13), R0
166	BEQ _ddrl2
167	MOVW $DDR_BASE, Rb
168	RMW(DDRC_CTRL, 0x1ffff, 0x81)
169_ddrl4:
170	MOVW DDR_MODE_STS(Rb), R0
171	AND.S $7, R0
172	BEQ _ddrl4
173
174	MOVW $MP_BASE, Rb
175	SET(FILTER_START, 0)
176	RET
177
178TEXT memtest(SB), $0
179	MOVW $0, R0
180	ADD $(1024 * 1024 * 10), R0, R1
181_testl:
182	MOVW R0, (R0)
183	ADD $4, R0
184	CMP.S R0, R1
185	BNE _testl
186	MOVW $0, R0
187_testl2:
188	MOVW (R0), R2
189	CMP.S R0, R2
190	BNE _no
191	ADD $4, R0
192	CMP.S R0, R1
193	BNE _testl2
194	MOVW $'.', R0
195	BL putc(SB)
196	RET
197_no:
198	MOVW $'!', R0
199	BL putc(SB)
200	RET
201
202TEXT uartsetup(SB), $0
203	MOVW $UART1_BASE, Rb
204	SET(UART_CTRL, 0x17)
205	SET(UART_MODE, 0x20)
206	SET(UART_SAMP, 15)
207	SET(UART_BAUD, 14)
208	RET
209
210TEXT putc(SB), $0
211	MOVW $UART1_BASE, Rb
212	CMP.S $10, R0
213	BNE _putcl
214	MOVW R0, R2
215	MOVW $13, R0
216	BL putc(SB)
217	MOVW R2, R0
218_putcl:
219	MOVW UART_STAT(Rb), R1
220	AND.S $0x10, R1
221	BNE _putcl
222	AND $0xFF, R0
223	MOVW R0, UART_DATA(Rb)
224	RET
225
226TEXT jump(SB), $-4
227	MOVW R0, R15
228
229TEXT abort(SB), $0
230	MOVW $'?', R0
231	BL putc(SB)
232_loop:
233	WFE
234	B _loop
235
236#define TRI 1
237#define LVCMOS18 (1<<9)
238#define LVCMOS25 (2<<9)
239#define LVCMOS33 (3<<9)
240#define HSTL (4<<9)
241#define PULLUP (1<<12)
242#define NORECV (1<<13)
243#define FAST (1<<8)
244#define MUX(a, b, c, d) ((a)<<1 | (b)<<2 | (c)<<3 | (d)<<5)
245
246#define NO (TRI | LVCMOS33)
247#define SPI (MUX(1, 0, 0, 0) | LVCMOS33)
248#define UART (MUX(0, 0, 0, 7) | LVCMOS33)
249#define SD (MUX(0, 0, 0, 4) | LVCMOS33)
250#define ETX (MUX(1, 0, 0, 0) | HSTL | NORECV | PULLUP)
251#define ERX (MUX(1, 0, 0, 0) | HSTL | TRI | PULLUP)
252#define USB (MUX(0, 1, 0, 0) | LVCMOS18)
253#define MDCLK (MUX(0, 0, 0, 4) | HSTL)
254#define MDDATA (MUX(0, 0, 0, 4) | HSTL)
255
256TEXT miodata(SB), $-4
257	WORD $NO // 0
258	WORD $SPI // 1
259	WORD $SPI // 2
260	WORD $SPI // 3
261	WORD $SPI // 4
262	WORD $SPI // 5
263	WORD $SPI // 6
264	WORD $NO // 7
265	WORD $UART // 8
266	WORD $(UART|TRI) // 9
267	WORD $SD // 10
268	WORD $SD // 11
269	WORD $SD // 12
270	WORD $SD // 13
271	WORD $SD // 14
272	WORD $SD // 15
273	WORD $ETX // 16
274	WORD $ETX // 17
275	WORD $ETX // 18
276	WORD $ETX // 19
277	WORD $ETX // 20
278	WORD $ETX // 21
279	WORD $ERX // 22
280	WORD $ERX // 23
281	WORD $ERX // 24
282	WORD $ERX // 25
283	WORD $ERX // 26
284	WORD $ERX // 27
285	WORD $USB // 28
286	WORD $USB // 29
287	WORD $USB // 30
288	WORD $USB // 31
289	WORD $USB // 32
290	WORD $USB // 33
291	WORD $USB // 34
292	WORD $USB // 35
293	WORD $USB // 36
294	WORD $USB // 37
295	WORD $USB // 38
296	WORD $USB // 39
297	WORD $USB // 40
298	WORD $USB // 41
299	WORD $USB // 42
300	WORD $USB // 43
301	WORD $USB // 44
302	WORD $USB // 45
303	WORD $USB // 46
304	WORD $USB // 47
305	WORD $USB // 48
306	WORD $USB // 49
307	WORD $USB // 50
308	WORD $USB // 51
309	WORD $MDCLK // 52
310	WORD $MDDATA // 53
311