| /llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 806 if (!TrueReg.isVirtual()) in simplifyCode() local
873 if (!TrueReg.isVirtual()) in simplifyCode() local
1222 Register TrueReg = simplifyCode() local
[all...] |
| H A D | PPCInstrInfo.cpp | 1522 canInsertSelect(const MachineBasicBlock & MBB,ArrayRef<MachineOperand> Cond,Register DstReg,Register TrueReg,Register FalseReg,int & CondCycles,int & TrueCycles,int & FalseCycles) const canInsertSelect() argument
1569 insertSelect(MachineBasicBlock & MBB,MachineBasicBlock::iterator MI,const DebugLoc & dl,Register DestReg,ArrayRef<MachineOperand> Cond,Register TrueReg,Register FalseReg) const insertSelect() argument
3254 selectReg(int64_t Imm1,int64_t Imm2,unsigned CompareOpc,unsigned TrueReg,unsigned FalseReg,unsigned CRSubReg) selectReg() argument
3413 Register TrueReg = TRI->lookThruCopyLike(Reg, MRI); getForwardingDefMI() local
4607 Register TrueReg = CompareUseMI.getOperand(1).getReg(); simplifyToLI() local
[all...] |
| /llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 552 canInsertSelect(const MachineBasicBlock & MBB,ArrayRef<MachineOperand> Pred,Register DstReg,Register TrueReg,Register FalseReg,int & CondCycles,int & TrueCycles,int & FalseCycles) const canInsertSelect() argument
588 insertSelect(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,Register DstReg,ArrayRef<MachineOperand> Pred,Register TrueReg,Register FalseReg) const insertSelect() argument
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| H A D | SystemZISelLowering.cpp | 8260 Register TrueReg = MI->getOperand(1).getReg(); createPHIsForSelects() local
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| /llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 936 canInsertSelect(const MachineBasicBlock & MBB,ArrayRef<MachineOperand> Cond,Register DstReg,Register TrueReg,Register FalseReg,int & CondCycles,int & TrueCycles,int & FalseCycles) canInsertSelect() argument
960 insertSelect(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,Register DstReg,ArrayRef<MachineOperand> Cond,Register TrueReg,Register FalseReg) insertSelect() argument
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| /llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFastISel.cpp | 921 Register TrueReg = getRegForValue(Select->getTrueValue()); selectSelect() local
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| H A D | WebAssemblyISelLowering.cpp | 503 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; LowerFPToInt() local
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 789 auto TrueReg = MIB.getReg(2); in selectSelect() local
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| H A D | ARMBaseInstrInfo.cpp | 2356 MachineOperand TrueReg = MI.getOperand(Invert ? 1 : 2); optimizeSelect() local
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| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 1231 insertVectorSelect(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,Register DstReg,ArrayRef<MachineOperand> Cond,Register TrueReg,Register FalseReg) const insertVectorSelect() argument
3224 canInsertSelect(const MachineBasicBlock & MBB,ArrayRef<MachineOperand> Cond,Register DstReg,Register TrueReg,Register FalseReg,int & CondCycles,int & TrueCycles,int & FalseCycles) const canInsertSelect() argument
3267 insertSelect(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,Register DstReg,ArrayRef<MachineOperand> Cond,Register TrueReg,Register FalseReg) const insertSelect() argument
[all...] |
| /llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 4099 canInsertSelect(const MachineBasicBlock & MBB,ArrayRef<MachineOperand> Cond,Register DstReg,Register TrueReg,Register FalseReg,int & CondCycles,int & TrueCycles,int & FalseCycles) const canInsertSelect() argument
4137 insertSelect(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,Register DstReg,ArrayRef<MachineOperand> Cond,Register TrueReg,Register FalseReg) const insertSelect() argument
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 704 canInsertSelect(const MachineBasicBlock & MBB,ArrayRef<MachineOperand> Cond,Register DstReg,Register TrueReg,Register FalseReg,int & CondCycles,int & TrueCycles,int & FalseCycles) const canInsertSelect() argument
755 insertSelect(MachineBasicBlock & MBB,MachineBasicBlock::iterator I,const DebugLoc & DL,Register DstReg,ArrayRef<MachineOperand> Cond,Register TrueReg,Register FalseReg) const insertSelect() argument
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