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Searched defs:TSFlags (Results 1 – 25 of 34) sorted by relevance

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/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.h41 static inline bool isVRegClass(uint64_t TSFlags) { in isVRegClass() argument
46 static inline RISCVII::VLMUL getLMul(uint64_t TSFlags) { in getLMul() argument
51 static inline unsigned getNF(uint64_t TSFlags) { in getNF() argument
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H A DRISCVOptWInstrs.cpp102 const uint64_t TSFlags = MCID.TSFlags; in vectorPseudoHasAllNBitUsers() local
353 uint64_t TSFlags = MI.getDesc().TSFlags; isSignExtendingOpW() local
H A DRISCVInsertVSETVLI.cpp406 uint64_t TSFlags = MI.getDesc().TSFlags; getDemanded() local
1011 const uint64_t TSFlags = MI.getDesc().TSFlags; computeInfoForInstr() local
1432 uint64_t TSFlags = MI.getDesc().TSFlags; emitVSETVLIs() local
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H A DRISCVAsmPrinter.cpp957 uint64_t TSFlags = MCID.TSFlags; lowerRISCVVMachineInstrToMCInst() local
H A DRISCVInstrInfo.cpp297 uint64_t TSFlags = MBBI->getDesc().TSFlags; isConvertibleToVMV_V_V() local
1713 const uint64_t TSFlags = Desc.TSFlags; areRVVInstsReassociable() local
2473 const uint64_t TSFlags = Desc.TSFlags; verifyInstruction() local
2983 uint64_t TSFlags = MI.getDesc().TSFlags; createMIROperandComment() local
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/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVBaseInfo.h142 // Helper functions to read TSFlags. in isTiedPseudo() argument
130 getFormat(uint64_t TSFlags) getFormat() argument
134 getLMul(uint64_t TSFlags) getLMul() argument
138 doesForceTailAgnostic(uint64_t TSFlags) doesForceTailAgnostic() argument
146 hasSEWOp(uint64_t TSFlags) hasSEWOp() argument
150 hasVLOp(uint64_t TSFlags) hasVLOp() argument
154 hasVecPolicyOp(uint64_t TSFlags) hasVecPolicyOp() argument
158 isRVVWideningReduction(uint64_t TSFlags) isRVVWideningReduction() argument
162 usesMaskPolicy(uint64_t TSFlags) usesMaskPolicy() argument
167 hasRoundModeOp(uint64_t TSFlags) hasRoundModeOp() argument
172 usesVXRM(uint64_t TSFlags) usesVXRM() argument
175 const uint64_t TSFlags = Desc.TSFlags; getVLOpNum() local
186 const uint64_t TSFlags = Desc.TSFlags; getSEWOpNum() local
202 const uint64_t TSFlags = Desc.TSFlags; getFRMOpNum() local
217 const uint64_t TSFlags = Desc.TSFlags; getVXRMOpNum() local
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/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86BaseInfo.h894 return TSFlags >> X86II::OpcodeShift; in hasImm() argument
879 isPrefix(uint64_t TSFlags) isPrefix() argument
884 isPseudo(uint64_t TSFlags) isPseudo() argument
890 getBaseOpcodeFor(uint64_t TSFlags) getBaseOpcodeFor() argument
898 getSizeOfImm(uint64_t TSFlags) getSizeOfImm() argument
920 isImmPCRel(uint64_t TSFlags) isImmPCRel() argument
940 isImmSigned(uint64_t TSFlags) isImmSigned() argument
998 hasNewDataDest(uint64_t TSFlags) hasNewDataDest() argument
1008 getMemoryOperandNo(uint64_t TSFlags) getMemoryOperandNo() argument
1258 uint64_t TSFlags = Desc.TSFlags; canUseApxExtendedReg() local
1311 isKMasked(uint64_t TSFlags) isKMasked() argument
1316 isKMergeMasked(uint64_t TSFlags) isKMergeMasked() argument
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H A DX86MCCodeEmitter.cpp439 /// instruction with the specified TSFlags. in getImmFixupKind() argument
415 isDispOrCDisp8(uint64_t TSFlags,int Value,int & ImmOffset) isDispOrCDisp8() argument
608 emitMemModRMByte(const MCInst & MI,unsigned Op,unsigned RegOpcodeField,uint64_t TSFlags,PrefixKind Kind,uint64_t StartByte,SmallVectorImpl<char> & CB,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & STI,bool ForceSIB) const emitMemModRMByte() argument
881 uint64_t TSFlags = MCII.get(MI.getOpcode()).TSFlags; emitPrefixImpl() local
956 uint64_t TSFlags = Desc.TSFlags; emitVEXOpcodePrefix() local
1335 uint64_t TSFlags = Desc.TSFlags; emitREXPrefix() local
1461 uint64_t TSFlags = Desc.TSFlags; emitOpcodePrefix() local
1523 uint64_t TSFlags = Desc.TSFlags; emitPrefix() local
1545 uint64_t TSFlags = Desc.TSFlags; encodeInstruction() local
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H A DX86InstPrinterCommon.cpp383 uint64_t TSFlags = Desc.TSFlags; printInstFlags() local
H A DX86EncodingOptimization.cpp37 uint64_t TSFlags = Desc.TSFlags; in optimizeInstFromVEX3ToVEX2() local
H A DX86InstComments.cpp253 uint64_t TSFlags = Desc.TSFlags; printMasking() local
H A DX86AsmBackend.cpp259 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags); in isRIPRelative() local
298 uint64_t TSFlags = Desc.TSFlags; determinePaddingPrefix() local
H A DX86MCTargetDesc.cpp117 uint64_t AdSize = TSFlags & X86II::AdSizeMask; in needsAddressSizeOverride() argument
/llvm-project/llvm/lib/Target/X86/
H A DX86CompressEVEX.cpp178 uint64_t TSFlags = MI.getDesc().TSFlags; CompressEVEXImpl() local
H A DX86InstrFMA3Info.cpp141 getFMA3Group(unsigned Opcode,uint64_t TSFlags) getFMA3Group() argument
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/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp112 uint64_t TSFlags = MI.getDesc().TSFlags; getBaseOffset() local
/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYInstPrinter.cpp132 uint64_t TSFlags = MII.get(MI->getOpcode()).TSFlags; in printOperand() local
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp287 uint64_t TSFlags = MCID.TSFlags; in GetInstrType() local
/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInsertDelayAlu.cpp63 static DelayType getDelayType(uint64_t TSFlags) { in getDelayType() argument
/llvm-project/llvm/include/llvm/MC/
H A DMCInstrDesc.h215 uint64_t TSFlags; // Target Specific Flag values variable
/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp570 uint64_t TSFlags = Desc.TSFlags; evaluateMemoryOperandAddress() local
/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp3453 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; checkTargetMatchPredicate() local
4381 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; validateOffset() local
4410 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; validateFlatOffset() local
4457 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; validateSMEMOffset() local
4530 uint64_t TSFlags = MII.get(Opc).TSFlags; validateOpSel() local
4561 uint64_t TSFlags = MII.get(Opc).TSFlags; validateNeg() local
4728 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; validateAGPRLdSt() local
4849 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; validateDS() local
4911 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags; validateCoherencyBits() local
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/llvm-project/llvm/utils/TableGen/Common/
H A DCodeGenRegisters.h357 uint8_t TSFlags; variable
/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp387 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; decodeAVLdSt() local
930 auto TSFlags = MCII->get(MI.getOpcode()).TSFlags; convertMIMGInst() local
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/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h64 const uint8_t TSFlags; global() variable

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