1 /* $NetBSD: smu73_discrete.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef _SMU73_DISCRETE_H_ 26 #define _SMU73_DISCRETE_H_ 27 28 #include "smu73.h" 29 30 #pragma pack(push, 1) 31 32 struct SMIO_Pattern 33 { 34 uint16_t Voltage; 35 uint8_t Smio; 36 uint8_t padding; 37 }; 38 39 typedef struct SMIO_Pattern SMIO_Pattern; 40 41 struct SMIO_Table 42 { 43 SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS]; 44 }; 45 46 typedef struct SMIO_Table SMIO_Table; 47 48 struct SMU73_Discrete_GraphicsLevel { 49 uint32_t MinVoltage; 50 51 uint32_t SclkFrequency; 52 53 uint8_t pcieDpmLevel; 54 uint8_t DeepSleepDivId; 55 uint16_t ActivityLevel; 56 uint32_t CgSpllFuncCntl3; 57 uint32_t CgSpllFuncCntl4; 58 uint32_t SpllSpreadSpectrum; 59 uint32_t SpllSpreadSpectrum2; 60 uint32_t CcPwrDynRm; 61 uint32_t CcPwrDynRm1; 62 uint8_t SclkDid; 63 uint8_t DisplayWatermark; 64 uint8_t EnabledForActivity; 65 uint8_t EnabledForThrottle; 66 uint8_t UpHyst; 67 uint8_t DownHyst; 68 uint8_t VoltageDownHyst; 69 uint8_t PowerThrottle; 70 }; 71 72 typedef struct SMU73_Discrete_GraphicsLevel SMU73_Discrete_GraphicsLevel; 73 74 struct SMU73_Discrete_ACPILevel { 75 uint32_t Flags; 76 uint32_t MinVoltage; 77 uint32_t SclkFrequency; 78 uint8_t SclkDid; 79 uint8_t DisplayWatermark; 80 uint8_t DeepSleepDivId; 81 uint8_t padding; 82 uint32_t CgSpllFuncCntl; 83 uint32_t CgSpllFuncCntl2; 84 uint32_t CgSpllFuncCntl3; 85 uint32_t CgSpllFuncCntl4; 86 uint32_t SpllSpreadSpectrum; 87 uint32_t SpllSpreadSpectrum2; 88 uint32_t CcPwrDynRm; 89 uint32_t CcPwrDynRm1; 90 }; 91 92 typedef struct SMU73_Discrete_ACPILevel SMU73_Discrete_ACPILevel; 93 94 struct SMU73_Discrete_Ulv { 95 uint32_t CcPwrDynRm; 96 uint32_t CcPwrDynRm1; 97 uint16_t VddcOffset; 98 uint8_t VddcOffsetVid; 99 uint8_t VddcPhase; 100 uint32_t Reserved; 101 }; 102 103 typedef struct SMU73_Discrete_Ulv SMU73_Discrete_Ulv; 104 105 struct SMU73_Discrete_MemoryLevel 106 { 107 uint32_t MinVoltage; 108 uint32_t MinMvdd; 109 110 uint32_t MclkFrequency; 111 112 uint8_t StutterEnable; 113 uint8_t FreqRange; 114 uint8_t EnabledForThrottle; 115 uint8_t EnabledForActivity; 116 117 uint8_t UpHyst; 118 uint8_t DownHyst; 119 uint8_t VoltageDownHyst; 120 uint8_t padding; 121 122 uint16_t ActivityLevel; 123 uint8_t DisplayWatermark; 124 uint8_t MclkDivider; 125 }; 126 127 typedef struct SMU73_Discrete_MemoryLevel SMU73_Discrete_MemoryLevel; 128 129 struct SMU73_Discrete_LinkLevel 130 { 131 uint8_t PcieGenSpeed; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 132 uint8_t PcieLaneCount; ///< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 133 uint8_t EnabledForActivity; 134 uint8_t SPC; 135 uint32_t DownThreshold; 136 uint32_t UpThreshold; 137 uint32_t Reserved; 138 }; 139 140 typedef struct SMU73_Discrete_LinkLevel SMU73_Discrete_LinkLevel; 141 142 143 // MC ARB DRAM Timing registers. 144 struct SMU73_Discrete_MCArbDramTimingTableEntry 145 { 146 uint32_t McArbDramTiming; 147 uint32_t McArbDramTiming2; 148 uint8_t McArbBurstTime; 149 uint8_t TRRDS; 150 uint8_t TRRDL; 151 uint8_t padding; 152 }; 153 154 typedef struct SMU73_Discrete_MCArbDramTimingTableEntry SMU73_Discrete_MCArbDramTimingTableEntry; 155 156 struct SMU73_Discrete_MCArbDramTimingTable 157 { 158 SMU73_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS]; 159 }; 160 161 typedef struct SMU73_Discrete_MCArbDramTimingTable SMU73_Discrete_MCArbDramTimingTable; 162 163 // UVD VCLK/DCLK state (level) definition. 164 struct SMU73_Discrete_UvdLevel 165 { 166 uint32_t VclkFrequency; 167 uint32_t DclkFrequency; 168 uint32_t MinVoltage; 169 uint8_t VclkDivider; 170 uint8_t DclkDivider; 171 uint8_t padding[2]; 172 }; 173 174 typedef struct SMU73_Discrete_UvdLevel SMU73_Discrete_UvdLevel; 175 176 // Clocks for other external blocks (VCE, ACP, SAMU). 177 struct SMU73_Discrete_ExtClkLevel 178 { 179 uint32_t Frequency; 180 uint32_t MinVoltage; 181 uint8_t Divider; 182 uint8_t padding[3]; 183 }; 184 185 typedef struct SMU73_Discrete_ExtClkLevel SMU73_Discrete_ExtClkLevel; 186 187 struct SMU73_Discrete_StateInfo 188 { 189 uint32_t SclkFrequency; 190 uint32_t MclkFrequency; 191 uint32_t VclkFrequency; 192 uint32_t DclkFrequency; 193 uint32_t SamclkFrequency; 194 uint32_t AclkFrequency; 195 uint32_t EclkFrequency; 196 uint16_t MvddVoltage; 197 uint16_t padding16; 198 uint8_t DisplayWatermark; 199 uint8_t McArbIndex; 200 uint8_t McRegIndex; 201 uint8_t SeqIndex; 202 uint8_t SclkDid; 203 int8_t SclkIndex; 204 int8_t MclkIndex; 205 uint8_t PCIeGen; 206 207 }; 208 209 typedef struct SMU73_Discrete_StateInfo SMU73_Discrete_StateInfo; 210 211 struct SMU73_Discrete_DpmTable 212 { 213 // Multi-DPM controller settings 214 SMU73_PIDController GraphicsPIDController; 215 SMU73_PIDController MemoryPIDController; 216 SMU73_PIDController LinkPIDController; 217 218 uint32_t SystemFlags; 219 220 // SMIO masks for voltage and phase controls 221 uint32_t VRConfig; 222 uint32_t SmioMask1; 223 uint32_t SmioMask2; 224 SMIO_Table SmioTable1; 225 SMIO_Table SmioTable2; 226 227 uint32_t MvddLevelCount; 228 229 230 uint8_t BapmVddcVidHiSidd [SMU73_MAX_LEVELS_VDDC]; 231 uint8_t BapmVddcVidLoSidd [SMU73_MAX_LEVELS_VDDC]; 232 uint8_t BapmVddcVidHiSidd2 [SMU73_MAX_LEVELS_VDDC]; 233 234 uint8_t GraphicsDpmLevelCount; 235 uint8_t MemoryDpmLevelCount; 236 uint8_t LinkLevelCount; 237 uint8_t MasterDeepSleepControl; 238 239 uint8_t UvdLevelCount; 240 uint8_t VceLevelCount; 241 uint8_t AcpLevelCount; 242 uint8_t SamuLevelCount; 243 244 uint8_t ThermOutGpio; 245 uint8_t ThermOutPolarity; 246 uint8_t ThermOutMode; 247 uint8_t BootPhases; 248 uint32_t Reserved[4]; 249 250 // State table entries for each DPM state 251 SMU73_Discrete_GraphicsLevel GraphicsLevel [SMU73_MAX_LEVELS_GRAPHICS]; 252 SMU73_Discrete_MemoryLevel MemoryACPILevel; 253 SMU73_Discrete_MemoryLevel MemoryLevel [SMU73_MAX_LEVELS_MEMORY]; 254 SMU73_Discrete_LinkLevel LinkLevel [SMU73_MAX_LEVELS_LINK]; 255 SMU73_Discrete_ACPILevel ACPILevel; 256 SMU73_Discrete_UvdLevel UvdLevel [SMU73_MAX_LEVELS_UVD]; 257 SMU73_Discrete_ExtClkLevel VceLevel [SMU73_MAX_LEVELS_VCE]; 258 SMU73_Discrete_ExtClkLevel AcpLevel [SMU73_MAX_LEVELS_ACP]; 259 SMU73_Discrete_ExtClkLevel SamuLevel [SMU73_MAX_LEVELS_SAMU]; 260 SMU73_Discrete_Ulv Ulv; 261 262 uint32_t SclkStepSize; 263 uint32_t Smio [SMU73_MAX_ENTRIES_SMIO]; 264 265 uint8_t UvdBootLevel; 266 uint8_t VceBootLevel; 267 uint8_t AcpBootLevel; 268 uint8_t SamuBootLevel; 269 270 uint8_t GraphicsBootLevel; 271 uint8_t GraphicsVoltageChangeEnable; 272 uint8_t GraphicsThermThrottleEnable; 273 uint8_t GraphicsInterval; 274 275 uint8_t VoltageInterval; 276 uint8_t ThermalInterval; 277 uint16_t TemperatureLimitHigh; 278 279 uint16_t TemperatureLimitLow; 280 uint8_t MemoryBootLevel; 281 uint8_t MemoryVoltageChangeEnable; 282 283 uint16_t BootMVdd; 284 uint8_t MemoryInterval; 285 uint8_t MemoryThermThrottleEnable; 286 287 uint16_t VoltageResponseTime; 288 uint16_t PhaseResponseTime; 289 290 uint8_t PCIeBootLinkLevel; 291 uint8_t PCIeGenInterval; 292 uint8_t DTEInterval; 293 uint8_t DTEMode; 294 295 uint8_t SVI2Enable; 296 uint8_t VRHotGpio; 297 uint8_t AcDcGpio; 298 uint8_t ThermGpio; 299 300 uint16_t PPM_PkgPwrLimit; 301 uint16_t PPM_TemperatureLimit; 302 303 uint16_t DefaultTdp; 304 uint16_t TargetTdp; 305 306 uint16_t FpsHighThreshold; 307 uint16_t FpsLowThreshold; 308 309 uint16_t TemperatureLimitEdge; 310 uint16_t TemperatureLimitHotspot; 311 uint16_t TemperatureLimitLiquid1; 312 uint16_t TemperatureLimitLiquid2; 313 uint16_t TemperatureLimitVrVddc; 314 uint16_t TemperatureLimitVrMvdd; 315 uint16_t TemperatureLimitPlx; 316 317 uint16_t FanGainEdge; 318 uint16_t FanGainHotspot; 319 uint16_t FanGainLiquid; 320 uint16_t FanGainVrVddc; 321 uint16_t FanGainVrMvdd; 322 uint16_t FanGainPlx; 323 uint16_t FanGainHbm; 324 325 uint8_t Liquid1_I2C_address; 326 uint8_t Liquid2_I2C_address; 327 uint8_t Vr_I2C_address; 328 uint8_t Plx_I2C_address; 329 330 uint8_t GeminiMode; 331 uint8_t spare17[3]; 332 uint32_t GeminiApertureHigh; 333 uint32_t GeminiApertureLow; 334 335 uint8_t Liquid_I2C_LineSCL; 336 uint8_t Liquid_I2C_LineSDA; 337 uint8_t Vr_I2C_LineSCL; 338 uint8_t Vr_I2C_LineSDA; 339 uint8_t Plx_I2C_LineSCL; 340 uint8_t Plx_I2C_LineSDA; 341 342 uint8_t spare1253[2]; 343 uint32_t spare123[2]; 344 345 uint8_t DTEAmbientTempBase; 346 uint8_t DTETjOffset; 347 uint8_t GpuTjMax; 348 uint8_t GpuTjHyst; 349 350 uint16_t BootVddc; 351 uint16_t BootVddci; 352 353 uint32_t BAPM_TEMP_GRADIENT; 354 355 uint32_t LowSclkInterruptThreshold; 356 uint32_t VddGfxReChkWait; 357 358 uint8_t ClockStretcherAmount; 359 uint8_t Sclk_CKS_masterEn0_7; 360 uint8_t Sclk_CKS_masterEn8_15; 361 uint8_t DPMFreezeAndForced; 362 363 uint8_t Sclk_voltageOffset[8]; 364 365 SMU_ClockStretcherDataTable ClockStretcherDataTable; 366 SMU_CKS_LOOKUPTable CKS_LOOKUPTable; 367 }; 368 369 typedef struct SMU73_Discrete_DpmTable SMU73_Discrete_DpmTable; 370 371 372 // --------------------------------------------------- Fan Table ----------------------------------------------------------- 373 struct SMU73_Discrete_FanTable 374 { 375 uint16_t FdoMode; 376 int16_t TempMin; 377 int16_t TempMed; 378 int16_t TempMax; 379 int16_t Slope1; 380 int16_t Slope2; 381 int16_t FdoMin; 382 int16_t HystUp; 383 int16_t HystDown; 384 int16_t HystSlope; 385 int16_t TempRespLim; 386 int16_t TempCurr; 387 int16_t SlopeCurr; 388 int16_t PwmCurr; 389 uint32_t RefreshPeriod; 390 int16_t FdoMax; 391 uint8_t TempSrc; 392 int8_t Padding; 393 }; 394 395 typedef struct SMU73_Discrete_FanTable SMU73_Discrete_FanTable; 396 397 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4 398 #define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG) 399 400 401 402 struct SMU7_MclkDpmScoreboard 403 { 404 405 uint32_t PercentageBusy; 406 407 int32_t PIDError; 408 int32_t PIDIntegral; 409 int32_t PIDOutput; 410 411 uint32_t SigmaDeltaAccum; 412 uint32_t SigmaDeltaOutput; 413 uint32_t SigmaDeltaLevel; 414 415 uint32_t UtilizationSetpoint; 416 417 uint8_t TdpClampMode; 418 uint8_t TdcClampMode; 419 uint8_t ThermClampMode; 420 uint8_t VoltageBusy; 421 422 int8_t CurrLevel; 423 int8_t TargLevel; 424 uint8_t LevelChangeInProgress; 425 uint8_t UpHyst; 426 427 uint8_t DownHyst; 428 uint8_t VoltageDownHyst; 429 uint8_t DpmEnable; 430 uint8_t DpmRunning; 431 432 uint8_t DpmForce; 433 uint8_t DpmForceLevel; 434 uint8_t DisplayWatermark; 435 uint8_t McArbIndex; 436 437 uint32_t MinimumPerfMclk; 438 439 uint8_t AcpiReq; 440 uint8_t AcpiAck; 441 uint8_t MclkSwitchInProgress; 442 uint8_t MclkSwitchCritical; 443 444 uint8_t IgnoreVBlank; 445 uint8_t TargetMclkIndex; 446 uint8_t TargetMvddIndex; 447 uint8_t MclkSwitchResult; 448 449 uint16_t VbiFailureCount; 450 uint8_t VbiWaitCounter; 451 uint8_t EnabledLevelsChange; 452 453 uint16_t LevelResidencyCounters [SMU73_MAX_LEVELS_MEMORY]; 454 uint16_t LevelSwitchCounters [SMU73_MAX_LEVELS_MEMORY]; 455 456 void (*TargetStateCalculator)(uint8_t); 457 void (*SavedTargetStateCalculator)(uint8_t); 458 459 uint16_t AutoDpmInterval; 460 uint16_t AutoDpmRange; 461 462 uint16_t VbiTimeoutCount; 463 uint16_t MclkSwitchingTime; 464 465 uint8_t fastSwitch; 466 uint8_t Save_PIC_VDDGFX_EXIT; 467 uint8_t Save_PIC_VDDGFX_ENTER; 468 uint8_t padding; 469 470 }; 471 472 typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard; 473 474 struct SMU7_UlvScoreboard 475 { 476 uint8_t EnterUlv; 477 uint8_t ExitUlv; 478 uint8_t UlvActive; 479 uint8_t WaitingForUlv; 480 uint8_t UlvEnable; 481 uint8_t UlvRunning; 482 uint8_t UlvMasterEnable; 483 uint8_t padding; 484 uint32_t UlvAbortedCount; 485 uint32_t UlvTimeStamp; 486 }; 487 488 typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard; 489 490 struct VddgfxSavedRegisters 491 { 492 uint32_t GPU_DBG[3]; 493 uint32_t MEC_BaseAddress_Hi; 494 uint32_t MEC_BaseAddress_Lo; 495 uint32_t THM_TMON0_CTRL2__RDIR_PRESENT; 496 uint32_t THM_TMON1_CTRL2__RDIR_PRESENT; 497 uint32_t CP_INT_CNTL; 498 }; 499 500 typedef struct VddgfxSavedRegisters VddgfxSavedRegisters; 501 502 struct SMU7_VddGfxScoreboard 503 { 504 uint8_t VddGfxEnable; 505 uint8_t VddGfxActive; 506 uint8_t VPUResetOccured; 507 uint8_t padding; 508 509 uint32_t VddGfxEnteredCount; 510 uint32_t VddGfxAbortedCount; 511 512 uint32_t VddGfxVid; 513 514 VddgfxSavedRegisters SavedRegisters; 515 }; 516 517 typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard; 518 519 struct SMU7_TdcLimitScoreboard { 520 uint8_t Enable; 521 uint8_t Running; 522 uint16_t Alpha; 523 uint32_t FilteredIddc; 524 uint32_t IddcLimit; 525 uint32_t IddcHyst; 526 SMU7_HystController_Data HystControllerData; 527 }; 528 529 typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard; 530 531 struct SMU7_PkgPwrLimitScoreboard { 532 uint8_t Enable; 533 uint8_t Running; 534 uint16_t Alpha; 535 uint32_t FilteredPkgPwr; 536 uint32_t Limit; 537 uint32_t Hyst; 538 uint32_t LimitFromDriver; 539 SMU7_HystController_Data HystControllerData; 540 }; 541 542 typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard; 543 544 struct SMU7_BapmScoreboard { 545 uint32_t source_powers[SMU73_DTE_SOURCES]; 546 uint32_t source_powers_last[SMU73_DTE_SOURCES]; 547 int32_t entity_temperatures[SMU73_NUM_GPU_TES]; 548 int32_t initial_entity_temperatures[SMU73_NUM_GPU_TES]; 549 int32_t Limit; 550 int32_t Hyst; 551 int32_t therm_influence_coeff_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS * 2]; 552 int32_t therm_node_table[SMU73_DTE_ITERATIONS * SMU73_DTE_SOURCES * SMU73_DTE_SINKS]; 553 uint16_t ConfigTDPPowerScalar; 554 uint16_t FanSpeedPowerScalar; 555 uint16_t OverDrivePowerScalar; 556 uint16_t OverDriveLimitScalar; 557 uint16_t FinalPowerScalar; 558 uint8_t VariantID; 559 uint8_t spare997; 560 561 SMU7_HystController_Data HystControllerData; 562 563 int32_t temperature_gradient_slope; 564 int32_t temperature_gradient; 565 uint32_t measured_temperature; 566 }; 567 568 569 typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard; 570 571 struct SMU7_AcpiScoreboard { 572 uint32_t SavedInterruptMask[2]; 573 uint8_t LastACPIRequest; 574 uint8_t CgBifResp; 575 uint8_t RequestType; 576 uint8_t Padding; 577 SMU73_Discrete_ACPILevel D0Level; 578 }; 579 580 typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard; 581 582 struct SMU_QuadraticCoeffs { 583 int32_t m1; 584 uint32_t b; 585 586 int16_t m2; 587 uint8_t m1_shift; 588 uint8_t m2_shift; 589 }; 590 591 typedef struct SMU_QuadraticCoeffs SMU_QuadraticCoeffs; 592 593 struct SMU73_Discrete_PmFuses { 594 /* dw0-dw1 */ 595 uint8_t BapmVddCVidHiSidd[8]; 596 597 /* dw2-dw3 */ 598 uint8_t BapmVddCVidLoSidd[8]; 599 600 /* dw4-dw5 */ 601 uint8_t VddCVid[8]; 602 603 /* dw1*/ 604 uint8_t SviLoadLineEn; 605 uint8_t SviLoadLineVddC; 606 uint8_t SviLoadLineTrimVddC; 607 uint8_t SviLoadLineOffsetVddC; 608 609 /* dw2 */ 610 uint16_t TDC_VDDC_PkgLimit; 611 uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; 612 uint8_t TDC_MAWt; 613 614 /* dw3 */ 615 uint8_t TdcWaterfallCtl; 616 uint8_t LPMLTemperatureMin; 617 uint8_t LPMLTemperatureMax; 618 uint8_t Reserved; 619 620 /* dw4-dw7 */ 621 uint8_t LPMLTemperatureScaler[16]; 622 623 /* dw8-dw9 */ 624 int16_t FuzzyFan_ErrorSetDelta; 625 int16_t FuzzyFan_ErrorRateSetDelta; 626 int16_t FuzzyFan_PwmSetDelta; 627 uint16_t Reserved6; 628 629 /* dw10-dw14 */ 630 uint8_t GnbLPML[16]; 631 632 /* dw15 */ 633 uint8_t GnbLPMLMaxVid; 634 uint8_t GnbLPMLMinVid; 635 uint8_t Reserved1[2]; 636 637 /* dw16 */ 638 uint16_t BapmVddCBaseLeakageHiSidd; 639 uint16_t BapmVddCBaseLeakageLoSidd; 640 641 /* AVFS */ 642 uint16_t VFT_Temp[3]; 643 uint16_t padding; 644 645 SMU_QuadraticCoeffs VFT_ATE[3]; 646 647 SMU_QuadraticCoeffs AVFS_GB; 648 SMU_QuadraticCoeffs ATE_ACBTC_GB; 649 650 SMU_QuadraticCoeffs P2V; 651 652 uint32_t PsmCharzFreq; 653 654 uint16_t InversionVoltage; 655 uint16_t PsmCharzTemp; 656 657 uint32_t EnabledAvfsModules; 658 }; 659 660 typedef struct SMU73_Discrete_PmFuses SMU73_Discrete_PmFuses; 661 662 struct SMU7_Discrete_Log_Header_Table { 663 uint32_t version; 664 uint32_t asic_id; 665 uint16_t flags; 666 uint16_t entry_size; 667 uint32_t total_size; 668 uint32_t num_of_entries; 669 uint8_t type; 670 uint8_t mode; 671 uint8_t filler_0[2]; 672 uint32_t filler_1[2]; 673 }; 674 675 typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table; 676 677 struct SMU7_Discrete_Log_Cntl { 678 uint8_t Enabled; 679 uint8_t Type; 680 uint8_t padding[2]; 681 uint32_t BufferSize; 682 uint32_t SamplesLogged; 683 uint32_t SampleSize; 684 uint32_t AddrL; 685 uint32_t AddrH; 686 }; 687 688 typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl; 689 690 #define CAC_ACC_NW_NUM_OF_SIGNALS 87 691 692 struct SMU7_Discrete_Cac_Collection_Table { 693 uint32_t temperature; 694 uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS]; 695 }; 696 697 typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table; 698 699 struct SMU7_Discrete_Cac_Verification_Table { 700 uint32_t VddcTotalPower; 701 uint32_t VddcLeakagePower; 702 uint32_t VddcConstantPower; 703 uint32_t VddcGfxDynamicPower; 704 uint32_t VddcUvdDynamicPower; 705 uint32_t VddcVceDynamicPower; 706 uint32_t VddcAcpDynamicPower; 707 uint32_t VddcPcieDynamicPower; 708 uint32_t VddcDceDynamicPower; 709 uint32_t VddcCurrent; 710 uint32_t VddcVoltage; 711 uint32_t VddciTotalPower; 712 uint32_t VddciLeakagePower; 713 uint32_t VddciConstantPower; 714 uint32_t VddciDynamicPower; 715 uint32_t Vddr1TotalPower; 716 uint32_t Vddr1LeakagePower; 717 uint32_t Vddr1ConstantPower; 718 uint32_t Vddr1DynamicPower; 719 uint32_t spare[4]; 720 uint32_t temperature; 721 }; 722 723 typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table; 724 725 struct SMU7_Discrete_Pm_Status_Table { 726 //Thermal entities 727 int32_t T_meas_max[SMU73_THERMAL_INPUT_LOOP_COUNT]; 728 int32_t T_meas_acc[SMU73_THERMAL_INPUT_LOOP_COUNT]; 729 int32_t T_meas_acc_cnt[SMU73_THERMAL_INPUT_LOOP_COUNT]; 730 uint32_t T_hbm_acc; 731 732 //Voltage domains 733 uint32_t I_calc_max; 734 uint32_t I_calc_acc; 735 uint32_t P_meas_acc; 736 uint32_t V_meas_load_acc; 737 uint32_t I_meas_acc; 738 uint32_t P_meas_acc_vddci; 739 uint32_t V_meas_load_acc_vddci; 740 uint32_t I_meas_acc_vddci; 741 742 //Frequency 743 uint16_t Sclk_dpm_residency[8]; 744 uint16_t Uvd_dpm_residency[8]; 745 uint16_t Vce_dpm_residency[8]; 746 747 //Chip 748 uint32_t P_roc_acc; 749 uint32_t PkgPwr_max; 750 uint32_t PkgPwr_acc; 751 uint32_t MclkSwitchingTime_max; 752 uint32_t MclkSwitchingTime_acc; 753 uint32_t FanPwm_acc; 754 uint32_t FanRpm_acc; 755 uint32_t Gfx_busy_acc; 756 uint32_t Mc_busy_acc; 757 uint32_t Fps_acc; 758 759 uint32_t AccCnt; 760 }; 761 762 typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table; 763 764 //FIXME THESE NEED TO BE UPDATED 765 #define SMU7_SCLK_CAC 0x561 766 #define SMU7_MCLK_CAC 0xF9 767 #define SMU7_VCLK_CAC 0x2DE 768 #define SMU7_DCLK_CAC 0x2DE 769 #define SMU7_ECLK_CAC 0x25E 770 #define SMU7_ACLK_CAC 0x25E 771 #define SMU7_SAMCLK_CAC 0x25E 772 #define SMU7_DISPCLK_CAC 0x100 773 #define SMU7_CAC_CONSTANT 0x2EE3430 774 #define SMU7_CAC_CONSTANT_SHIFT 18 775 776 #define SMU7_VDDCI_MCLK_CONST 1765 777 #define SMU7_VDDCI_MCLK_CONST_SHIFT 16 778 #define SMU7_VDDCI_VDDCI_CONST 50958 779 #define SMU7_VDDCI_VDDCI_CONST_SHIFT 14 780 #define SMU7_VDDCI_CONST 11781 781 #define SMU7_VDDCI_STROBE_PWR 1331 782 783 #define SMU7_VDDR1_CONST 693 784 #define SMU7_VDDR1_CAC_WEIGHT 20 785 #define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19 786 #define SMU7_VDDR1_STROBE_PWR 512 787 788 #define SMU7_AREA_COEFF_UVD 0xA78 789 #define SMU7_AREA_COEFF_VCE 0x190A 790 #define SMU7_AREA_COEFF_ACP 0x22D1 791 #define SMU7_AREA_COEFF_SAMU 0x534 792 793 //ThermOutMode values 794 #define SMU7_THERM_OUT_MODE_DISABLE 0x0 795 #define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1 796 #define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2 797 798 #pragma pack(pop) 799 800 #endif 801 802