1 /* $NetBSD: a9tmr_reg.h,v 1.3 2021/10/02 20:52:09 skrll Exp $ */ 2 /*- 3 * Copyright (c) 2012 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Matt Thomas of 3am Software Foundry. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 20 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 22 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * ARM MPCORE Global Timer Register Definitions 33 * 34 * These registers are accessible through a dedicated internal bus. 35 * All accesses must be done in a little-endian manner. 36 * The base address of the pages containing these registers is defined 37 * by the pins PERIPHBASE[31:13] which can be obtained by doing a 38 * MRC p15,4,<Rd>,c15,c0,0; Read Configuration Base Address Register 39 * (except cortex-A9 uniprocessor) 40 * 41 */ 42 43 #ifndef _ARM_CORTEX_A9TMR_REG_H_ 44 #define _ARM_CORTEX_A9TMR_REG_H_ 45 46 #define TMR_GLOBAL_BASE 0x0200 // Offset in PeriphBase 47 #define TMR_PRIVATE_BASE 0x0600 48 #define TMR_WDOG_BASE 0x0620 49 #define TMR_GLOBAL_SIZE 0x0100 50 #define TMR_PRIVATE_SIZE 0x0020 51 #define TMR_WDOG_SIZE 0x0020 52 53 /* 54 * F(timer) = PeriphClk / ((PreScaler_Value + 1) * Load_Value + 1)) 55 */ 56 #define TMR_LOAD 0x0000 // Timer Load Register 57 #define TMR_CTR 0x0004 // Timer Counter Register 58 #define TMR_CTL 0x0008 // Timer Control Register 59 #define TMR_INT 0x000C // Timer Interrupt Status 60 #define TMR_WDOGRST 0x0010 // Timer Reset Status (WDOG only) 61 #define TMR_WDOGDIS 0x0014 // [WO] Timer Disable (WDOG only) 62 63 #define TMR_CTL_PRESCALER __BITS(15,8) 64 #define TMR_CTL_WDOG_MODE __BIT(3) // WDOG mode 65 #define TMR_CTL_INT_ENABLE __BIT(2) // INT 29/30 is enabled 66 #define TMR_CTL_AUTO_RELOAD __BIT(1) 67 #define TMR_CTL_ENABLE __BIT(0) 68 69 #define TMR_INT_EVENT __BIT(0) // [W1C] timer reached 0 70 #define TMR_RST_EVENT __BIT(0) // [W1C] wdog timer reached 0 71 72 #define TMR_WDOG_DISABLE_MAGIC1 0x12345678 73 #define TMR_WDOG_DISABLE_MAGIC2 0x87654321 74 75 /* 76 * Global Timer is a 64-bit incrementing counter. As much as we'd like to 77 * be able to use LDRD for loading the 64-bit counter, we aren't allowed to. 78 */ 79 #define TMR_GBL_CTR_L 0x000 // Global Timer 64-bit Lower Value 80 #define TMR_GBL_CTR_U 0x004 // Global Timer 64-bit Upper Timer 81 #define TMR_GBL_CTL 0x008 // Global Timer Control 82 #define TMR_GBL_INT 0x00c // [L] Global Timer Interrupt Status 83 #define TMR_GBL_CMP_L 0x010 // [L] Global Timer 64-bit Comparator Low 84 #define TMR_GBL_CMP_H 0x014 // [L] Global Timer 64-bit Comparator High 85 #define TMR_GBL_AUTOINC 0x018 // [L] Global Timer Auto-Increment 86 87 #define TMR_GBL_CTL_PRESCALER __BIT(15,8) 88 #define TMR_GBL_CTL_AUTO_INC __BIT(3) // Auto Increment is enabled 89 #define TMR_GBL_CTL_INT_ENABLE __BIT(2) // [banked] INT 27 is enabled 90 #define TMR_GBL_CTL_CMP_ENABLE __BIT(1) // [banked] 91 #define TMR_GBL_CTL_ENABLE __BIT(0) 92 93 #endif /* !_ARM_CORTEX_A9TMR_REG_H_ */ 94