| /netbsd-src/common/lib/libc/arch/arm/atomic/ |
| H A D | atomic_op_asm.h | 63 #define TLO r5 macro
69 #define TLO r4 macro
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1606 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine() local
1622 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 604 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedBits() local
618 TargetLoweringOpt &TLO, in SimplifyDemandedBits()
901 const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, in SimplifyDemandedBits()
2312 TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in SimplifyDemandedVectorElts() local
2375 APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth, in SimplifyDemandedVectorElts()
2990 TargetLoweringOpt &TLO, unsigned Depth) const { in SimplifyDemandedVectorEltsForTargetNode()
3002 KnownBits &Known, TargetLoweringOpt &TLO, unsigned Depth) const { in SimplifyDemandedBitsForTargetNode()
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| H A D | DAGCombiner.cpp | 327 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); in SimplifyDemandedBits() local
855 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { in CommitTargetLoweringOpt()
1134 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { in CommitTargetLoweringOpt()
1161 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); in SimplifyDemandedBits() local
1180 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); in SimplifyDemandedVectorElts() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 3310 TargetLoweringOpt &TLO) const { in targetShrinkDemandedConstant()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 4069 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in PerformDAGCombine() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1551 TargetLowering::TargetLoweringOpt &TLO, in optimizeLogicalImm()
14791 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in performTBISimplification() local
17929 const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, in SimplifyDemandedBitsForTargetNode()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 38348 TargetLowering::TargetLoweringOpt &TLO, unsigned Depth) const { in SimplifyDemandedVectorEltsForTargetShuffle()
38415 TargetLoweringOpt &TLO, unsigned Depth) const { in SimplifyDemandedVectorEltsForTargetNode()
38969 const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, in SimplifyDemandedBitsForTargetNode()
41400 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), in combineVSelectToBLENDV() local
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 18285 const APInt &OriginalDemandedElts, KnownBits &Known, TargetLoweringOpt &TLO, in SimplifyDemandedBitsForTargetNode()
|