xref: /netbsd-src/external/gpl3/gcc/dist/gcc/config/aarch64/aarch64.h (revision 4fe0f936ff464bca8e6277bde90f477ef5a4d004)
1 /* Machine description for AArch64 architecture.
2    Copyright (C) 2009-2022 Free Software Foundation, Inc.
3    Contributed by ARM Ltd.
4 
5    This file is part of GCC.
6 
7    GCC is free software; you can redistribute it and/or modify it
8    under the terms of the GNU General Public License as published by
9    the Free Software Foundation; either version 3, or (at your option)
10    any later version.
11 
12    GCC is distributed in the hope that it will be useful, but
13    WITHOUT ANY WARRANTY; without even the implied warranty of
14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15    General Public License for more details.
16 
17    You should have received a copy of the GNU General Public License
18    along with GCC; see the file COPYING3.  If not see
19    <http://www.gnu.org/licenses/>.  */
20 
21 
22 #ifndef GCC_AARCH64_H
23 #define GCC_AARCH64_H
24 
25 /* Target CPU builtins.  */
26 #define TARGET_CPU_CPP_BUILTINS()	\
27   aarch64_cpu_cpp_builtins (pfile)
28 
29 
30 
31 #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas ()
32 
33 /* Target machine storage layout.  */
34 
35 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)	\
36   if (GET_MODE_CLASS (MODE) == MODE_INT		\
37       && GET_MODE_SIZE (MODE) < 4)		\
38     {						\
39       if (MODE == QImode || MODE == HImode)	\
40 	{					\
41 	  MODE = SImode;			\
42 	}					\
43     }
44 
45 /* Bits are always numbered from the LSBit.  */
46 #define BITS_BIG_ENDIAN 0
47 
48 /* Big/little-endian flavour.  */
49 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
50 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
51 
52 /* AdvSIMD is supported in the default configuration, unless disabled by
53    -mgeneral-regs-only or by the +nosimd extension.  */
54 #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD)
55 #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP)
56 
57 #define UNITS_PER_WORD		8
58 
59 #define UNITS_PER_VREG		16
60 
61 #define PARM_BOUNDARY		64
62 
63 #define STACK_BOUNDARY		128
64 
65 #define FUNCTION_BOUNDARY	32
66 
67 #define EMPTY_FIELD_BOUNDARY	32
68 
69 #define BIGGEST_ALIGNMENT	128
70 
71 #define SHORT_TYPE_SIZE		16
72 
73 #define INT_TYPE_SIZE		32
74 
75 #define LONG_TYPE_SIZE		(TARGET_ILP32 ? 32 : 64)
76 
77 #define POINTER_SIZE		(TARGET_ILP32 ? 32 : 64)
78 
79 #define LONG_LONG_TYPE_SIZE	64
80 
81 #define FLOAT_TYPE_SIZE		32
82 
83 #define DOUBLE_TYPE_SIZE	64
84 
85 #define LONG_DOUBLE_TYPE_SIZE	128
86 
87 /* This value is the amount of bytes a caller is allowed to drop the stack
88    before probing has to be done for stack clash protection.  */
89 #define STACK_CLASH_CALLER_GUARD 1024
90 
91 /* This value represents the minimum amount of bytes we expect the function's
92    outgoing arguments to be when stack-clash is enabled.  */
93 #define STACK_CLASH_MIN_BYTES_OUTGOING_ARGS 8
94 
95 /* This value controls how many pages we manually unroll the loop for when
96    generating stack clash probes.  */
97 #define STACK_CLASH_MAX_UNROLL_PAGES 4
98 
99 /* The architecture reserves all bits of the address for hardware use,
100    so the vbit must go into the delta field of pointers to member
101    functions.  This is the same config as that in the AArch32
102    port.  */
103 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
104 
105 
106 /* Emit calls to libgcc helpers for atomic operations for runtime detection
107    of LSE instructions.  */
108 #define TARGET_OUTLINE_ATOMICS (aarch64_flag_outline_atomics)
109 
110 /* Align definitions of arrays, unions and structures so that
111    initializations and copies can be made more efficient.  This is not
112    ABI-changing, so it only affects places where we can see the
113    definition.  Increasing the alignment tends to introduce padding,
114    so don't do this when optimizing for size/conserving stack space.  */
115 #define AARCH64_EXPAND_ALIGNMENT(COND, EXP, ALIGN)			\
116   (((COND) && ((ALIGN) < BITS_PER_WORD)					\
117     && (TREE_CODE (EXP) == ARRAY_TYPE					\
118 	|| TREE_CODE (EXP) == UNION_TYPE				\
119 	|| TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
120 
121 /* Align global data.  */
122 #define DATA_ALIGNMENT(EXP, ALIGN)			\
123   AARCH64_EXPAND_ALIGNMENT (!optimize_size, EXP, ALIGN)
124 
125 /* Similarly, make sure that objects on the stack are sensibly aligned.  */
126 #define LOCAL_ALIGNMENT(EXP, ALIGN)				\
127   AARCH64_EXPAND_ALIGNMENT (!flag_conserve_stack, EXP, ALIGN)
128 
129 #define STRUCTURE_SIZE_BOUNDARY		8
130 
131 /* Heap alignment (same as BIGGEST_ALIGNMENT and STACK_BOUNDARY).  */
132 #define MALLOC_ABI_ALIGNMENT  128
133 
134 /* Defined by the ABI */
135 #define WCHAR_TYPE "unsigned int"
136 #define WCHAR_TYPE_SIZE			32
137 
138 /* Using long long breaks -ansi and -std=c90, so these will need to be
139    made conditional for an LLP64 ABI.  */
140 
141 #define SIZE_TYPE	"long unsigned int"
142 
143 #define PTRDIFF_TYPE	"long int"
144 
145 #define PCC_BITFIELD_TYPE_MATTERS	1
146 
147 /* Major revision number of the ARM Architecture implemented by the target.  */
148 extern unsigned aarch64_architecture_version;
149 
150 /* Instruction tuning/selection flags.  */
151 
152 /* Bit values used to identify processor capabilities.  */
153 #define AARCH64_FL_SIMD       (1 << 0)	/* Has SIMD instructions.  */
154 #define AARCH64_FL_FP         (1 << 1)	/* Has FP.  */
155 #define AARCH64_FL_CRYPTO     (1 << 2)	/* Has crypto.  */
156 #define AARCH64_FL_CRC        (1 << 3)	/* Has CRC.  */
157 /* ARMv8.1-A architecture extensions.  */
158 #define AARCH64_FL_LSE	      (1 << 4)  /* Has Large System Extensions.  */
159 #define AARCH64_FL_RDMA       (1 << 5)  /* Has Round Double Multiply Add.  */
160 #define AARCH64_FL_V8_1       (1 << 6)  /* Has ARMv8.1-A extensions.  */
161 /* Armv8-R.  */
162 #define AARCH64_FL_V8_R       (1 << 7)  /* Armv8-R AArch64.  */
163 /* ARMv8.2-A architecture extensions.  */
164 #define AARCH64_FL_V8_2       (1 << 8)  /* Has ARMv8.2-A features.  */
165 #define AARCH64_FL_F16	      (1 << 9)  /* Has ARMv8.2-A FP16 extensions.  */
166 #define AARCH64_FL_SVE        (1 << 10) /* Has Scalable Vector Extensions.  */
167 /* ARMv8.3-A architecture extensions.  */
168 #define AARCH64_FL_V8_3       (1 << 11)  /* Has ARMv8.3-A features.  */
169 #define AARCH64_FL_RCPC       (1 << 12)  /* Has support for RCpc model.  */
170 #define AARCH64_FL_DOTPROD    (1 << 13)  /* Has ARMv8.2-A Dot Product ins.  */
171 /* New flags to split crypto into aes and sha2.  */
172 #define AARCH64_FL_AES	      (1 << 14)  /* Has Crypto AES.  */
173 #define AARCH64_FL_SHA2	      (1 << 15)  /* Has Crypto SHA2.  */
174 /* ARMv8.4-A architecture extensions.  */
175 #define AARCH64_FL_V8_4	      (1 << 16)  /* Has ARMv8.4-A features.  */
176 #define AARCH64_FL_SM4	      (1 << 17)  /* Has ARMv8.4-A SM3 and SM4.  */
177 #define AARCH64_FL_SHA3	      (1 << 18)  /* Has ARMv8.4-a SHA3 and SHA512.  */
178 #define AARCH64_FL_F16FML     (1 << 19)  /* Has ARMv8.4-a FP16 extensions.  */
179 #define AARCH64_FL_RCPC8_4    (1 << 20)  /* Has ARMv8.4-a RCPC extensions.  */
180 
181 /* Statistical Profiling extensions.  */
182 #define AARCH64_FL_PROFILE    (1 << 21)
183 
184 /* ARMv8.5-A architecture extensions.  */
185 #define AARCH64_FL_V8_5	      (1 << 22)  /* Has ARMv8.5-A features.  */
186 #define AARCH64_FL_RNG	      (1 << 23)  /* ARMv8.5-A Random Number Insns.  */
187 #define AARCH64_FL_MEMTAG     (1 << 24)  /* ARMv8.5-A Memory Tagging
188 					    Extensions.  */
189 
190 /* Speculation Barrier instruction supported.  */
191 #define AARCH64_FL_SB	      (1 << 25)
192 
193 /* Speculative Store Bypass Safe instruction supported.  */
194 #define AARCH64_FL_SSBS	      (1 << 26)
195 
196 /* Execution and Data Prediction Restriction instructions supported.  */
197 #define AARCH64_FL_PREDRES    (1 << 27)
198 
199 /* SVE2 instruction supported.  */
200 #define AARCH64_FL_SVE2		(1 << 28)
201 #define AARCH64_FL_SVE2_AES	(1 << 29)
202 #define AARCH64_FL_SVE2_SM4	(1 << 30)
203 #define AARCH64_FL_SVE2_SHA3	(1ULL << 31)
204 #define AARCH64_FL_SVE2_BITPERM	(1ULL << 32)
205 
206 /* Transactional Memory Extension.  */
207 #define AARCH64_FL_TME	      (1ULL << 33)  /* Has TME instructions.  */
208 
209 /* Armv8.6-A architecture extensions.  */
210 #define AARCH64_FL_V8_6	      (1ULL << 34)
211 
212 /* 8-bit Integer Matrix Multiply (I8MM) extensions.  */
213 #define AARCH64_FL_I8MM	      (1ULL << 35)
214 
215 /* Brain half-precision floating-point (BFloat16) Extension.  */
216 #define AARCH64_FL_BF16	      (1ULL << 36)
217 
218 /* 32-bit Floating-point Matrix Multiply (F32MM) extensions.  */
219 #define AARCH64_FL_F32MM      (1ULL << 37)
220 
221 /* 64-bit Floating-point Matrix Multiply (F64MM) extensions.  */
222 #define AARCH64_FL_F64MM      (1ULL << 38)
223 
224 /* Flag Manipulation Instructions (FLAGM) extension.  */
225 #define AARCH64_FL_FLAGM      (1ULL << 39)
226 
227 /* Pointer Authentication (PAUTH) extension.  */
228 #define AARCH64_FL_PAUTH      (1ULL << 40)
229 
230 /* Armv9.0-A.  */
231 #define AARCH64_FL_V9         (1ULL << 41)  /* Armv9.0-A Architecture.  */
232 
233 /* 64-byte atomic load/store extensions.  */
234 #define AARCH64_FL_LS64      (1ULL << 42)
235 
236 /* Armv8.7-a architecture extensions.  */
237 #define AARCH64_FL_V8_7       (1ULL << 43)
238 
239 /* Hardware memory operation instructions.  */
240 #define AARCH64_FL_MOPS       (1ULL << 44)
241 
242 /* Armv8.8-a architecture extensions.  */
243 #define AARCH64_FL_V8_8       (1ULL << 45)
244 
245 /* Has FP and SIMD.  */
246 #define AARCH64_FL_FPSIMD     (AARCH64_FL_FP | AARCH64_FL_SIMD)
247 
248 /* Has FP without SIMD.  */
249 #define AARCH64_FL_FPQ16      (AARCH64_FL_FP & ~AARCH64_FL_SIMD)
250 
251 /* Architecture flags that effect instruction selection.  */
252 #define AARCH64_FL_FOR_ARCH8       (AARCH64_FL_FPSIMD)
253 #define AARCH64_FL_FOR_ARCH8_1			       \
254   (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC \
255    | AARCH64_FL_RDMA | AARCH64_FL_V8_1)
256 #define AARCH64_FL_FOR_ARCH8_2			\
257   (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2)
258 #define AARCH64_FL_FOR_ARCH8_3			\
259   (AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_V8_3 | AARCH64_FL_PAUTH \
260    | AARCH64_FL_RCPC)
261 #define AARCH64_FL_FOR_ARCH8_4			\
262   (AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_V8_4 | AARCH64_FL_F16FML \
263    | AARCH64_FL_DOTPROD | AARCH64_FL_RCPC8_4 | AARCH64_FL_FLAGM)
264 #define AARCH64_FL_FOR_ARCH8_5			\
265   (AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_V8_5	\
266    | AARCH64_FL_SB | AARCH64_FL_SSBS | AARCH64_FL_PREDRES)
267 #define AARCH64_FL_FOR_ARCH8_6			\
268   (AARCH64_FL_FOR_ARCH8_5 | AARCH64_FL_V8_6 | AARCH64_FL_FPSIMD \
269    | AARCH64_FL_I8MM | AARCH64_FL_BF16)
270 #define AARCH64_FL_FOR_ARCH8_7			\
271   (AARCH64_FL_FOR_ARCH8_6 | AARCH64_FL_V8_7)
272 #define AARCH64_FL_FOR_ARCH8_8			\
273   (AARCH64_FL_FOR_ARCH8_7 | AARCH64_FL_V8_8 | AARCH64_FL_MOPS)
274 
275 #define AARCH64_FL_FOR_ARCH8_R     \
276   (AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_V8_R)
277 #define AARCH64_FL_FOR_ARCH9       \
278   (AARCH64_FL_FOR_ARCH8_5 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_V9 \
279    | AARCH64_FL_F16)
280 
281 /* Macros to test ISA flags.  */
282 
283 #define AARCH64_ISA_CRC            (aarch64_isa_flags & AARCH64_FL_CRC)
284 #define AARCH64_ISA_CRYPTO         (aarch64_isa_flags & AARCH64_FL_CRYPTO)
285 #define AARCH64_ISA_FP             (aarch64_isa_flags & AARCH64_FL_FP)
286 #define AARCH64_ISA_SIMD           (aarch64_isa_flags & AARCH64_FL_SIMD)
287 #define AARCH64_ISA_LSE		   (aarch64_isa_flags & AARCH64_FL_LSE)
288 #define AARCH64_ISA_RDMA	   (aarch64_isa_flags & AARCH64_FL_RDMA)
289 #define AARCH64_ISA_V8_2	   (aarch64_isa_flags & AARCH64_FL_V8_2)
290 #define AARCH64_ISA_F16		   (aarch64_isa_flags & AARCH64_FL_F16)
291 #define AARCH64_ISA_SVE            (aarch64_isa_flags & AARCH64_FL_SVE)
292 #define AARCH64_ISA_SVE2	   (aarch64_isa_flags & AARCH64_FL_SVE2)
293 #define AARCH64_ISA_SVE2_AES	   (aarch64_isa_flags & AARCH64_FL_SVE2_AES)
294 #define AARCH64_ISA_SVE2_BITPERM  (aarch64_isa_flags & AARCH64_FL_SVE2_BITPERM)
295 #define AARCH64_ISA_SVE2_SHA3	   (aarch64_isa_flags & AARCH64_FL_SVE2_SHA3)
296 #define AARCH64_ISA_SVE2_SM4	   (aarch64_isa_flags & AARCH64_FL_SVE2_SM4)
297 #define AARCH64_ISA_V8_3	   (aarch64_isa_flags & AARCH64_FL_V8_3)
298 #define AARCH64_ISA_DOTPROD	   (aarch64_isa_flags & AARCH64_FL_DOTPROD)
299 #define AARCH64_ISA_AES	           (aarch64_isa_flags & AARCH64_FL_AES)
300 #define AARCH64_ISA_SHA2	   (aarch64_isa_flags & AARCH64_FL_SHA2)
301 #define AARCH64_ISA_V8_4	   (aarch64_isa_flags & AARCH64_FL_V8_4)
302 #define AARCH64_ISA_SM4	           (aarch64_isa_flags & AARCH64_FL_SM4)
303 #define AARCH64_ISA_SHA3	   (aarch64_isa_flags & AARCH64_FL_SHA3)
304 #define AARCH64_ISA_F16FML	   (aarch64_isa_flags & AARCH64_FL_F16FML)
305 #define AARCH64_ISA_RCPC	   (aarch64_isa_flags & AARCH64_FL_RCPC)
306 #define AARCH64_ISA_RCPC8_4	   (aarch64_isa_flags & AARCH64_FL_RCPC8_4)
307 #define AARCH64_ISA_RNG		   (aarch64_isa_flags & AARCH64_FL_RNG)
308 #define AARCH64_ISA_V8_5	   (aarch64_isa_flags & AARCH64_FL_V8_5)
309 #define AARCH64_ISA_TME		   (aarch64_isa_flags & AARCH64_FL_TME)
310 #define AARCH64_ISA_MEMTAG	   (aarch64_isa_flags & AARCH64_FL_MEMTAG)
311 #define AARCH64_ISA_V8_6	   (aarch64_isa_flags & AARCH64_FL_V8_6)
312 #define AARCH64_ISA_I8MM	   (aarch64_isa_flags & AARCH64_FL_I8MM)
313 #define AARCH64_ISA_F32MM	   (aarch64_isa_flags & AARCH64_FL_F32MM)
314 #define AARCH64_ISA_F64MM	   (aarch64_isa_flags & AARCH64_FL_F64MM)
315 #define AARCH64_ISA_BF16	   (aarch64_isa_flags & AARCH64_FL_BF16)
316 #define AARCH64_ISA_SB		   (aarch64_isa_flags & AARCH64_FL_SB)
317 #define AARCH64_ISA_V8_R	   (aarch64_isa_flags & AARCH64_FL_V8_R)
318 #define AARCH64_ISA_PAUTH	   (aarch64_isa_flags & AARCH64_FL_PAUTH)
319 #define AARCH64_ISA_V9		   (aarch64_isa_flags & AARCH64_FL_V9)
320 #define AARCH64_ISA_MOPS	   (aarch64_isa_flags & AARCH64_FL_MOPS)
321 #define AARCH64_ISA_LS64	   (aarch64_isa_flags & AARCH64_FL_LS64)
322 
323 /* Crypto is an optional extension to AdvSIMD.  */
324 #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
325 
326 /* SHA2 is an optional extension to AdvSIMD.  */
327 #define TARGET_SHA2 ((TARGET_SIMD && AARCH64_ISA_SHA2) || TARGET_CRYPTO)
328 
329 /* SHA3 is an optional extension to AdvSIMD.  */
330 #define TARGET_SHA3 (TARGET_SIMD && AARCH64_ISA_SHA3)
331 
332 /* AES is an optional extension to AdvSIMD.  */
333 #define TARGET_AES ((TARGET_SIMD && AARCH64_ISA_AES) || TARGET_CRYPTO)
334 
335 /* SM is an optional extension to AdvSIMD.  */
336 #define TARGET_SM4 (TARGET_SIMD && AARCH64_ISA_SM4)
337 
338 /* FP16FML is an optional extension to AdvSIMD.  */
339 #define TARGET_F16FML (TARGET_SIMD && AARCH64_ISA_F16FML && TARGET_FP_F16INST)
340 
341 /* CRC instructions that can be enabled through +crc arch extension.  */
342 #define TARGET_CRC32 (AARCH64_ISA_CRC)
343 
344 /* Atomic instructions that can be enabled through the +lse extension.  */
345 #define TARGET_LSE (AARCH64_ISA_LSE)
346 
347 /* ARMv8.2-A FP16 support that can be enabled through the +fp16 extension.  */
348 #define TARGET_FP_F16INST (TARGET_FLOAT && AARCH64_ISA_F16)
349 #define TARGET_SIMD_F16INST (TARGET_SIMD && AARCH64_ISA_F16)
350 
351 /* Dot Product is an optional extension to AdvSIMD enabled through +dotprod.  */
352 #define TARGET_DOTPROD (TARGET_SIMD && AARCH64_ISA_DOTPROD)
353 
354 /* SVE instructions, enabled through +sve.  */
355 #define TARGET_SVE (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SVE)
356 
357 /* SVE2 instructions, enabled through +sve2.  */
358 #define TARGET_SVE2 (TARGET_SVE && AARCH64_ISA_SVE2)
359 
360 /* SVE2 AES instructions, enabled through +sve2-aes.  */
361 #define TARGET_SVE2_AES (TARGET_SVE2 && AARCH64_ISA_SVE2_AES)
362 
363 /* SVE2 BITPERM instructions, enabled through +sve2-bitperm.  */
364 #define TARGET_SVE2_BITPERM (TARGET_SVE2 && AARCH64_ISA_SVE2_BITPERM)
365 
366 /* SVE2 SHA3 instructions, enabled through +sve2-sha3.  */
367 #define TARGET_SVE2_SHA3 (TARGET_SVE2 && AARCH64_ISA_SVE2_SHA3)
368 
369 /* SVE2 SM4 instructions, enabled through +sve2-sm4.  */
370 #define TARGET_SVE2_SM4 (TARGET_SVE2 && AARCH64_ISA_SVE2_SM4)
371 
372 /* ARMv8.3-A features.  */
373 #define TARGET_ARMV8_3	(AARCH64_ISA_V8_3)
374 
375 /* Javascript conversion instruction from Armv8.3-a.  */
376 #define TARGET_JSCVT	(TARGET_FLOAT && AARCH64_ISA_V8_3)
377 
378 /* Armv8.3-a Complex number extension to AdvSIMD extensions.  */
379 #define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3)
380 
381 /* Floating-point rounding instructions from Armv8.5-a.  */
382 #define TARGET_FRINT (AARCH64_ISA_V8_5 && TARGET_FLOAT)
383 
384 /* TME instructions are enabled.  */
385 #define TARGET_TME (AARCH64_ISA_TME)
386 
387 /* Random number instructions from Armv8.5-a.  */
388 #define TARGET_RNG (AARCH64_ISA_RNG)
389 
390 /* Memory Tagging instructions optional to Armv8.5 enabled through +memtag.  */
391 #define TARGET_MEMTAG (AARCH64_ISA_V8_5 && AARCH64_ISA_MEMTAG)
392 
393 /* I8MM instructions are enabled through +i8mm.  */
394 #define TARGET_I8MM (AARCH64_ISA_I8MM)
395 #define TARGET_SVE_I8MM (TARGET_SVE && AARCH64_ISA_I8MM)
396 
397 /* F32MM instructions are enabled through +f32mm.  */
398 #define TARGET_F32MM (AARCH64_ISA_F32MM)
399 #define TARGET_SVE_F32MM (TARGET_SVE && AARCH64_ISA_F32MM)
400 
401 /* F64MM instructions are enabled through +f64mm.  */
402 #define TARGET_F64MM (AARCH64_ISA_F64MM)
403 #define TARGET_SVE_F64MM (TARGET_SVE && AARCH64_ISA_F64MM)
404 
405 /* BF16 instructions are enabled through +bf16.  */
406 #define TARGET_BF16_FP (AARCH64_ISA_BF16)
407 #define TARGET_BF16_SIMD (AARCH64_ISA_BF16 && TARGET_SIMD)
408 #define TARGET_SVE_BF16 (TARGET_SVE && AARCH64_ISA_BF16)
409 
410 /* PAUTH instructions are enabled through +pauth.  */
411 #define TARGET_PAUTH (AARCH64_ISA_PAUTH)
412 
413 /* MOPS instructions are enabled through +mops.  */
414 #define TARGET_MOPS (AARCH64_ISA_MOPS)
415 
416 /* LS64 instructions are enabled through +ls64.  */
417 #define TARGET_LS64 (AARCH64_ISA_LS64)
418 
419 /* Make sure this is always defined so we don't have to check for ifdefs
420    but rather use normal ifs.  */
421 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
422 #define TARGET_FIX_ERR_A53_835769_DEFAULT 0
423 #else
424 #undef TARGET_FIX_ERR_A53_835769_DEFAULT
425 #define TARGET_FIX_ERR_A53_835769_DEFAULT 1
426 #endif
427 
428 /* SB instruction is enabled through +sb.  */
429 #define TARGET_SB (AARCH64_ISA_SB)
430 
431 /* Apply the workaround for Cortex-A53 erratum 835769.  */
432 #define TARGET_FIX_ERR_A53_835769	\
433   ((aarch64_fix_a53_err835769 == 2)	\
434   ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769)
435 
436 /* Make sure this is always defined so we don't have to check for ifdefs
437    but rather use normal ifs.  */
438 #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT
439 #define TARGET_FIX_ERR_A53_843419_DEFAULT 0
440 #else
441 #undef TARGET_FIX_ERR_A53_843419_DEFAULT
442 #define TARGET_FIX_ERR_A53_843419_DEFAULT 1
443 #endif
444 
445 /* Apply the workaround for Cortex-A53 erratum 843419.  */
446 #define TARGET_FIX_ERR_A53_843419	\
447   ((aarch64_fix_a53_err843419 == 2)	\
448   ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419)
449 
450 /* ARMv8.1-A Adv.SIMD support.  */
451 #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA)
452 
453 /* Standard register usage.  */
454 
455 /* 31 64-bit general purpose registers R0-R30:
456    R30		LR (link register)
457    R29		FP (frame pointer)
458    R19-R28	Callee-saved registers
459    R18		The platform register; use as temporary register.
460    R17		IP1 The second intra-procedure-call temporary register
461 		(can be used by call veneers and PLT code); otherwise use
462 		as a temporary register
463    R16		IP0 The first intra-procedure-call temporary register (can
464 		be used by call veneers and PLT code); otherwise use as a
465 		temporary register
466    R9-R15	Temporary registers
467    R8		Structure value parameter / temporary register
468    R0-R7	Parameter/result registers
469 
470    SP		stack pointer, encoded as X/R31 where permitted.
471    ZR		zero register, encoded as X/R31 elsewhere
472 
473    32 x 128-bit floating-point/vector registers
474    V16-V31	Caller-saved (temporary) registers
475    V8-V15	Callee-saved registers
476    V0-V7	Parameter/result registers
477 
478    The vector register V0 holds scalar B0, H0, S0 and D0 in its least
479    significant bits.  Unlike AArch32 S1 is not packed into D0, etc.
480 
481    P0-P7        Predicate low registers: valid in all predicate contexts
482    P8-P15       Predicate high registers: used as scratch space
483 
484    FFR		First Fault Register, a fixed-use SVE predicate register
485    FFRT		FFR token: a fake register used for modelling dependencies
486 
487    VG           Pseudo "vector granules" register
488 
489    VG is the number of 64-bit elements in an SVE vector.  We define
490    it as a hard register so that we can easily map it to the DWARF VG
491    register.  GCC internally uses the poly_int variable aarch64_sve_vg
492    instead.  */
493 
494 #define FIXED_REGISTERS					\
495   {							\
496     0, 0, 0, 0,   0, 0, 0, 0,	/* R0 - R7 */		\
497     0, 0, 0, 0,   0, 0, 0, 0,	/* R8 - R15 */		\
498     0, 0, 0, 0,   0, 0, 0, 0,	/* R16 - R23 */		\
499     0, 0, 0, 0,   0, 1, 0, 1,	/* R24 - R30, SP */	\
500     0, 0, 0, 0,   0, 0, 0, 0,   /* V0 - V7 */           \
501     0, 0, 0, 0,   0, 0, 0, 0,   /* V8 - V15 */		\
502     0, 0, 0, 0,   0, 0, 0, 0,   /* V16 - V23 */         \
503     0, 0, 0, 0,   0, 0, 0, 0,   /* V24 - V31 */         \
504     1, 1, 1, 1,			/* SFP, AP, CC, VG */	\
505     0, 0, 0, 0,   0, 0, 0, 0,   /* P0 - P7 */           \
506     0, 0, 0, 0,   0, 0, 0, 0,   /* P8 - P15 */          \
507     1, 1			/* FFR and FFRT */	\
508   }
509 
510 /* X30 is marked as caller-saved which is in line with regular function call
511    behavior since the call instructions clobber it; AARCH64_EXPAND_CALL does
512    that for regular function calls and avoids it for sibcalls.  X30 is
513    considered live for sibcalls; EPILOGUE_USES helps achieve that by returning
514    true but not until function epilogues have been generated.  This ensures
515    that X30 is available for use in leaf functions if needed.  */
516 
517 #define CALL_USED_REGISTERS				\
518   {							\
519     1, 1, 1, 1,   1, 1, 1, 1,	/* R0 - R7 */		\
520     1, 1, 1, 1,   1, 1, 1, 1,	/* R8 - R15 */		\
521     1, 1, 1, 0,   0, 0, 0, 0,	/* R16 - R23 */		\
522     0, 0, 0, 0,   0, 1, 1, 1,	/* R24 - R30, SP */	\
523     1, 1, 1, 1,   1, 1, 1, 1,	/* V0 - V7 */		\
524     0, 0, 0, 0,   0, 0, 0, 0,	/* V8 - V15 */		\
525     1, 1, 1, 1,   1, 1, 1, 1,   /* V16 - V23 */         \
526     1, 1, 1, 1,   1, 1, 1, 1,   /* V24 - V31 */         \
527     1, 1, 1, 1,			/* SFP, AP, CC, VG */	\
528     1, 1, 1, 1,   1, 1, 1, 1,	/* P0 - P7 */		\
529     1, 1, 1, 1,   1, 1, 1, 1,	/* P8 - P15 */		\
530     1, 1			/* FFR and FFRT */	\
531   }
532 
533 #define REGISTER_NAMES						\
534   {								\
535     "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",	\
536     "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",	\
537     "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",	\
538     "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp",	\
539     "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",	\
540     "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",	\
541     "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",	\
542     "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",	\
543     "sfp", "ap",  "cc",  "vg",					\
544     "p0",  "p1",  "p2",  "p3",  "p4",  "p5",  "p6",  "p7",	\
545     "p8",  "p9",  "p10", "p11", "p12", "p13", "p14", "p15",	\
546     "ffr", "ffrt"						\
547   }
548 
549 /* Generate the register aliases for core register N */
550 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \
551                      {"w" # N, R0_REGNUM + (N)}
552 
553 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \
554                      {"d" # N, V0_REGNUM + (N)}, \
555                      {"s" # N, V0_REGNUM + (N)}, \
556                      {"h" # N, V0_REGNUM + (N)}, \
557                      {"b" # N, V0_REGNUM + (N)}, \
558                      {"z" # N, V0_REGNUM + (N)}
559 
560 /* Provide aliases for all of the ISA defined register name forms.
561    These aliases are convenient for use in the clobber lists of inline
562    asm statements.  */
563 
564 #define ADDITIONAL_REGISTER_NAMES \
565   { R_ALIASES(0),  R_ALIASES(1),  R_ALIASES(2),  R_ALIASES(3),  \
566     R_ALIASES(4),  R_ALIASES(5),  R_ALIASES(6),  R_ALIASES(7),  \
567     R_ALIASES(8),  R_ALIASES(9),  R_ALIASES(10), R_ALIASES(11), \
568     R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \
569     R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \
570     R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \
571     R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \
572     R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \
573     V_ALIASES(0),  V_ALIASES(1),  V_ALIASES(2),  V_ALIASES(3),  \
574     V_ALIASES(4),  V_ALIASES(5),  V_ALIASES(6),  V_ALIASES(7),  \
575     V_ALIASES(8),  V_ALIASES(9),  V_ALIASES(10), V_ALIASES(11), \
576     V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \
577     V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \
578     V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \
579     V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \
580     V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31)  \
581   }
582 
583 #define EPILOGUE_USES(REGNO) (aarch64_epilogue_uses (REGNO))
584 
585 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
586    the stack pointer does not matter.  This is only true if the function
587    uses alloca.  */
588 #define EXIT_IGNORE_STACK	(cfun->calls_alloca)
589 
590 #define STATIC_CHAIN_REGNUM		R18_REGNUM
591 #define HARD_FRAME_POINTER_REGNUM	R29_REGNUM
592 #define FRAME_POINTER_REGNUM		SFP_REGNUM
593 #define STACK_POINTER_REGNUM		SP_REGNUM
594 #define ARG_POINTER_REGNUM		AP_REGNUM
595 #define FIRST_PSEUDO_REGISTER		(FFRT_REGNUM + 1)
596 
597 /* The number of argument registers available for each class.  */
598 #define NUM_ARG_REGS			8
599 #define NUM_FP_ARG_REGS			8
600 #define NUM_PR_ARG_REGS			4
601 
602 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
603    four members.  */
604 #define HA_MAX_NUM_FLDS		4
605 
606 /* External dwarf register number scheme.  These number are used to
607    identify registers in dwarf debug information, the values are
608    defined by the AArch64 ABI.  The numbering scheme is independent of
609    GCC's internal register numbering scheme.  */
610 
611 #define AARCH64_DWARF_R0        0
612 
613 /* The number of R registers, note 31! not 32.  */
614 #define AARCH64_DWARF_NUMBER_R 31
615 
616 #define AARCH64_DWARF_SP       31
617 #define AARCH64_DWARF_VG       46
618 #define AARCH64_DWARF_P0       48
619 #define AARCH64_DWARF_V0       64
620 
621 /* The number of V registers.  */
622 #define AARCH64_DWARF_NUMBER_V 32
623 
624 /* For signal frames we need to use an alternative return column.  This
625    value must not correspond to a hard register and must be out of the
626    range of DWARF_FRAME_REGNUM().  */
627 #define DWARF_ALT_FRAME_RETURN_COLUMN   \
628   (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V)
629 
630 /* We add 1 extra frame register for use as the
631    DWARF_ALT_FRAME_RETURN_COLUMN.  */
632 #define DWARF_FRAME_REGISTERS           (DWARF_ALT_FRAME_RETURN_COLUMN + 1)
633 
634 
635 #define DBX_REGISTER_NUMBER(REGNO)	aarch64_dbx_register_number (REGNO)
636 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders
637    can use DWARF_ALT_FRAME_RETURN_COLUMN defined below.  This is just the same
638    as the default definition in dwarf2out.cc.  */
639 #undef DWARF_FRAME_REGNUM
640 #define DWARF_FRAME_REGNUM(REGNO)	DBX_REGISTER_NUMBER (REGNO)
641 
642 #define DWARF_FRAME_RETURN_COLUMN	DWARF_FRAME_REGNUM (LR_REGNUM)
643 
644 #define DWARF2_UNWIND_INFO 1
645 
646 /* Use R0 through R3 to pass exception handling information.  */
647 #define EH_RETURN_DATA_REGNO(N) \
648   ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM)
649 
650 /* Select a format to encode pointers in exception handling data.  */
651 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
652   aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL))
653 
654 /* Output the assembly strings we want to add to a function definition.  */
655 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL)	\
656   aarch64_declare_function_name (STR, NAME, DECL)
657 
658 /* Output assembly strings for alias definition.  */
659 #define ASM_OUTPUT_DEF_FROM_DECLS(STR, DECL, TARGET) \
660   aarch64_asm_output_alias (STR, DECL, TARGET)
661 
662 /* Output assembly strings for undefined extern symbols.  */
663 #undef ASM_OUTPUT_EXTERNAL
664 #define ASM_OUTPUT_EXTERNAL(STR, DECL, NAME) \
665   aarch64_asm_output_external (STR, DECL, NAME)
666 
667 /* Output assembly strings after .cfi_startproc is emitted.  */
668 #define ASM_POST_CFI_STARTPROC  aarch64_post_cfi_startproc
669 
670 /* For EH returns X4 contains the stack adjustment.  */
671 #define EH_RETURN_STACKADJ_RTX	gen_rtx_REG (Pmode, R4_REGNUM)
672 #define EH_RETURN_HANDLER_RTX  aarch64_eh_return_handler_rtx ()
673 
674 /* Don't use __builtin_setjmp until we've defined it.  */
675 #undef DONT_USE_BUILTIN_SETJMP
676 #define DONT_USE_BUILTIN_SETJMP 1
677 
678 #undef TARGET_COMPUTE_FRAME_LAYOUT
679 #define TARGET_COMPUTE_FRAME_LAYOUT aarch64_layout_frame
680 
681 /* Register in which the structure value is to be returned.  */
682 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM
683 
684 /* Non-zero if REGNO is part of the Core register set.
685 
686    The rather unusual way of expressing this check is to avoid
687    warnings when building the compiler when R0_REGNUM is 0 and REGNO
688    is unsigned.  */
689 #define GP_REGNUM_P(REGNO)						\
690   (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM))
691 
692 /* Registers known to be preserved over a BL instruction.  This consists of the
693    GENERAL_REGS without x16, x17, and x30.  The x30 register is changed by the
694    BL instruction itself, while the x16 and x17 registers may be used by
695    veneers which can be inserted by the linker.  */
696 #define STUB_REGNUM_P(REGNO) \
697   (GP_REGNUM_P (REGNO) \
698    && (REGNO) != R16_REGNUM \
699    && (REGNO) != R17_REGNUM \
700    && (REGNO) != R30_REGNUM) \
701 
702 #define FP_REGNUM_P(REGNO)			\
703   (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM))
704 
705 #define FP_LO_REGNUM_P(REGNO)            \
706   (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM))
707 
708 #define FP_LO8_REGNUM_P(REGNO)            \
709   (((unsigned) (REGNO - V0_REGNUM)) <= (V7_REGNUM - V0_REGNUM))
710 
711 #define PR_REGNUM_P(REGNO)\
712   (((unsigned) (REGNO - P0_REGNUM)) <= (P15_REGNUM - P0_REGNUM))
713 
714 #define PR_LO_REGNUM_P(REGNO)\
715   (((unsigned) (REGNO - P0_REGNUM)) <= (P7_REGNUM - P0_REGNUM))
716 
717 #define FP_SIMD_SAVED_REGNUM_P(REGNO)			\
718   (((unsigned) (REGNO - V8_REGNUM)) <= (V23_REGNUM - V8_REGNUM))
719 
720 /* Register and constant classes.  */
721 
722 enum reg_class
723 {
724   NO_REGS,
725   TAILCALL_ADDR_REGS,
726   STUB_REGS,
727   GENERAL_REGS,
728   STACK_REG,
729   POINTER_REGS,
730   FP_LO8_REGS,
731   FP_LO_REGS,
732   FP_REGS,
733   POINTER_AND_FP_REGS,
734   PR_LO_REGS,
735   PR_HI_REGS,
736   PR_REGS,
737   FFR_REGS,
738   PR_AND_FFR_REGS,
739   ALL_REGS,
740   LIM_REG_CLASSES		/* Last */
741 };
742 
743 #define N_REG_CLASSES	((int) LIM_REG_CLASSES)
744 
745 #define REG_CLASS_NAMES				\
746 {						\
747   "NO_REGS",					\
748   "TAILCALL_ADDR_REGS",				\
749   "STUB_REGS",					\
750   "GENERAL_REGS",				\
751   "STACK_REG",					\
752   "POINTER_REGS",				\
753   "FP_LO8_REGS",				\
754   "FP_LO_REGS",					\
755   "FP_REGS",					\
756   "POINTER_AND_FP_REGS",			\
757   "PR_LO_REGS",					\
758   "PR_HI_REGS",					\
759   "PR_REGS",					\
760   "FFR_REGS",					\
761   "PR_AND_FFR_REGS",				\
762   "ALL_REGS"					\
763 }
764 
765 #define REG_CLASS_CONTENTS						\
766 {									\
767   { 0x00000000, 0x00000000, 0x00000000 },	/* NO_REGS */		\
768   { 0x00030000, 0x00000000, 0x00000000 },	/* TAILCALL_ADDR_REGS */\
769   { 0x3ffcffff, 0x00000000, 0x00000000 },	/* STUB_REGS */		\
770   { 0x7fffffff, 0x00000000, 0x00000003 },	/* GENERAL_REGS */	\
771   { 0x80000000, 0x00000000, 0x00000000 },	/* STACK_REG */		\
772   { 0xffffffff, 0x00000000, 0x00000003 },	/* POINTER_REGS */	\
773   { 0x00000000, 0x000000ff, 0x00000000 },       /* FP_LO8_REGS  */	\
774   { 0x00000000, 0x0000ffff, 0x00000000 },       /* FP_LO_REGS  */	\
775   { 0x00000000, 0xffffffff, 0x00000000 },       /* FP_REGS  */		\
776   { 0xffffffff, 0xffffffff, 0x00000003 },	/* POINTER_AND_FP_REGS */\
777   { 0x00000000, 0x00000000, 0x00000ff0 },	/* PR_LO_REGS */	\
778   { 0x00000000, 0x00000000, 0x000ff000 },	/* PR_HI_REGS */	\
779   { 0x00000000, 0x00000000, 0x000ffff0 },	/* PR_REGS */		\
780   { 0x00000000, 0x00000000, 0x00300000 },	/* FFR_REGS */		\
781   { 0x00000000, 0x00000000, 0x003ffff0 },	/* PR_AND_FFR_REGS */	\
782   { 0xffffffff, 0xffffffff, 0x000fffff }	/* ALL_REGS */		\
783 }
784 
785 #define REGNO_REG_CLASS(REGNO)	aarch64_regno_regclass (REGNO)
786 
787 #define INDEX_REG_CLASS	GENERAL_REGS
788 #define BASE_REG_CLASS  POINTER_REGS
789 
790 /* Register pairs used to eliminate unneeded registers that point into
791    the stack frame.  */
792 #define ELIMINABLE_REGS							\
793 {									\
794   { ARG_POINTER_REGNUM,		STACK_POINTER_REGNUM		},	\
795   { ARG_POINTER_REGNUM,		HARD_FRAME_POINTER_REGNUM	},	\
796   { FRAME_POINTER_REGNUM,	STACK_POINTER_REGNUM		},	\
797   { FRAME_POINTER_REGNUM,	HARD_FRAME_POINTER_REGNUM	},	\
798 }
799 
800 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
801   (OFFSET) = aarch64_initial_elimination_offset (FROM, TO)
802 
803 /* CPU/ARCH option handling.  */
804 #include "config/aarch64/aarch64-opts.h"
805 
806 enum target_cpus
807 {
808 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
809   TARGET_CPU_##INTERNAL_IDENT,
810 #include "aarch64-cores.def"
811   TARGET_CPU_generic
812 };
813 
814 /* Define how many bits are used to represent the CPU in TARGET_CPU_DEFAULT.
815    This needs to be big enough to fit the value of TARGET_CPU_generic.
816    All bits after this are used to represent the AARCH64_CPU_DEFAULT_FLAGS.  */
817 #define TARGET_CPU_NBITS 8
818 #define TARGET_CPU_MASK ((1 << TARGET_CPU_NBITS) - 1)
819 
820 /* If there is no CPU defined at configure, use generic as default.  */
821 #ifndef TARGET_CPU_DEFAULT
822 #define TARGET_CPU_DEFAULT \
823   (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << TARGET_CPU_NBITS))
824 #endif
825 
826 /* If inserting NOP before a mult-accumulate insn remember to adjust the
827    length so that conditional branching code is updated appropriately.  */
828 #define ADJUST_INSN_LENGTH(insn, length)	\
829   do						\
830     {						\
831        if (aarch64_madd_needs_nop (insn))	\
832          length += 4;				\
833     } while (0)
834 
835 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)	\
836     aarch64_final_prescan_insn (INSN);			\
837 
838 /* The processor for which instructions should be scheduled.  */
839 extern enum aarch64_processor aarch64_tune;
840 
841 /* RTL generation support.  */
842 #define INIT_EXPANDERS aarch64_init_expanders ()
843 
844 
845 /* Stack layout; function entry, exit and calling.  */
846 #define STACK_GROWS_DOWNWARD	1
847 
848 #define FRAME_GROWS_DOWNWARD	1
849 
850 #define ACCUMULATE_OUTGOING_ARGS	1
851 
852 #define FIRST_PARM_OFFSET(FNDECL) 0
853 
854 /* Fix for VFP */
855 #define LIBCALL_VALUE(MODE)  \
856   gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM)
857 
858 #define DEFAULT_PCC_STRUCT_RETURN 0
859 
860 #ifdef HAVE_POLY_INT_H
861 struct GTY (()) aarch64_frame
862 {
863   /* The offset from the bottom of the static frame (the bottom of the
864      outgoing arguments) of each register save slot, or -2 if no save is
865      needed.  */
866   poly_int64 reg_offset[LAST_SAVED_REGNUM + 1];
867 
868   /* The number of extra stack bytes taken up by register varargs.
869      This area is allocated by the callee at the very top of the
870      frame.  This value is rounded up to a multiple of
871      STACK_BOUNDARY.  */
872   HOST_WIDE_INT saved_varargs_size;
873 
874   /* The number of bytes between the bottom of the static frame (the bottom
875      of the outgoing arguments) and the bottom of the register save area.
876      This value is always a multiple of STACK_BOUNDARY.  */
877   poly_int64 bytes_below_saved_regs;
878 
879   /* The number of bytes between the bottom of the static frame (the bottom
880      of the outgoing arguments) and the hard frame pointer.  This value is
881      always a multiple of STACK_BOUNDARY.  */
882   poly_int64 bytes_below_hard_fp;
883 
884   /* The number of bytes between the top of the locals area and the top
885      of the frame (the incomming SP).  This value is always a multiple of
886      STACK_BOUNDARY.  */
887   poly_int64 bytes_above_locals;
888 
889   /* The number of bytes between the hard_frame_pointer and the top of
890      the frame (the incomming SP).  This value is always a multiple of
891      STACK_BOUNDARY.  */
892   poly_int64 bytes_above_hard_fp;
893 
894   /* The size of the frame, i.e. the number of bytes between the bottom
895      of the outgoing arguments and the incoming SP.  This value is always
896      a multiple of STACK_BOUNDARY.  */
897   poly_int64 frame_size;
898 
899   /* The size of the initial stack adjustment before saving callee-saves.  */
900   poly_int64 initial_adjust;
901 
902   /* The writeback value when pushing callee-save registers.
903      It is zero when no push is used.  */
904   HOST_WIDE_INT callee_adjust;
905 
906   /* The size of the stack adjustment before saving or after restoring
907      SVE registers.  */
908   poly_int64 sve_callee_adjust;
909 
910   /* The size of the stack adjustment after saving callee-saves.  */
911   poly_int64 final_adjust;
912 
913   /* Store FP,LR and setup a frame pointer.  */
914   bool emit_frame_chain;
915 
916   /* In each frame, we can associate up to two register saves with the
917      initial stack allocation.  This happens in one of two ways:
918 
919      (1) Using an STR or STP with writeback to perform the initial
920 	 stack allocation.  When EMIT_FRAME_CHAIN, the registers will
921 	 be those needed to create a frame chain.
922 
923 	 Indicated by CALLEE_ADJUST != 0.
924 
925      (2) Using a separate STP to set up the frame record, after the
926 	 initial stack allocation but before setting up the frame pointer.
927 	 This is used if the offset is too large to use writeback.
928 
929 	 Indicated by CALLEE_ADJUST == 0 && EMIT_FRAME_CHAIN.
930 
931      These fields indicate which registers we've decided to handle using
932      (1) or (2), or INVALID_REGNUM if none.
933 
934      In some cases we don't always need to pop all registers in the push
935      candidates, pop candidates record which registers need to be popped
936      eventually.  The initial value of a pop candidate is copied from its
937      corresponding push candidate.
938 
939      Currently, different pop candidates are only used for shadow call
940      stack.  When "-fsanitize=shadow-call-stack" is specified, we replace
941      x30 in the pop candidate with INVALID_REGNUM to ensure that x30 is
942      not popped twice.  */
943   unsigned wb_push_candidate1;
944   unsigned wb_push_candidate2;
945   unsigned wb_pop_candidate1;
946   unsigned wb_pop_candidate2;
947 
948   /* Big-endian SVE frames need a spare predicate register in order
949      to save vector registers in the correct layout for unwinding.
950      This is the register they should use.  */
951   unsigned spare_pred_reg;
952 
953   /* An SVE register that is saved below the hard frame pointer and that acts
954      as a probe for later allocations, or INVALID_REGNUM if none.  */
955   unsigned sve_save_and_probe;
956 
957   /* A register that is saved at the hard frame pointer and that acts
958      as a probe for later allocations, or INVALID_REGNUM if none.  */
959   unsigned hard_fp_save_and_probe;
960 
961   bool laid_out;
962 
963   /* True if shadow call stack should be enabled for the current function.  */
964   bool is_scs_enabled;
965 };
966 
967 #ifdef hash_set_h
968 typedef struct GTY (()) machine_function
969 {
970   struct aarch64_frame frame;
971   /* One entry for each hard register.  */
972   bool reg_is_wrapped_separately[LAST_SAVED_REGNUM];
973   /* One entry for each general purpose register.  */
974   rtx call_via[SP_REGNUM];
975   bool label_is_assembled;
976   /* A set of all decls that have been passed to a vld1 intrinsic in the
977      current function.  This is used to help guide the vector cost model.  */
978   hash_set<tree> *vector_load_decls;
979 } machine_function;
980 #endif
981 #endif
982 
983 /* Which ABI to use.  */
984 enum aarch64_abi_type
985 {
986   AARCH64_ABI_LP64 = 0,
987   AARCH64_ABI_ILP32 = 1
988 };
989 
990 #ifndef AARCH64_ABI_DEFAULT
991 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64
992 #endif
993 
994 #define TARGET_ILP32	(aarch64_abi & AARCH64_ABI_ILP32)
995 
996 enum arm_pcs
997 {
998   ARM_PCS_AAPCS64,		/* Base standard AAPCS for 64 bit.  */
999   ARM_PCS_SIMD,			/* For aarch64_vector_pcs functions.  */
1000   ARM_PCS_SVE,			/* For functions that pass or return
1001 				   values in SVE registers.  */
1002   ARM_PCS_TLSDESC,		/* For targets of tlsdesc calls.  */
1003   ARM_PCS_UNKNOWN
1004 };
1005 
1006 
1007 
1008 
1009 /* We can't use machine_mode inside a generator file because it
1010    hasn't been created yet; we shouldn't be using any code that
1011    needs the real definition though, so this ought to be safe.  */
1012 #ifdef GENERATOR_FILE
1013 #define MACHMODE int
1014 #else
1015 #include "insn-modes.h"
1016 #define MACHMODE machine_mode
1017 #endif
1018 
1019 #ifndef USED_FOR_TARGET
1020 /* AAPCS related state tracking.  */
1021 typedef struct
1022 {
1023   enum arm_pcs pcs_variant;
1024   int aapcs_arg_processed;	/* No need to lay out this argument again.  */
1025   int aapcs_ncrn;		/* Next Core register number.  */
1026   int aapcs_nextncrn;		/* Next next core register number.  */
1027   int aapcs_nvrn;		/* Next Vector register number.  */
1028   int aapcs_nextnvrn;		/* Next Next Vector register number.  */
1029   int aapcs_nprn;		/* Next Predicate register number.  */
1030   int aapcs_nextnprn;		/* Next Next Predicate register number.  */
1031   rtx aapcs_reg;		/* Register assigned to this argument.  This
1032 				   is NULL_RTX if this parameter goes on
1033 				   the stack.  */
1034   MACHMODE aapcs_vfp_rmode;
1035   int aapcs_stack_words;	/* If the argument is passed on the stack, this
1036 				   is the number of words needed, after rounding
1037 				   up.  Only meaningful when
1038 				   aapcs_reg == NULL_RTX.  */
1039   int aapcs_stack_size;		/* The total size (in words, per 8 byte) of the
1040 				   stack arg area so far.  */
1041   bool silent_p;		/* True if we should act silently, rather than
1042 				   raise an error for invalid calls.  */
1043 } CUMULATIVE_ARGS;
1044 #endif
1045 
1046 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1047   (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD)
1048 
1049 #define PAD_VARARGS_DOWN	0
1050 
1051 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1052   aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS)
1053 
1054 #define FUNCTION_ARG_REGNO_P(REGNO) \
1055   aarch64_function_arg_regno_p(REGNO)
1056 
1057 
1058 /* ISA Features.  */
1059 
1060 /* Addressing modes, etc.  */
1061 #define HAVE_POST_INCREMENT	1
1062 #define HAVE_PRE_INCREMENT	1
1063 #define HAVE_POST_DECREMENT	1
1064 #define HAVE_PRE_DECREMENT	1
1065 #define HAVE_POST_MODIFY_DISP	1
1066 #define HAVE_PRE_MODIFY_DISP	1
1067 
1068 #define MAX_REGS_PER_ADDRESS	2
1069 
1070 #define CONSTANT_ADDRESS_P(X)		aarch64_constant_address_p(X)
1071 
1072 #define REGNO_OK_FOR_BASE_P(REGNO)	\
1073   aarch64_regno_ok_for_base_p (REGNO, true)
1074 
1075 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1076   aarch64_regno_ok_for_index_p (REGNO, true)
1077 
1078 #define LEGITIMATE_PIC_OPERAND_P(X) \
1079   aarch64_legitimate_pic_operand_p (X)
1080 
1081 #define CASE_VECTOR_MODE Pmode
1082 
1083 #define DEFAULT_SIGNED_CHAR 0
1084 
1085 /* An integer expression for the size in bits of the largest integer machine
1086    mode that should actually be used.  We allow pairs of registers.  */
1087 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1088 
1089 /* Maximum bytes moved by a single instruction (load/store pair).  */
1090 #define MOVE_MAX (UNITS_PER_WORD * 2)
1091 
1092 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends.  */
1093 #define AARCH64_CALL_RATIO 8
1094 
1095 /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure.
1096    move_by_pieces will continually copy the largest safe chunks.  So a
1097    7-byte copy is a 4-byte + 2-byte + byte copy.  This proves inefficient
1098    for both size and speed of copy, so we will instead use the "cpymem"
1099    standard name to implement the copy.  This logic does not apply when
1100    targeting -mstrict-align or TARGET_MOPS, so keep a sensible default in
1101    that case.  */
1102 #define MOVE_RATIO(speed) \
1103   ((!STRICT_ALIGNMENT || TARGET_MOPS) ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2))
1104 
1105 /* Like MOVE_RATIO, without -mstrict-align, make decisions in "setmem" when
1106    we would use more than 3 scalar instructions.
1107    Otherwise follow a sensible default: when optimizing for size, give a better
1108    estimate of the length of a memset call, but use the default otherwise.  */
1109 #define CLEAR_RATIO(speed) \
1110   (!STRICT_ALIGNMENT ? (TARGET_MOPS ? 0 : 4) : (speed) ? 15 : AARCH64_CALL_RATIO)
1111 
1112 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant.  Without
1113    -mstrict-align, make decisions in "setmem".  Otherwise follow a sensible
1114    default: when optimizing for size adjust the ratio to account for the
1115    overhead of loading the constant.  */
1116 #define SET_RATIO(speed) \
1117   ((!STRICT_ALIGNMENT || TARGET_MOPS) ? 0 : (speed) ? 15 : AARCH64_CALL_RATIO - 2)
1118 
1119 /* Disable auto-increment in move_by_pieces et al.  Use of auto-increment is
1120    rarely a good idea in straight-line code since it adds an extra address
1121    dependency between each instruction.  Better to use incrementing offsets.  */
1122 #define USE_LOAD_POST_INCREMENT(MODE)   0
1123 #define USE_LOAD_POST_DECREMENT(MODE)   0
1124 #define USE_LOAD_PRE_INCREMENT(MODE)    0
1125 #define USE_LOAD_PRE_DECREMENT(MODE)    0
1126 #define USE_STORE_POST_INCREMENT(MODE)  0
1127 #define USE_STORE_POST_DECREMENT(MODE)  0
1128 #define USE_STORE_PRE_INCREMENT(MODE)   0
1129 #define USE_STORE_PRE_DECREMENT(MODE)   0
1130 
1131 /* WORD_REGISTER_OPERATIONS does not hold for AArch64.
1132    The assigned word_mode is DImode but operations narrower than SImode
1133    behave as 32-bit operations if using the W-form of the registers rather
1134    than as word_mode (64-bit) operations as WORD_REGISTER_OPERATIONS
1135    expects.  */
1136 #define WORD_REGISTER_OPERATIONS 0
1137 
1138 /* Define if loading from memory in MODE, an integral mode narrower than
1139    BITS_PER_WORD will either zero-extend or sign-extend.  The value of this
1140    macro should be the code that says which one of the two operations is
1141    implicitly done, or UNKNOWN if none.  */
1142 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1143 
1144 /* Define this macro to be non-zero if instructions will fail to work
1145    if given data not on the nominal alignment.  */
1146 #define STRICT_ALIGNMENT		TARGET_STRICT_ALIGN
1147 
1148 /* Enable wide bitfield accesses for more efficient bitfield code.  */
1149 #define SLOW_BYTE_ACCESS 1
1150 
1151 #define NO_FUNCTION_CSE	1
1152 
1153 /* Specify the machine mode that the hardware addresses have.
1154    After generation of rtl, the compiler makes no further distinction
1155    between pointers and any other objects of this machine mode.  */
1156 #define Pmode		DImode
1157 
1158 /* A C expression whose value is zero if pointers that need to be extended
1159    from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and
1160    greater then zero if they are zero-extended and less then zero if the
1161    ptr_extend instruction should be used.  */
1162 #define POINTERS_EXTEND_UNSIGNED 1
1163 
1164 /* Mode of a function address in a call instruction (for indexing purposes).  */
1165 #define FUNCTION_MODE	Pmode
1166 
1167 #define SELECT_CC_MODE(OP, X, Y)	aarch64_select_cc_mode (OP, X, Y)
1168 
1169 /* Having an integer comparison mode guarantees that we can use
1170    reverse_condition, but the usual restrictions apply to floating-point
1171    comparisons.  */
1172 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPmode && (MODE) != CCFPEmode)
1173 
1174 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1175   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1176 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1177   ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1178 
1179 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
1180 
1181 #define RETURN_ADDR_RTX aarch64_return_addr
1182 
1183 /* BTI c + 3 insns
1184    + sls barrier of DSB + ISB.
1185    + 2 pointer-sized entries.  */
1186 #define TRAMPOLINE_SIZE	(24 + (TARGET_ILP32 ? 8 : 16))
1187 
1188 /* Trampolines contain dwords, so must be dword aligned.  */
1189 #define TRAMPOLINE_ALIGNMENT 64
1190 
1191 /* Put trampolines in the text section so that mapping symbols work
1192    correctly.  */
1193 #define TRAMPOLINE_SECTION text_section
1194 
1195 /* To start with.  */
1196 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \
1197   (aarch64_branch_cost (SPEED_P, PREDICTABLE_P))
1198 
1199 
1200 /* Assembly output.  */
1201 
1202 /* For now we'll make all jump tables pc-relative.  */
1203 #define CASE_VECTOR_PC_RELATIVE	1
1204 
1205 #define CASE_VECTOR_SHORTEN_MODE(min, max, body)	\
1206   ((min < -0x1fff0 || max > 0x1fff0) ? SImode		\
1207    : (min < -0x1f0 || max > 0x1f0) ? HImode		\
1208    : QImode)
1209 
1210 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL.  */
1211 #define ADDR_VEC_ALIGN(JUMPTABLE) 0
1212 
1213 #define MCOUNT_NAME "_mcount"
1214 
1215 #define NO_PROFILE_COUNTERS 1
1216 
1217 /* Emit rtl for profiling.  Output assembler code to FILE
1218    to call "_mcount" for profiling a function entry.  */
1219 #define PROFILE_HOOK(LABEL)						\
1220   {									\
1221     rtx fun, lr;							\
1222     lr = aarch64_return_addr_rtx ();					\
1223     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);			\
1224     emit_library_call (fun, LCT_NORMAL, VOIDmode, lr, Pmode);		\
1225   }
1226 
1227 /* All the work done in PROFILE_HOOK, but still required.  */
1228 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
1229 
1230 /* For some reason, the Linux headers think they know how to define
1231    these macros.  They don't!!!  */
1232 #undef ASM_APP_ON
1233 #undef ASM_APP_OFF
1234 #define ASM_APP_ON	"\t" ASM_COMMENT_START " Start of user assembly\n"
1235 #define ASM_APP_OFF	"\t" ASM_COMMENT_START " End of user assembly\n"
1236 
1237 #define CONSTANT_POOL_BEFORE_FUNCTION 0
1238 
1239 /* This definition should be relocated to aarch64-elf-raw.h.  This macro
1240    should be undefined in aarch64-linux.h and a clear_cache pattern
1241    implmented to emit either the call to __aarch64_sync_cache_range()
1242    directly or preferably the appropriate sycall or cache clear
1243    instructions inline.  */
1244 #define CLEAR_INSN_CACHE(beg, end)				\
1245   extern void  __aarch64_sync_cache_range (void *, void *);	\
1246   __aarch64_sync_cache_range (beg, end)
1247 
1248 #define SHIFT_COUNT_TRUNCATED (!TARGET_SIMD)
1249 
1250 /* Choose appropriate mode for caller saves, so we do the minimum
1251    required size of load/store.  */
1252 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1253   aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE))
1254 
1255 #undef SWITCHABLE_TARGET
1256 #define SWITCHABLE_TARGET 1
1257 
1258 /* Check TLS Descriptors mechanism is selected.  */
1259 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS)
1260 
1261 extern enum aarch64_code_model aarch64_cmodel;
1262 
1263 /* When using the tiny addressing model conditional and unconditional branches
1264    can span the whole of the available address space (1MB).  */
1265 #define HAS_LONG_COND_BRANCH				\
1266   (aarch64_cmodel == AARCH64_CMODEL_TINY		\
1267    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
1268 
1269 #define HAS_LONG_UNCOND_BRANCH				\
1270   (aarch64_cmodel == AARCH64_CMODEL_TINY		\
1271    || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC)
1272 
1273 #define TARGET_SUPPORTS_WIDE_INT 1
1274 
1275 /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register.  */
1276 #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \
1277   ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \
1278    || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \
1279    || (MODE) == DFmode || (MODE) == V4BFmode)
1280 
1281 /* Modes valid for AdvSIMD Q registers.  */
1282 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \
1283   ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \
1284    || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \
1285    || (MODE) == V2DFmode || (MODE) == V8BFmode)
1286 
1287 #define ENDIAN_LANE_N(NUNITS, N) \
1288   (BYTES_BIG_ENDIAN ? NUNITS - 1 - N : N)
1289 
1290 /* Support for configure-time --with-arch, --with-cpu and --with-tune.
1291    --with-arch and --with-cpu are ignored if either -mcpu or -march is used.
1292    --with-tune is ignored if either -mtune or -mcpu is used (but is not
1293    affected by -march).  */
1294 #define OPTION_DEFAULT_SPECS				\
1295   {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" },	\
1296   {"cpu",  "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" },   \
1297   {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}"},
1298 
1299 #define MCPU_TO_MARCH_SPEC \
1300    " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}"
1301 
1302 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv);
1303 #define MCPU_TO_MARCH_SPEC_FUNCTIONS \
1304   { "rewrite_mcpu", aarch64_rewrite_mcpu },
1305 
1306 #if defined(__aarch64__) && (defined(__linux__) || defined(__NetBSD__))
1307 extern const char *host_detect_local_cpu (int argc, const char **argv);
1308 #define HAVE_LOCAL_CPU_DETECT
1309 # define EXTRA_SPEC_FUNCTIONS						\
1310   { "local_cpu_detect", host_detect_local_cpu },			\
1311   MCPU_TO_MARCH_SPEC_FUNCTIONS
1312 
1313 # define MCPU_MTUNE_NATIVE_SPECS					\
1314    " %{march=native:%<march=native %:local_cpu_detect(arch)}"		\
1315    " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}"		\
1316    " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
1317 #else
1318 # define MCPU_MTUNE_NATIVE_SPECS ""
1319 # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS
1320 #endif
1321 
1322 #define ASM_CPU_SPEC \
1323    MCPU_TO_MARCH_SPEC
1324 
1325 #define EXTRA_SPECS						\
1326   { "asm_cpu_spec",		ASM_CPU_SPEC }
1327 
1328 #define ASM_OUTPUT_POOL_EPILOGUE  aarch64_asm_output_pool_epilogue
1329 
1330 /* This type is the user-visible __fp16, and a pointer to that type.  We
1331    need it in many places in the backend.  Defined in aarch64-builtins.cc.  */
1332 extern GTY(()) tree aarch64_fp16_type_node;
1333 extern GTY(()) tree aarch64_fp16_ptr_type_node;
1334 
1335 /* This type is the user-visible __bf16, and a pointer to that type.  Defined
1336    in aarch64-builtins.cc.  */
1337 extern GTY(()) tree aarch64_bf16_type_node;
1338 extern GTY(()) tree aarch64_bf16_ptr_type_node;
1339 
1340 /* The generic unwind code in libgcc does not initialize the frame pointer.
1341    So in order to unwind a function using a frame pointer, the very first
1342    function that is unwound must save the frame pointer.  That way the frame
1343    pointer is restored and its value is now valid - otherwise _Unwind_GetGR
1344    crashes.  Libgcc can now be safely built with -fomit-frame-pointer.  */
1345 #define LIBGCC2_UNWIND_ATTRIBUTE \
1346   __attribute__((optimize ("no-omit-frame-pointer")))
1347 
1348 #ifndef USED_FOR_TARGET
1349 extern poly_uint16 aarch64_sve_vg;
1350 
1351 /* The number of bits and bytes in an SVE vector.  */
1352 #define BITS_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 64))
1353 #define BYTES_PER_SVE_VECTOR (poly_uint16 (aarch64_sve_vg * 8))
1354 
1355 /* The number of bits and bytes in an SVE predicate.  */
1356 #define BITS_PER_SVE_PRED BYTES_PER_SVE_VECTOR
1357 #define BYTES_PER_SVE_PRED aarch64_sve_vg
1358 
1359 /* The SVE mode for a vector of bytes.  */
1360 #define SVE_BYTE_MODE VNx16QImode
1361 
1362 /* The maximum number of bytes in a fixed-size vector.  This is 256 bytes
1363    (for -msve-vector-bits=2048) multiplied by the maximum number of
1364    vectors in a structure mode (4).
1365 
1366    This limit must not be used for variable-size vectors, since
1367    VL-agnostic code must work with arbitary vector lengths.  */
1368 #define MAX_COMPILE_TIME_VEC_BYTES (256 * 4)
1369 #endif
1370 
1371 #define REGMODE_NATURAL_SIZE(MODE) aarch64_regmode_natural_size (MODE)
1372 
1373 /* Allocate a minimum of STACK_CLASH_MIN_BYTES_OUTGOING_ARGS bytes for the
1374    outgoing arguments if stack clash protection is enabled.  This is essential
1375    as the extra arg space allows us to skip a check in alloca.  */
1376 #undef STACK_DYNAMIC_OFFSET
1377 #define STACK_DYNAMIC_OFFSET(FUNDECL)			   \
1378    ((flag_stack_clash_protection			   \
1379      && cfun->calls_alloca				   \
1380      && known_lt (crtl->outgoing_args_size,		   \
1381 		  STACK_CLASH_MIN_BYTES_OUTGOING_ARGS))    \
1382     ? ROUND_UP (STACK_CLASH_MIN_BYTES_OUTGOING_ARGS,       \
1383 		STACK_BOUNDARY / BITS_PER_UNIT)		   \
1384     : (crtl->outgoing_args_size + STACK_POINTER_OFFSET))
1385 
1386 #endif /* GCC_AARCH64_H */
1387