1 /* Definitions of target machine for GNU compiler, for IBM RS/6000. 2 Copyright (C) 1992-2022 Free Software Foundation, Inc. 3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 Under Section 7 of GPL version 3, you are granted additional 18 permissions described in the GCC Runtime Library Exception, version 19 3.1, as published by the Free Software Foundation. 20 21 You should have received a copy of the GNU General Public License and 22 a copy of the GCC Runtime Library Exception along with this program; 23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 24 <http://www.gnu.org/licenses/>. */ 25 26 /* Note that some other tm.h files include this one and then override 27 many of the definitions. */ 28 29 #ifndef RS6000_OPTS_H 30 #include "config/rs6000/rs6000-opts.h" 31 #endif 32 33 /* 128-bit floating point precision values. */ 34 #ifndef RS6000_MODES_H 35 #include "config/rs6000/rs6000-modes.h" 36 #endif 37 38 /* Definitions for the object file format. These are set at 39 compile-time. */ 40 41 #define OBJECT_XCOFF 1 42 #define OBJECT_ELF 2 43 #define OBJECT_MACHO 4 44 45 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) 46 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) 47 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) 48 49 #ifndef TARGET_AIX 50 #define TARGET_AIX 0 51 #endif 52 53 #ifndef TARGET_AIX_OS 54 #define TARGET_AIX_OS 0 55 #endif 56 57 /* Turn off TOC support if pc-relative addressing is used. */ 58 #define TARGET_TOC (TARGET_HAS_TOC && !TARGET_PCREL) 59 60 /* On 32-bit systems without a TOC or pc-relative addressing, we need to use 61 ADDIS/ADDI to load up the address of a symbol. */ 62 #define TARGET_NO_TOC_OR_PCREL (!TARGET_HAS_TOC && !TARGET_PCREL) 63 64 /* Control whether function entry points use a "dot" symbol when 65 ABI_AIX. */ 66 #define DOT_SYMBOLS 1 67 68 /* Default string to use for cpu if not specified. */ 69 #ifndef TARGET_CPU_DEFAULT 70 #define TARGET_CPU_DEFAULT ((char *)0) 71 #endif 72 73 /* If configured for PPC405, support PPC405CR Erratum77. */ 74 #ifdef CONFIG_PPC405CR 75 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) 76 #else 77 #define PPC405_ERRATUM77 0 78 #endif 79 80 #ifndef SUBTARGET_DRIVER_SELF_SPECS 81 # define SUBTARGET_DRIVER_SELF_SPECS "" 82 #endif 83 84 /* Only for use in the testsuite: -mdejagnu-cpu=<value> filters out all 85 -mcpu= as well as -mtune= options then simply adds -mcpu=<value>, 86 while -mdejagnu-tune=<value> filters out all -mtune= options then 87 simply adds -mtune=<value>. 88 With older versions of Dejagnu the command line arguments you set in 89 RUNTESTFLAGS override those set in the testcases; with these options, 90 the testcase will always win. */ 91 #define DRIVER_SELF_SPECS \ 92 "%{mdejagnu-cpu=*: %<mcpu=* %<mtune=* -mcpu=%*}", \ 93 "%{mdejagnu-tune=*: %<mtune=* -mtune=%*}", \ 94 "%{mdejagnu-*: %<mdejagnu-*}", \ 95 SUBTARGET_DRIVER_SELF_SPECS 96 97 #if CHECKING_P 98 #define ASM_OPT_ANY "" 99 #else 100 #define ASM_OPT_ANY " -many" 101 #endif 102 103 /* Common ASM definitions used by ASM_SPEC among the various targets for 104 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.cc to 105 provide the default assembler options if the user uses -mcpu=native, so if 106 you make changes here, make them also there. PR63177: Do not pass -mpower8 107 to the assembler if -mpower9-vector was also used. */ 108 #define ASM_CPU_SPEC \ 109 "%{mcpu=native: %(asm_cpu_native); \ 110 mcpu=power10: -mpower10; \ 111 mcpu=power9: -mpower9; \ 112 mcpu=power8|mcpu=powerpc64le: %{mpower9-vector: -mpower9;: -mpower8}; \ 113 mcpu=power7: -mpower7; \ 114 mcpu=power6x: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \ 115 mcpu=power6: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \ 116 mcpu=power5+: -mpower5; \ 117 mcpu=power5: -mpower5; \ 118 mcpu=power4: -mpower4; \ 119 mcpu=power3: -mppc64; \ 120 mcpu=powerpc: -mppc; \ 121 mcpu=powerpc64: -mppc64; \ 122 mcpu=a2: -ma2; \ 123 mcpu=cell: -mcell; \ 124 mcpu=rs64: -mppc64; \ 125 mcpu=401: -mppc; \ 126 mcpu=403: -m403; \ 127 mcpu=405: -m405; \ 128 mcpu=405fp: -m405; \ 129 mcpu=440: -m440; \ 130 mcpu=440fp: -m440; \ 131 mcpu=464: -m440; \ 132 mcpu=464fp: -m440; \ 133 mcpu=476: -m476; \ 134 mcpu=476fp: -m476; \ 135 mcpu=505: -mppc; \ 136 mcpu=601: -m601; \ 137 mcpu=602: -mppc; \ 138 mcpu=603: -mppc; \ 139 mcpu=603e: -mppc; \ 140 mcpu=ec603e: -mppc; \ 141 mcpu=604: -mppc; \ 142 mcpu=604e: -mppc; \ 143 mcpu=620: -mppc64; \ 144 mcpu=630: -mppc64; \ 145 mcpu=740: -mppc; \ 146 mcpu=750: -mppc; \ 147 mcpu=G3: -mppc; \ 148 mcpu=7400: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ 149 mcpu=7450: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ 150 mcpu=G4: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \ 151 mcpu=801: -mppc; \ 152 mcpu=821: -mppc; \ 153 mcpu=823: -mppc; \ 154 mcpu=860: -mppc; \ 155 mcpu=970: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \ 156 mcpu=G5: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \ 157 mcpu=8540: -me500; \ 158 mcpu=8548: -me500; \ 159 mcpu=e300c2: -me300; \ 160 mcpu=e300c3: -me300; \ 161 mcpu=e500mc: -me500mc; \ 162 mcpu=e500mc64: -me500mc64; \ 163 mcpu=e5500: -me5500; \ 164 mcpu=e6500: -me6500; \ 165 mcpu=titan: -mtitan; \ 166 !mcpu*: %{mpower9-vector: -mpower9; \ 167 mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \ 168 mvsx: -mpower7; \ 169 mpowerpc64: -mppc64;: %(asm_default)}; \ 170 :%eMissing -mcpu option in ASM_CPU_SPEC?\n} \ 171 %{mvsx: -mvsx -maltivec; maltivec: -maltivec}" \ 172 ASM_OPT_ANY 173 174 #define CPP_DEFAULT_SPEC "" 175 176 #define ASM_DEFAULT_SPEC "" 177 #define ASM_DEFAULT_EXTRA "" 178 179 /* This macro defines names of additional specifications to put in the specs 180 that can be used in various specifications like CC1_SPEC. Its definition 181 is an initializer with a subgrouping for each command option. 182 183 Each subgrouping contains a string constant, that defines the 184 specification name, and a string constant that used by the GCC driver 185 program. 186 187 Do not define this macro if it does not need to do anything. */ 188 189 #define SUBTARGET_EXTRA_SPECS 190 191 #define EXTRA_SPECS \ 192 { "cpp_default", CPP_DEFAULT_SPEC }, \ 193 { "asm_cpu", ASM_CPU_SPEC }, \ 194 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ 195 { "asm_default", ASM_DEFAULT_SPEC ASM_DEFAULT_EXTRA }, \ 196 { "cc1_cpu", CC1_CPU_SPEC }, \ 197 SUBTARGET_EXTRA_SPECS 198 199 /* -mcpu=native handling only makes sense with compiler running on 200 an PowerPC chip. If changing this condition, also change 201 the condition in driver-rs6000.cc. */ 202 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) 203 /* In driver-rs6000.cc. */ 204 extern const char *host_detect_local_cpu (int argc, const char **argv); 205 #define EXTRA_SPEC_FUNCTIONS \ 206 { "local_cpu_detect", host_detect_local_cpu }, 207 #define HAVE_LOCAL_CPU_DETECT 208 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" 209 210 #else 211 #define ASM_CPU_NATIVE_SPEC "%(asm_default)" 212 #endif 213 214 #ifndef CC1_CPU_SPEC 215 #ifdef HAVE_LOCAL_CPU_DETECT 216 #define CC1_CPU_SPEC \ 217 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ 218 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 219 #else 220 #define CC1_CPU_SPEC "" 221 #endif 222 #endif 223 224 /* Architecture type. */ 225 226 /* Define TARGET_MFCRF if the target assembler does not support the 227 optional field operand for mfcr. */ 228 229 #ifndef HAVE_AS_MFCRF 230 #undef TARGET_MFCRF 231 #define TARGET_MFCRF 0 232 #endif 233 234 #ifndef TARGET_SECURE_PLT 235 #define TARGET_SECURE_PLT 0 236 #endif 237 238 #ifndef TARGET_CMODEL 239 #define TARGET_CMODEL CMODEL_SMALL 240 #endif 241 242 #define TARGET_32BIT (! TARGET_64BIT) 243 244 #ifndef HAVE_AS_TLS 245 #define HAVE_AS_TLS 0 246 #endif 247 248 #ifndef HAVE_AS_PLTSEQ 249 #define HAVE_AS_PLTSEQ 0 250 #endif 251 252 #ifndef TARGET_PLTSEQ 253 #define TARGET_PLTSEQ 0 254 #endif 255 256 #ifndef TARGET_LINK_STACK 257 #define TARGET_LINK_STACK 0 258 #endif 259 260 #ifndef SET_TARGET_LINK_STACK 261 #define SET_TARGET_LINK_STACK(X) do { } while (0) 262 #endif 263 264 #ifndef TARGET_FLOAT128_ENABLE_TYPE 265 #define TARGET_FLOAT128_ENABLE_TYPE 0 266 #endif 267 268 /* Return 1 for a symbol ref for a thread-local storage symbol. */ 269 #define RS6000_SYMBOL_REF_TLS_P(RTX) \ 270 (SYMBOL_REF_P (RTX) && SYMBOL_REF_TLS_MODEL (RTX) != 0) 271 272 #ifdef IN_LIBGCC2 273 /* For libgcc2 we make sure this is a compile time constant */ 274 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) 275 #undef TARGET_POWERPC64 276 #define TARGET_POWERPC64 1 277 #else 278 #undef TARGET_POWERPC64 279 #define TARGET_POWERPC64 0 280 #endif 281 #else 282 /* The option machinery will define this. */ 283 #endif 284 285 #define TARGET_DEFAULT (MASK_MULTIPLE) 286 287 /* Define generic processor types based upon current deployment. */ 288 #define PROCESSOR_COMMON PROCESSOR_PPC601 289 #define PROCESSOR_POWERPC PROCESSOR_PPC604 290 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A 291 292 /* Define the default processor. This is overridden by other tm.h files. */ 293 #define PROCESSOR_DEFAULT PROCESSOR_PPC603 294 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A 295 296 /* Specify the dialect of assembler to use. Only new mnemonics are supported 297 starting with GCC 4.8, i.e. just one dialect, but for backwards 298 compatibility with older inline asm ASSEMBLER_DIALECT needs to be 299 defined. */ 300 #define ASSEMBLER_DIALECT 1 301 302 /* Debug support */ 303 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */ 304 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */ 305 #define MASK_DEBUG_REG 0x04 /* debug register handling */ 306 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */ 307 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */ 308 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */ 309 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */ 310 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \ 311 | MASK_DEBUG_ARG \ 312 | MASK_DEBUG_REG \ 313 | MASK_DEBUG_ADDR \ 314 | MASK_DEBUG_COST \ 315 | MASK_DEBUG_TARGET \ 316 | MASK_DEBUG_BUILTIN) 317 318 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK) 319 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG) 320 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG) 321 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR) 322 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST) 323 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) 324 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) 325 326 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM 327 long double format that uses a pair of doubles, or IEEE 128-bit floating 328 point. KFmode was added as a way to represent IEEE 128-bit floating point, 329 even if the default for long double is the IBM long double format. 330 Similarly IFmode is the IBM long double format even if the default is IEEE 331 128-bit. Don't allow IFmode if -msoft-float. */ 332 #define FLOAT128_IEEE_P(MODE) \ 333 ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ 334 && ((MODE) == TFmode || (MODE) == TCmode)) \ 335 || ((MODE) == KFmode) || ((MODE) == KCmode)) 336 337 #define FLOAT128_IBM_P(MODE) \ 338 ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ 339 && ((MODE) == TFmode || (MODE) == TCmode)) \ 340 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode))) 341 342 /* Helper macros to say whether a 128-bit floating point type can go in a 343 single vector register, or whether it needs paired scalar values. */ 344 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)) 345 346 #define FLOAT128_2REG_P(MODE) \ 347 (FLOAT128_IBM_P (MODE) \ 348 || ((MODE) == TDmode) \ 349 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))) 350 351 /* Return true for floating point that does not use a vector register. */ 352 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \ 353 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE)) 354 355 /* Describe the vector unit used for arithmetic operations. */ 356 extern enum rs6000_vector rs6000_vector_unit[]; 357 358 #define VECTOR_UNIT_NONE_P(MODE) \ 359 (rs6000_vector_unit[(MODE)] == VECTOR_NONE) 360 361 #define VECTOR_UNIT_VSX_P(MODE) \ 362 (rs6000_vector_unit[(MODE)] == VECTOR_VSX) 363 364 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \ 365 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) 366 367 #define VECTOR_UNIT_ALTIVEC_P(MODE) \ 368 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) 369 370 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ 371 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ 372 (int)VECTOR_VSX, \ 373 (int)VECTOR_P8_VECTOR)) 374 375 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either 376 altivec (VMX) or VSX vector instructions. P8 vector support is upwards 377 compatible, so allow it as well, rather than changing all of the uses of the 378 macro. */ 379 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ 380 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ 381 (int)VECTOR_ALTIVEC, \ 382 (int)VECTOR_P8_VECTOR)) 383 384 /* Describe whether to use VSX loads or Altivec loads. For now, just use the 385 same unit as the vector unit we are using, but we may want to migrate to 386 using VSX style loads even for types handled by altivec. */ 387 extern enum rs6000_vector rs6000_vector_mem[]; 388 389 #define VECTOR_MEM_NONE_P(MODE) \ 390 (rs6000_vector_mem[(MODE)] == VECTOR_NONE) 391 392 #define VECTOR_MEM_VSX_P(MODE) \ 393 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) 394 395 #define VECTOR_MEM_P8_VECTOR_P(MODE) \ 396 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) 397 398 #define VECTOR_MEM_ALTIVEC_P(MODE) \ 399 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) 400 401 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ 402 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ 403 (int)VECTOR_VSX, \ 404 (int)VECTOR_P8_VECTOR)) 405 406 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ 407 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ 408 (int)VECTOR_ALTIVEC, \ 409 (int)VECTOR_P8_VECTOR)) 410 411 /* Return the alignment of a given vector type, which is set based on the 412 vector unit use. VSX for instance can load 32 or 64 bit aligned words 413 without problems, while Altivec requires 128-bit aligned vectors. */ 414 extern int rs6000_vector_align[]; 415 416 #define VECTOR_ALIGN(MODE) \ 417 ((rs6000_vector_align[(MODE)] != 0) \ 418 ? rs6000_vector_align[(MODE)] \ 419 : (int)GET_MODE_BITSIZE ((MODE))) 420 421 /* Element number of the 64-bit value in a 128-bit vector that can be accessed 422 with scalar instructions. */ 423 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1) 424 425 /* Element number of the 64-bit value in a 128-bit vector that can be accessed 426 with the ISA 3.0 MFVSRLD instructions. */ 427 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0) 428 429 /* Alignment options for fields in structures for sub-targets following 430 AIX-like ABI. 431 ALIGN_POWER word-aligns FP doubles (default AIX ABI). 432 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). 433 434 Override the macro definitions when compiling libobjc to avoid undefined 435 reference to rs6000_alignment_flags due to library's use of GCC alignment 436 macros which use the macros below. */ 437 438 #ifndef IN_TARGET_LIBS 439 #define MASK_ALIGN_POWER 0x00000000 440 #define MASK_ALIGN_NATURAL 0x00000001 441 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) 442 #else 443 #define TARGET_ALIGN_NATURAL 0 444 #endif 445 446 /* We use values 126..128 to pick the appropriate long double type (IFmode, 447 KFmode, TFmode). */ 448 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64) 449 #define TARGET_IEEEQUAD rs6000_ieeequad 450 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi 451 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) 452 453 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only. 454 Enable 32-bit fcfid's on any of the switches for newer ISA machines. */ 455 #define TARGET_FCFID (TARGET_POWERPC64 \ 456 || TARGET_PPC_GPOPT /* 970/power4 */ \ 457 || TARGET_POPCNTB /* ISA 2.02 */ \ 458 || TARGET_CMPB /* ISA 2.05 */ \ 459 || TARGET_POPCNTD) /* ISA 2.06 */ 460 461 #define TARGET_FCTIDZ TARGET_FCFID 462 #define TARGET_STFIWX TARGET_PPC_GFXOPT 463 #define TARGET_LFIWAX TARGET_CMPB 464 #define TARGET_LFIWZX TARGET_POPCNTD 465 #define TARGET_FCFIDS TARGET_POPCNTD 466 #define TARGET_FCFIDU TARGET_POPCNTD 467 #define TARGET_FCFIDUS TARGET_POPCNTD 468 #define TARGET_FCTIDUZ TARGET_POPCNTD 469 #define TARGET_FCTIWUZ TARGET_POPCNTD 470 #define TARGET_CTZ TARGET_MODULO 471 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) 472 #define TARGET_MADDLD TARGET_MODULO 473 474 /* TARGET_DIRECT_MOVE is redundant to TARGET_P8_VECTOR, so alias it to that. */ 475 #define TARGET_DIRECT_MOVE TARGET_P8_VECTOR 476 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) 477 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) 478 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64) 479 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ 480 && TARGET_POWERPC64) 481 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \ 482 && TARGET_POWERPC64) 483 484 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */ 485 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT 486 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT) 487 488 /* This wants to be set for p8 and newer. On p7, overlapping unaligned 489 loads are slow. */ 490 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX 491 492 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present 493 in power7, so conditionalize them on p8 features. TImode syncs need quad 494 memory support. */ 495 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ 496 || TARGET_QUAD_MEMORY_ATOMIC \ 497 || TARGET_POWER8) 498 499 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC 500 501 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need 502 to allocate the SDmode stack slot to get the value into the proper location 503 in the register. */ 504 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) 505 506 /* ISA 3.0 has new min/max functions that don't need fast math that are being 507 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct 508 answers if the arguments are not in the normal range. */ 509 #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ 510 && (TARGET_P9_MINMAX || !flag_trapping_math)) 511 512 /* In switching from using target_flags to using rs6000_isa_flags, the options 513 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map 514 OPTION_MASK_<xxx> back into MASK_<xxx>. */ 515 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC 516 #define MASK_CMPB OPTION_MASK_CMPB 517 #define MASK_CRYPTO OPTION_MASK_CRYPTO 518 #define MASK_DFP OPTION_MASK_DFP 519 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE 520 #define MASK_DLMZB OPTION_MASK_DLMZB 521 #define MASK_EABI OPTION_MASK_EABI 522 #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD 523 #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW 524 #define MASK_FPRND OPTION_MASK_FPRND 525 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION 526 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT 527 #define MASK_HTM OPTION_MASK_HTM 528 #define MASK_ISEL OPTION_MASK_ISEL 529 #define MASK_MFCRF OPTION_MASK_MFCRF 530 #define MASK_MMA OPTION_MASK_MMA 531 #define MASK_MULHW OPTION_MASK_MULHW 532 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE 533 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE 534 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR 535 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR 536 #define MASK_P9_MISC OPTION_MASK_P9_MISC 537 #define MASK_POPCNTB OPTION_MASK_POPCNTB 538 #define MASK_POPCNTD OPTION_MASK_POPCNTD 539 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT 540 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT 541 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION 542 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT 543 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN 544 #define MASK_UPDATE OPTION_MASK_UPDATE 545 #define MASK_VSX OPTION_MASK_VSX 546 #define MASK_POWER10 OPTION_MASK_POWER10 547 #define MASK_P10_FUSION OPTION_MASK_P10_FUSION 548 549 #ifndef IN_LIBGCC2 550 #define MASK_POWERPC64 OPTION_MASK_POWERPC64 551 #endif 552 553 #ifdef TARGET_64BIT 554 #define MASK_64BIT OPTION_MASK_64BIT 555 #endif 556 557 #ifdef TARGET_LITTLE_ENDIAN 558 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN 559 #endif 560 561 #ifdef TARGET_REGNAMES 562 #define MASK_REGNAMES OPTION_MASK_REGNAMES 563 #endif 564 565 #ifdef TARGET_PROTOTYPE 566 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE 567 #endif 568 569 #ifdef TARGET_MODULO 570 #define RS6000_BTM_MODULO OPTION_MASK_MODULO 571 #endif 572 573 574 /* For power systems, we want to enable Altivec and VSX builtins even if the 575 user did not use -maltivec or -mvsx to allow the builtins to be used inside 576 of #pragma GCC target or the target attribute to change the code level for a 577 given system. */ 578 579 #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \ 580 || TARGET_PPC_GPOPT /* 970/power4 */ \ 581 || TARGET_POPCNTB /* ISA 2.02 */ \ 582 || TARGET_CMPB /* ISA 2.05 */ \ 583 || TARGET_POPCNTD /* ISA 2.06 */ \ 584 || TARGET_ALTIVEC \ 585 || TARGET_VSX \ 586 || TARGET_HARD_FLOAT) 587 588 /* E500 cores only support plain "sync", not lwsync. */ 589 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ 590 || rs6000_cpu == PROCESSOR_PPC8548) 591 592 593 /* Which machine supports the various reciprocal estimate instructions. */ 594 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT) 595 596 #define TARGET_FRE (TARGET_HARD_FLOAT \ 597 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode))) 598 599 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \ 600 && TARGET_PPC_GFXOPT) 601 602 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \ 603 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode))) 604 605 /* Macro to say whether we can do optimizations where we need to do parts of 606 the calculation in 64-bit GPRs and then is transfered to the vector 607 registers. */ 608 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \ 609 && TARGET_P8_VECTOR \ 610 && TARGET_POWERPC64) 611 612 /* Inlining allows targets to define the meanings of bits in target_info 613 field of ipa_fn_summary by itself, the used bits for rs6000 are listed 614 below. */ 615 #define RS6000_FN_TARGET_INFO_HTM 1 616 617 /* Whether the various reciprocal divide/square root estimate instructions 618 exist, and whether we should automatically generate code for the instruction 619 by default. */ 620 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */ 621 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */ 622 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */ 623 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */ 624 625 extern unsigned char rs6000_recip_bits[]; 626 627 #define RS6000_RECIP_HAVE_RE_P(MODE) \ 628 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE) 629 630 #define RS6000_RECIP_AUTO_RE_P(MODE) \ 631 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE) 632 633 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \ 634 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE) 635 636 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ 637 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) 638 639 /* The default CPU for TARGET_OPTION_OVERRIDE. */ 640 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT 641 642 /* Target pragma. */ 643 #define REGISTER_TARGET_PRAGMAS() do { \ 644 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ 645 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \ 646 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ 647 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \ 648 } while (0) 649 650 /* Target #defines. */ 651 #define TARGET_CPU_CPP_BUILTINS() \ 652 rs6000_cpu_cpp_builtins (pfile) 653 654 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order 655 we're compiling for. Some configurations may need to override it. */ 656 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ 657 do \ 658 { \ 659 if (BYTES_BIG_ENDIAN) \ 660 { \ 661 builtin_define ("__BIG_ENDIAN__"); \ 662 builtin_define ("_BIG_ENDIAN"); \ 663 builtin_assert ("machine=bigendian"); \ 664 } \ 665 else \ 666 { \ 667 builtin_define ("__LITTLE_ENDIAN__"); \ 668 builtin_define ("_LITTLE_ENDIAN"); \ 669 builtin_assert ("machine=littleendian"); \ 670 } \ 671 } \ 672 while (0) 673 674 /* Target machine storage layout. */ 675 676 /* Define this if most significant bit is lowest numbered 677 in instructions that operate on numbered bit-fields. */ 678 /* That is true on RS/6000. */ 679 #define BITS_BIG_ENDIAN 1 680 681 /* Define this if most significant byte of a word is the lowest numbered. */ 682 /* That is true on RS/6000. */ 683 #define BYTES_BIG_ENDIAN 1 684 685 /* Define this if most significant word of a multiword number is lowest 686 numbered. 687 688 For RS/6000 we can decide arbitrarily since there are no machine 689 instructions for them. Might as well be consistent with bits and bytes. */ 690 #define WORDS_BIG_ENDIAN 1 691 692 /* This says that for the IBM long double the larger magnitude double 693 comes first. It's really a two element double array, and arrays 694 don't index differently between little- and big-endian. */ 695 #define LONG_DOUBLE_LARGE_FIRST 1 696 697 #define MAX_BITS_PER_WORD 64 698 699 /* Width of a word, in units (bytes). */ 700 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) 701 #ifdef IN_LIBGCC2 702 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 703 #else 704 #define MIN_UNITS_PER_WORD 4 705 #endif 706 #define UNITS_PER_FP_WORD 8 707 #define UNITS_PER_ALTIVEC_WORD 16 708 #define UNITS_PER_VSX_WORD 16 709 710 /* Type used for ptrdiff_t, as a string used in a declaration. */ 711 #define PTRDIFF_TYPE "int" 712 713 /* Type used for size_t, as a string used in a declaration. */ 714 #define SIZE_TYPE "long unsigned int" 715 716 /* Type used for wchar_t, as a string used in a declaration. */ 717 #define WCHAR_TYPE "short unsigned int" 718 719 /* Width of wchar_t in bits. */ 720 #define WCHAR_TYPE_SIZE 16 721 722 /* A C expression for the size in bits of the type `short' on the 723 target machine. If you don't define this, the default is half a 724 word. (If this would be less than one storage unit, it is 725 rounded up to one unit.) */ 726 #define SHORT_TYPE_SIZE 16 727 728 /* A C expression for the size in bits of the type `int' on the 729 target machine. If you don't define this, the default is one 730 word. */ 731 #define INT_TYPE_SIZE 32 732 733 /* A C expression for the size in bits of the type `long' on the 734 target machine. If you don't define this, the default is one 735 word. */ 736 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) 737 738 /* A C expression for the size in bits of the type `long long' on the 739 target machine. If you don't define this, the default is two 740 words. */ 741 #define LONG_LONG_TYPE_SIZE 64 742 743 /* A C expression for the size in bits of the type `float' on the 744 target machine. If you don't define this, the default is one 745 word. */ 746 #define FLOAT_TYPE_SIZE 32 747 748 /* A C expression for the size in bits of the type `double' on the 749 target machine. If you don't define this, the default is two 750 words. */ 751 #define DOUBLE_TYPE_SIZE 64 752 753 /* A C expression for the size in bits of the type `long double' on the target 754 machine. If you don't define this, the default is two words. */ 755 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size 756 757 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.cc. */ 758 #define WIDEST_HARDWARE_FP_SIZE 64 759 760 /* Width in bits of a pointer. 761 See also the macro `Pmode' defined below. */ 762 extern unsigned rs6000_pointer_size; 763 #define POINTER_SIZE rs6000_pointer_size 764 765 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 766 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) 767 768 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 769 #define STACK_BOUNDARY \ 770 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ 771 ? 64 : 128) 772 773 /* Allocation boundary (in *bits*) for the code of a function. */ 774 #define FUNCTION_BOUNDARY 32 775 776 /* No data type is required to be aligned rounder than this. Warning, if 777 BIGGEST_ALIGNMENT is changed, then this may be an ABI break. An example 778 of where this can break an ABI is in GLIBC's struct _Unwind_Exception. */ 779 #define BIGGEST_ALIGNMENT 128 780 781 /* Alignment of field after `int : 0' in a structure. */ 782 #define EMPTY_FIELD_BOUNDARY 32 783 784 /* Every structure's size must be a multiple of this. */ 785 #define STRUCTURE_SIZE_BOUNDARY 8 786 787 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 788 #define PCC_BITFIELD_TYPE_MATTERS 1 789 790 enum data_align { align_abi, align_opt, align_both }; 791 792 /* A C expression to compute the alignment for a variables in the 793 local store. TYPE is the data type, and ALIGN is the alignment 794 that the object would ordinarily have. */ 795 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 796 rs6000_data_alignment (TYPE, ALIGN, align_both) 797 798 /* Make arrays of chars word-aligned for the same reasons. */ 799 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 800 rs6000_data_alignment (TYPE, ALIGN, align_opt) 801 802 /* Align vectors to 128 bits. */ 803 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ 804 rs6000_data_alignment (TYPE, ALIGN, align_abi) 805 806 /* Nonzero if move instructions will actually fail to work 807 when given unaligned data. */ 808 #define STRICT_ALIGNMENT 0 809 810 /* Standard register usage. */ 811 812 /* Number of actual hardware registers. 813 The hardware registers are assigned numbers for the compiler 814 from 0 to just below FIRST_PSEUDO_REGISTER. 815 All registers that the compiler knows about must be given numbers, 816 even those that are not normally considered general registers. 817 818 RS/6000 has 32 fixed-point registers, 32 floating-point registers, 819 a count register, a link register, and 8 condition register fields, 820 which we view here as separate registers. AltiVec adds 32 vector 821 registers and a VRsave register. 822 823 In addition, the difference between the frame and argument pointers is 824 a function of the number of registers saved, so we need to have a 825 register for AP that will later be eliminated in favor of SP or FP. 826 This is a normal register, but it is fixed. 827 828 We also create a pseudo register for float/int conversions, that will 829 really represent the memory location used. It is represented here as 830 a register, in order to work around problems in allocating stack storage 831 in inline functions. 832 833 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame 834 pointer, which is eventually eliminated in favor of SP or FP. */ 835 836 #define FIRST_PSEUDO_REGISTER 111 837 838 /* Use standard DWARF numbering for DWARF debugging information. */ 839 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0) 840 841 /* Use gcc hard register numbering for eh_frame. */ 842 #define DWARF_FRAME_REGNUM(REGNO) (REGNO) 843 844 /* Map register numbers held in the call frame info that gcc has 845 collected using DWARF_FRAME_REGNUM to those that should be output in 846 .debug_frame and .eh_frame. */ 847 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ 848 rs6000_dbx_register_number ((REGNO), (FOR_EH) ? 2 : 1) 849 850 /* 1 for registers that have pervasive standard uses 851 and are not available for the register allocator. 852 853 On RS/6000, r1 is used for the stack. On Darwin, r2 is available 854 as a local register; for all other OS's r2 is the TOC pointer. 855 856 On System V implementations, r13 is fixed and not available for use. */ 857 858 #define FIXED_REGISTERS \ 859 {/* GPRs */ \ 860 0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ 861 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 862 /* FPRs */ \ 863 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 864 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 865 /* VRs */ \ 866 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 867 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 868 /* lr ctr ca ap */ \ 869 0, 0, 1, 1, \ 870 /* cr0..cr7 */ \ 871 0, 0, 0, 0, 0, 0, 0, 0, \ 872 /* vrsave vscr sfp */ \ 873 1, 1, 1 \ 874 } 875 876 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that 877 the entire set of `FIXED_REGISTERS' be included. 878 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). 879 This macro is optional. If not specified, it defaults to the value 880 of `CALL_USED_REGISTERS'. */ 881 882 #define CALL_REALLY_USED_REGISTERS \ 883 {/* GPRs */ \ 884 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 885 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 886 /* FPRs */ \ 887 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 888 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 889 /* VRs */ \ 890 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 891 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 892 /* lr ctr ca ap */ \ 893 1, 1, 1, 1, \ 894 /* cr0..cr7 */ \ 895 1, 1, 0, 0, 0, 1, 1, 1, \ 896 /* vrsave vscr sfp */ \ 897 0, 0, 0 \ 898 } 899 900 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) 901 902 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) 903 #define FIRST_SAVED_FP_REGNO (14+32) 904 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13) 905 906 /* List the order in which to allocate registers. Each register must be 907 listed once, even those in FIXED_REGISTERS. 908 909 We allocate in the following order: 910 fp0 (not saved or used for anything) 911 fp13 - fp2 (not saved; incoming fp arg registers) 912 fp1 (not saved; return value) 913 fp31 - fp14 (saved; order given to save least number) 914 cr7, cr5 (not saved or special) 915 cr6 (not saved, but used for vector operations) 916 cr1 (not saved, but used for FP operations) 917 cr0 (not saved, but used for arithmetic operations) 918 cr4, cr3, cr2 (saved) 919 r9 (not saved; best for TImode) 920 r10, r8-r4 (not saved; highest first for less conflict with params) 921 r3 (not saved; return value register) 922 r11 (not saved; later alloc to help shrink-wrap) 923 r0 (not saved; cannot be base reg) 924 r31 - r13 (saved; order given to save least number) 925 r12 (not saved; if used for DImode or DFmode would use r13) 926 ctr (not saved; when we have the choice ctr is better) 927 lr (saved) 928 r1, r2, ap, ca (fixed) 929 v0 - v1 (not saved or used for anything) 930 v13 - v3 (not saved; incoming vector arg registers) 931 v2 (not saved; incoming vector arg reg; return value) 932 v19 - v14 (not saved or used for anything) 933 v31 - v20 (saved; order given to save least number) 934 vrsave, vscr (fixed) 935 sfp (fixed) 936 */ 937 938 #if FIXED_R2 == 1 939 #define MAYBE_R2_AVAILABLE 940 #define MAYBE_R2_FIXED 2, 941 #else 942 #define MAYBE_R2_AVAILABLE 2, 943 #define MAYBE_R2_FIXED 944 #endif 945 946 #if FIXED_R13 == 1 947 #define EARLY_R12 12, 948 #define LATE_R12 949 #else 950 #define EARLY_R12 951 #define LATE_R12 12, 952 #endif 953 954 #define REG_ALLOC_ORDER \ 955 {32, \ 956 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ 957 /* not use fr14 which is a saved register. */ \ 958 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ 959 33, \ 960 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 961 50, 49, 48, 47, 46, \ 962 100, 107, 105, 106, 101, 104, 103, 102, \ 963 MAYBE_R2_AVAILABLE \ 964 9, 10, 8, 7, 6, 5, 4, \ 965 3, EARLY_R12 11, 0, \ 966 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 967 18, 17, 16, 15, 14, 13, LATE_R12 \ 968 97, 96, \ 969 1, MAYBE_R2_FIXED 99, 98, \ 970 /* AltiVec registers. */ \ 971 64, 65, \ 972 77, 76, 75, 74, 73, 72, 71, 70, 69, 68, 67, \ 973 66, \ 974 83, 82, 81, 80, 79, 78, \ 975 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, \ 976 108, 109, \ 977 110 \ 978 } 979 980 /* True if register is floating-point. */ 981 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) 982 983 /* True if register is a condition register. */ 984 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) 985 986 /* True if register is a condition register, but not cr0. */ 987 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) 988 989 /* True if register is an integer register. */ 990 #define INT_REGNO_P(N) \ 991 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) 992 993 /* True if register is the CA register. */ 994 #define CA_REGNO_P(N) ((N) == CA_REGNO) 995 996 /* True if register is an AltiVec register. */ 997 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) 998 999 /* True if register is a VSX register. */ 1000 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) 1001 1002 /* Alternate name for any vector register supporting floating point, no matter 1003 which instruction set(s) are available. */ 1004 #define VFLOAT_REGNO_P(N) \ 1005 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) 1006 1007 /* Alternate name for any vector register supporting integer, no matter which 1008 instruction set(s) are available. */ 1009 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) 1010 1011 /* Alternate name for any vector register supporting logical operations, no 1012 matter which instruction set(s) are available. Allow GPRs as well as the 1013 vector registers. */ 1014 #define VLOGICAL_REGNO_P(N) \ 1015 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ 1016 || (TARGET_VSX && FP_REGNO_P (N))) \ 1017 1018 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate 1019 enough space to account for vectors in FP regs. However, TFmode/TDmode 1020 should not use VSX instructions to do a caller save. */ 1021 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1022 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \ 1023 ? (MODE) \ 1024 : TARGET_VSX \ 1025 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ 1026 && FP_REGNO_P (REGNO) \ 1027 ? V2DFmode \ 1028 : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \ 1029 ? DFmode \ 1030 : (MODE) == TDmode && FP_REGNO_P (REGNO) \ 1031 ? DImode \ 1032 : choose_hard_reg_mode ((REGNO), (NREGS), NULL)) 1033 1034 #define VSX_VECTOR_MODE(MODE) \ 1035 ((MODE) == V4SFmode \ 1036 || (MODE) == V2DFmode) \ 1037 1038 /* Modes that are not vectors, but require vector alignment. Treat these like 1039 vectors in terms of loads and stores. */ 1040 #define VECTOR_ALIGNMENT_P(MODE) \ 1041 (FLOAT128_VECTOR_P (MODE) || (MODE) == OOmode || (MODE) == XOmode) 1042 1043 #define ALTIVEC_VECTOR_MODE(MODE) \ 1044 ((MODE) == V16QImode \ 1045 || (MODE) == V8HImode \ 1046 || (MODE) == V4SFmode \ 1047 || (MODE) == V4SImode \ 1048 || VECTOR_ALIGNMENT_P (MODE)) 1049 1050 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ 1051 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ 1052 || (MODE) == V2DImode || (MODE) == V1TImode) 1053 1054 /* Post-reload, we can't use any new AltiVec registers, as we already 1055 emitted the vrsave mask. */ 1056 1057 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1058 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) 1059 1060 /* Specify the cost of a branch insn; roughly the number of extra insns that 1061 should be added to avoid a branch. 1062 1063 Set this to 3 on the RS/6000 since that is roughly the average cost of an 1064 unscheduled conditional branch. */ 1065 1066 #define BRANCH_COST(speed_p, predictable_p) 3 1067 1068 /* Override BRANCH_COST heuristic which empirically produces worse 1069 performance for removing short circuiting from the logical ops. */ 1070 1071 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 1072 1073 /* Specify the registers used for certain standard purposes. 1074 The values of these macros are register numbers. */ 1075 1076 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ 1077 /* #define PC_REGNUM */ 1078 1079 /* Register to use for pushing function arguments. */ 1080 #define STACK_POINTER_REGNUM 1 1081 1082 /* Base register for access to local variables of the function. */ 1083 #define HARD_FRAME_POINTER_REGNUM 31 1084 1085 /* Base register for access to local variables of the function. */ 1086 #define FRAME_POINTER_REGNUM 110 1087 1088 /* Base register for access to arguments of the function. */ 1089 #define ARG_POINTER_REGNUM 99 1090 1091 /* Place to put static chain when calling a function that requires it. */ 1092 #define STATIC_CHAIN_REGNUM 11 1093 1094 /* Base register for access to thread local storage variables. */ 1095 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2) 1096 1097 1098 /* Define the classes of registers for register constraints in the 1099 machine description. Also define ranges of constants. 1100 1101 One of the classes must always be named ALL_REGS and include all hard regs. 1102 If there is more than one class, another class must be named NO_REGS 1103 and contain no registers. 1104 1105 The name GENERAL_REGS must be the name of a class (or an alias for 1106 another name such as ALL_REGS). This is the class of registers 1107 that is allowed by "g" or "r" in a register constraint. 1108 Also, registers outside this class are allocated only when 1109 instructions express preferences for them. 1110 1111 The classes must be numbered in nondecreasing order; that is, 1112 a larger-numbered class must never be contained completely 1113 in a smaller-numbered class. 1114 1115 For any two classes, it is very desirable that there be another 1116 class that represents their union. */ 1117 1118 /* The RS/6000 has three types of registers, fixed-point, floating-point, and 1119 condition registers, plus three special registers, CTR, and the link 1120 register. AltiVec adds a vector register class. VSX registers overlap the 1121 FPR registers and the Altivec registers. 1122 1123 However, r0 is special in that it cannot be used as a base register. 1124 So make a class for registers valid as base registers. 1125 1126 Also, cr0 is the only condition code register that can be used in 1127 arithmetic insns, so make a separate class for it. */ 1128 1129 enum reg_class 1130 { 1131 NO_REGS, 1132 BASE_REGS, 1133 GENERAL_REGS, 1134 FLOAT_REGS, 1135 ALTIVEC_REGS, 1136 VSX_REGS, 1137 VRSAVE_REGS, 1138 VSCR_REGS, 1139 GEN_OR_FLOAT_REGS, 1140 GEN_OR_VSX_REGS, 1141 LINK_REGS, 1142 CTR_REGS, 1143 LINK_OR_CTR_REGS, 1144 SPECIAL_REGS, 1145 SPEC_OR_GEN_REGS, 1146 CR0_REGS, 1147 CR_REGS, 1148 NON_FLOAT_REGS, 1149 CA_REGS, 1150 ALL_REGS, 1151 LIM_REG_CLASSES 1152 }; 1153 1154 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1155 1156 /* Give names of register classes as strings for dump file. */ 1157 1158 #define REG_CLASS_NAMES \ 1159 { \ 1160 "NO_REGS", \ 1161 "BASE_REGS", \ 1162 "GENERAL_REGS", \ 1163 "FLOAT_REGS", \ 1164 "ALTIVEC_REGS", \ 1165 "VSX_REGS", \ 1166 "VRSAVE_REGS", \ 1167 "VSCR_REGS", \ 1168 "GEN_OR_FLOAT_REGS", \ 1169 "GEN_OR_VSX_REGS", \ 1170 "LINK_REGS", \ 1171 "CTR_REGS", \ 1172 "LINK_OR_CTR_REGS", \ 1173 "SPECIAL_REGS", \ 1174 "SPEC_OR_GEN_REGS", \ 1175 "CR0_REGS", \ 1176 "CR_REGS", \ 1177 "NON_FLOAT_REGS", \ 1178 "CA_REGS", \ 1179 "ALL_REGS" \ 1180 } 1181 1182 /* Define which registers fit in which classes. 1183 This is an initializer for a vector of HARD_REG_SET 1184 of length N_REG_CLASSES. */ 1185 1186 #define REG_CLASS_CONTENTS \ 1187 { \ 1188 /* NO_REGS. */ \ 1189 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 1190 /* BASE_REGS. */ \ 1191 { 0xfffffffe, 0x00000000, 0x00000000, 0x00004008 }, \ 1192 /* GENERAL_REGS. */ \ 1193 { 0xffffffff, 0x00000000, 0x00000000, 0x00004008 }, \ 1194 /* FLOAT_REGS. */ \ 1195 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \ 1196 /* ALTIVEC_REGS. */ \ 1197 { 0x00000000, 0x00000000, 0xffffffff, 0x00000000 }, \ 1198 /* VSX_REGS. */ \ 1199 { 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ 1200 /* VRSAVE_REGS. */ \ 1201 { 0x00000000, 0x00000000, 0x00000000, 0x00001000 }, \ 1202 /* VSCR_REGS. */ \ 1203 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \ 1204 /* GEN_OR_FLOAT_REGS. */ \ 1205 { 0xffffffff, 0xffffffff, 0x00000000, 0x00004008 }, \ 1206 /* GEN_OR_VSX_REGS. */ \ 1207 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00004008 }, \ 1208 /* LINK_REGS. */ \ 1209 { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, \ 1210 /* CTR_REGS. */ \ 1211 { 0x00000000, 0x00000000, 0x00000000, 0x00000002 }, \ 1212 /* LINK_OR_CTR_REGS. */ \ 1213 { 0x00000000, 0x00000000, 0x00000000, 0x00000003 }, \ 1214 /* SPECIAL_REGS. */ \ 1215 { 0x00000000, 0x00000000, 0x00000000, 0x00001003 }, \ 1216 /* SPEC_OR_GEN_REGS. */ \ 1217 { 0xffffffff, 0x00000000, 0x00000000, 0x0000500b }, \ 1218 /* CR0_REGS. */ \ 1219 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, \ 1220 /* CR_REGS. */ \ 1221 { 0x00000000, 0x00000000, 0x00000000, 0x00000ff0 }, \ 1222 /* NON_FLOAT_REGS. */ \ 1223 { 0xffffffff, 0x00000000, 0x00000000, 0x00004ffb }, \ 1224 /* CA_REGS. */ \ 1225 { 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \ 1226 /* ALL_REGS. */ \ 1227 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \ 1228 } 1229 1230 /* The same information, inverted: 1231 Return the class number of the smallest class containing 1232 reg number REGNO. This could be a conditional expression 1233 or could index an array. */ 1234 1235 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; 1236 1237 #define REGNO_REG_CLASS(REGNO) \ 1238 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\ 1239 rs6000_regno_regclass[(REGNO)]) 1240 1241 /* Register classes for various constraints that are based on the target 1242 switches. */ 1243 enum r6000_reg_class_enum { 1244 RS6000_CONSTRAINT_d, /* fpr registers for double values */ 1245 RS6000_CONSTRAINT_f, /* fpr registers for single values */ 1246 RS6000_CONSTRAINT_v, /* Altivec registers */ 1247 RS6000_CONSTRAINT_wa, /* Any VSX register */ 1248 RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */ 1249 RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ 1250 RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ 1251 RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ 1252 RS6000_CONSTRAINT_MAX 1253 }; 1254 1255 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; 1256 1257 /* The class value for index registers, and the one for base regs. */ 1258 #define INDEX_REG_CLASS GENERAL_REGS 1259 #define BASE_REG_CLASS BASE_REGS 1260 1261 /* Return whether a given register class can hold VSX objects. */ 1262 #define VSX_REG_CLASS_P(CLASS) \ 1263 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) 1264 1265 /* Return whether a given register class targets general purpose registers. */ 1266 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) 1267 1268 /* Given an rtx X being reloaded into a reg required to be 1269 in class CLASS, return the class of reg to actually use. 1270 In general this is just CLASS; but on some machines 1271 in some cases it is preferable to use a more restrictive class. 1272 1273 On the RS/6000, we have to return NO_REGS when we want to reload a 1274 floating-point CONST_DOUBLE to force it to be copied to memory. 1275 1276 We also don't want to reload integer values into floating-point 1277 registers if we can at all help it. In fact, this can 1278 cause reload to die, if it tries to generate a reload of CTR 1279 into a FP register and discovers it doesn't have the memory location 1280 required. 1281 1282 ??? Would it be a good idea to have reload do the converse, that is 1283 try to reload floating modes into FP registers if possible? 1284 */ 1285 1286 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1287 rs6000_preferred_reload_class_ptr (X, CLASS) 1288 1289 /* Return the register class of a scratch register needed to copy IN into 1290 or out of a register in CLASS in MODE. If it can be done directly, 1291 NO_REGS is returned. */ 1292 1293 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ 1294 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) 1295 1296 /* Return the maximum number of consecutive registers 1297 needed to represent mode MODE in a register of class CLASS. 1298 1299 On RS/6000, this is the size of MODE in words, except in the FP regs, where 1300 a single reg is enough for two words, unless we have VSX, where the FP 1301 registers can hold 128 bits. */ 1302 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] 1303 1304 /* Stack layout; function entry, exit and calling. */ 1305 1306 /* Define this if pushing a word on the stack 1307 makes the stack pointer a smaller address. */ 1308 #define STACK_GROWS_DOWNWARD 1 1309 1310 /* Offsets recorded in opcodes are a multiple of this alignment factor. */ 1311 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) 1312 1313 /* Define this to nonzero if the nominal address of the stack frame 1314 is at the high-address end of the local variables; 1315 that is, each additional local variable allocated 1316 goes at a more negative offset in the frame. 1317 1318 On the RS/6000, we grow upwards, from the area after the outgoing 1319 arguments. */ 1320 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \ 1321 || (flag_sanitize & SANITIZE_ADDRESS) != 0) 1322 1323 /* Size of the fixed area on the stack */ 1324 #define RS6000_SAVE_AREA \ 1325 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \ 1326 << (TARGET_64BIT ? 1 : 0)) 1327 1328 /* Stack offset for toc save slot. */ 1329 #define RS6000_TOC_SAVE_SLOT \ 1330 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0)) 1331 1332 /* Align an address */ 1333 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a)) 1334 1335 /* Offset within stack frame to start allocating local variables at. 1336 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1337 first local allocated. Otherwise, it is the offset to the BEGINNING 1338 of the first local allocated. 1339 1340 On the RS/6000, the frame pointer is the same as the stack pointer, 1341 except for dynamic allocations. So we start after the fixed area and 1342 outgoing parameter area. 1343 1344 If the function uses dynamic stack space (CALLS_ALLOCA is set), that 1345 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the 1346 sizes of the fixed area and the parameter area must be a multiple of 1347 STACK_BOUNDARY. */ 1348 1349 #define RS6000_STARTING_FRAME_OFFSET \ 1350 (cfun->calls_alloca \ 1351 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \ 1352 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \ 1353 : (RS6000_ALIGN (crtl->outgoing_args_size, \ 1354 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ 1355 + RS6000_SAVE_AREA)) 1356 1357 /* Offset from the stack pointer register to an item dynamically 1358 allocated on the stack, e.g., by `alloca'. 1359 1360 The default value for this macro is `STACK_POINTER_OFFSET' plus the 1361 length of the outgoing arguments. The default is correct for most 1362 machines. See `function.cc' for details. 1363 1364 This value must be a multiple of STACK_BOUNDARY (hard coded in 1365 `emit-rtl.cc'). */ 1366 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1367 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \ 1368 + STACK_POINTER_OFFSET, \ 1369 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) 1370 1371 /* If we generate an insn to push BYTES bytes, 1372 this says how many the stack pointer really advances by. 1373 On RS/6000, don't define this because there are no push insns. */ 1374 /* #define PUSH_ROUNDING(BYTES) */ 1375 1376 /* Offset of first parameter from the argument pointer register value. 1377 On the RS/6000, we define the argument pointer to the start of the fixed 1378 area. */ 1379 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA 1380 1381 /* Offset from the argument pointer register value to the top of 1382 stack. This is different from FIRST_PARM_OFFSET because of the 1383 register save area. */ 1384 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1385 1386 /* Define this if stack space is still allocated for a parameter passed 1387 in a register. The value is the number of bytes allocated to this 1388 area. */ 1389 #define REG_PARM_STACK_SPACE(FNDECL) \ 1390 rs6000_reg_parm_stack_space ((FNDECL), false) 1391 1392 /* Define this macro if space guaranteed when compiling a function body 1393 is different to space required when making a call, a situation that 1394 can arise with K&R style function definitions. */ 1395 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \ 1396 rs6000_reg_parm_stack_space ((FNDECL), true) 1397 1398 /* Define this if the above stack space is to be considered part of the 1399 space allocated by the caller. */ 1400 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 1401 1402 /* This is the difference between the logical top of stack and the actual sp. 1403 1404 For the RS/6000, sp points past the fixed area. */ 1405 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA 1406 1407 /* Define this if the maximum size of all the outgoing args is to be 1408 accumulated and pushed during the prologue. The amount can be 1409 found in the variable crtl->outgoing_args_size. */ 1410 #define ACCUMULATE_OUTGOING_ARGS 1 1411 1412 /* Define how to find the value returned by a library function 1413 assuming the value has mode MODE. */ 1414 1415 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) 1416 1417 /* DRAFT_V4_STRUCT_RET defaults off. */ 1418 #define DRAFT_V4_STRUCT_RET 0 1419 1420 /* Let TARGET_RETURN_IN_MEMORY control what happens. */ 1421 #define DEFAULT_PCC_STRUCT_RETURN 0 1422 1423 /* Mode of stack savearea. 1424 FUNCTION is VOIDmode because calling convention maintains SP. 1425 BLOCK needs Pmode for SP. 1426 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 1427 #define STACK_SAVEAREA_MODE(LEVEL) \ 1428 (LEVEL == SAVE_FUNCTION ? VOIDmode \ 1429 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) 1430 1431 /* Minimum and maximum general purpose registers used to hold arguments. */ 1432 #define GP_ARG_MIN_REG 3 1433 #define GP_ARG_MAX_REG 10 1434 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) 1435 1436 /* Minimum and maximum floating point registers used to hold arguments. */ 1437 #define FP_ARG_MIN_REG 33 1438 #define FP_ARG_AIX_MAX_REG 45 1439 #define FP_ARG_V4_MAX_REG 40 1440 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \ 1441 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG) 1442 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) 1443 1444 /* Minimum and maximum AltiVec registers used to hold arguments. */ 1445 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) 1446 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) 1447 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) 1448 1449 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */ 1450 #define AGGR_ARG_NUM_REG 8 1451 1452 /* Return registers */ 1453 #define GP_ARG_RETURN GP_ARG_MIN_REG 1454 #define FP_ARG_RETURN FP_ARG_MIN_REG 1455 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) 1456 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ 1457 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) 1458 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \ 1459 ? (ALTIVEC_ARG_RETURN \ 1460 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \ 1461 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) 1462 1463 /* Flags for the call/call_value rtl operations set up by function_arg */ 1464 #define CALL_NORMAL 0x00000000 /* no special processing */ 1465 /* Bits in 0x00000001 are unused. */ 1466 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ 1467 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ 1468 #define CALL_LONG 0x00000008 /* always call indirect */ 1469 #define CALL_LIBCALL 0x00000010 /* libcall */ 1470 1471 /* Identify PLT sequence for rs6000_pltseq_template. */ 1472 enum rs6000_pltseq_enum { 1473 RS6000_PLTSEQ_TOCSAVE, 1474 RS6000_PLTSEQ_PLT16_HA, 1475 RS6000_PLTSEQ_PLT16_LO, 1476 RS6000_PLTSEQ_MTCTR, 1477 RS6000_PLTSEQ_PLT_PCREL34 1478 }; 1479 1480 #define IS_V4_FP_ARGS(OP) \ 1481 ((INTVAL (OP) & (CALL_V4_CLEAR_FP_ARGS | CALL_V4_SET_FP_ARGS)) != 0) 1482 1483 /* We don't have prologue and epilogue functions to save/restore 1484 everything for most ABIs. */ 1485 #define WORLD_SAVE_P(INFO) 0 1486 1487 /* 1 if N is a possible register number for a function value 1488 as seen by the caller. 1489 1490 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ 1491 #define FUNCTION_VALUE_REGNO_P(N) \ 1492 ((N) == GP_ARG_RETURN \ 1493 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \ 1494 && TARGET_HARD_FLOAT) \ 1495 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \ 1496 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) 1497 1498 /* 1 if N is a possible register number for function argument passing. 1499 On RS/6000, these are r3-r10 and fp1-fp13. 1500 On AltiVec, v2 - v13 are used for passing vectors. */ 1501 #define FUNCTION_ARG_REGNO_P(N) \ 1502 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \ 1503 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \ 1504 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ 1505 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \ 1506 && TARGET_HARD_FLOAT)) 1507 1508 /* Define a data type for recording info about an argument list 1509 during the scan of that argument list. This data type should 1510 hold all necessary information about the function itself 1511 and about the args processed so far, enough to enable macros 1512 such as FUNCTION_ARG to determine where the next arg should go. 1513 1514 On the RS/6000, this is a structure. The first element is the number of 1515 total argument words, the second is used to store the next 1516 floating-point register number, and the third says how many more args we 1517 have prototype types for. 1518 1519 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is 1520 the next available GP register, `fregno' is the next available FP 1521 register, and `words' is the number of words used on the stack. 1522 1523 The varargs/stdarg support requires that this structure's size 1524 be a multiple of sizeof(int). */ 1525 1526 typedef struct rs6000_args 1527 { 1528 int words; /* # words used for passing GP registers */ 1529 int fregno; /* next available FP register */ 1530 int vregno; /* next available AltiVec register */ 1531 int nargs_prototype; /* # args left in the current prototype */ 1532 int prototype; /* Whether a prototype was defined */ 1533 int stdarg; /* Whether function is a stdarg function. */ 1534 int call_cookie; /* Do special things for this call */ 1535 int sysv_gregno; /* next available GP register */ 1536 int intoffset; /* running offset in struct (darwin64) */ 1537 int use_stack; /* any part of struct on stack (darwin64) */ 1538 int floats_in_gpr; /* count of SFmode floats taking up 1539 GPR space (darwin64) */ 1540 int named; /* false for varargs params */ 1541 int escapes; /* if function visible outside tu */ 1542 int libcall; /* If this is a compiler generated call. */ 1543 } CUMULATIVE_ARGS; 1544 1545 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1546 for a call to a function whose data type is FNTYPE. 1547 For a library call, FNTYPE is 0. */ 1548 1549 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1550 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \ 1551 N_NAMED_ARGS, FNDECL, VOIDmode) 1552 1553 /* Similar, but when scanning the definition of a procedure. We always 1554 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ 1555 1556 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 1557 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \ 1558 1000, current_function_decl, VOIDmode) 1559 1560 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ 1561 1562 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1563 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \ 1564 0, NULL_TREE, MODE) 1565 1566 #define PAD_VARARGS_DOWN \ 1567 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD) 1568 1569 /* Output assembler code to FILE to increment profiler label # LABELNO 1570 for profiling a function entry. */ 1571 1572 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1573 output_function_profiler ((FILE), (LABELNO)); 1574 1575 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1576 the stack pointer does not matter. No definition is equivalent to 1577 always zero. 1578 1579 On the RS/6000, this is nonzero because we can restore the stack from 1580 its backpointer, which we maintain. */ 1581 #define EXIT_IGNORE_STACK 1 1582 1583 /* Define this macro as a C expression that is nonzero for registers 1584 that are used by the epilogue or the return' pattern. The stack 1585 and frame pointer registers are already be assumed to be used as 1586 needed. */ 1587 1588 #define EPILOGUE_USES(REGNO) \ 1589 ((reload_completed && (REGNO) == LR_REGNO) \ 1590 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ 1591 || (crtl->calls_eh_return \ 1592 && TARGET_AIX \ 1593 && (REGNO) == 2)) 1594 1595 1596 /* Length in units of the trampoline for entering a nested function. */ 1597 1598 #define TRAMPOLINE_SIZE rs6000_trampoline_size () 1599 1600 /* Definitions for __builtin_return_address and __builtin_frame_address. 1601 __builtin_return_address (0) should give link register (LR_REGNO), enable 1602 this. */ 1603 /* This should be uncommented, so that the link register is used, but 1604 currently this would result in unmatched insns and spilling fixed 1605 registers so we'll leave it for another day. When these problems are 1606 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. 1607 (mrs) */ 1608 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ 1609 1610 /* Number of bytes into the frame return addresses can be found. See 1611 rs6000_stack_info in rs6000.cc for more information on how the different 1612 abi's store the return address. */ 1613 #define RETURN_ADDRESS_OFFSET \ 1614 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0)) 1615 1616 /* The current return address is in the link register. The return address 1617 of anything farther back is accessed normally at an offset of 8 from the 1618 frame pointer. */ 1619 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 1620 (rs6000_return_addr (COUNT, FRAME)) 1621 1622 1623 /* Definitions for register eliminations. 1624 1625 We have two registers that can be eliminated on the RS/6000. First, the 1626 frame pointer register can often be eliminated in favor of the stack 1627 pointer register. Secondly, the argument pointer register can always be 1628 eliminated; it is replaced with either the stack or frame pointer. 1629 1630 In addition, we use the elimination mechanism to see if r30 is needed 1631 Initially we assume that it isn't. If it is, we spill it. This is done 1632 by making it an eliminable register. We replace it with itself so that 1633 if it isn't needed, then existing uses won't be modified. */ 1634 1635 /* This is an array of structures. Each structure initializes one pair 1636 of eliminable registers. The "from" register number is given first, 1637 followed by "to". Eliminations of the same "from" register are listed 1638 in order of preference. */ 1639 #define ELIMINABLE_REGS \ 1640 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1641 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1642 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1643 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1644 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1645 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } 1646 1647 /* Define the offset between two registers, one to be eliminated, and the other 1648 its replacement, at the start of a routine. */ 1649 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1650 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) 1651 1652 /* Addressing modes, and classification of registers for them. */ 1653 1654 #define HAVE_PRE_DECREMENT 1 1655 #define HAVE_PRE_INCREMENT 1 1656 #define HAVE_PRE_MODIFY_DISP 1 1657 #define HAVE_PRE_MODIFY_REG 1 1658 1659 /* Macros to check register numbers against specific register classes. */ 1660 1661 /* These assume that REGNO is a hard or pseudo reg number. 1662 They give nonzero only if REGNO is a hard reg of the suitable class 1663 or a pseudo reg currently allocated to a suitable hard reg. 1664 Since they use reg_renumber, they are safe only once reg_renumber 1665 has been allocated, which happens in reginfo.cc during register 1666 allocation. */ 1667 1668 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1669 (HARD_REGISTER_NUM_P (REGNO) \ 1670 ? (REGNO) <= 31 \ 1671 || (REGNO) == ARG_POINTER_REGNUM \ 1672 || (REGNO) == FRAME_POINTER_REGNUM \ 1673 : (reg_renumber[REGNO] >= 0 \ 1674 && (reg_renumber[REGNO] <= 31 \ 1675 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \ 1676 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1677 1678 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1679 (HARD_REGISTER_NUM_P (REGNO) \ 1680 ? ((REGNO) > 0 && (REGNO) <= 31) \ 1681 || (REGNO) == ARG_POINTER_REGNUM \ 1682 || (REGNO) == FRAME_POINTER_REGNUM \ 1683 : (reg_renumber[REGNO] > 0 \ 1684 && (reg_renumber[REGNO] <= 31 \ 1685 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \ 1686 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1687 1688 /* Nonzero if X is a hard reg that can be used as an index 1689 or if it is a pseudo reg in the non-strict case. */ 1690 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ 1691 ((!(STRICT) && !HARD_REGISTER_P (X)) \ 1692 || REGNO_OK_FOR_INDEX_P (REGNO (X))) 1693 1694 /* Nonzero if X is a hard reg that can be used as a base reg 1695 or if it is a pseudo reg in the non-strict case. */ 1696 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ 1697 ((!(STRICT) && !HARD_REGISTER_P (X)) \ 1698 || REGNO_OK_FOR_BASE_P (REGNO (X))) 1699 1700 1701 /* Maximum number of registers that can appear in a valid memory address. */ 1702 1703 #define MAX_REGS_PER_ADDRESS 2 1704 1705 /* Recognize any constant value that is a valid address. */ 1706 1707 #define CONSTANT_ADDRESS_P(X) \ 1708 (GET_CODE (X) == LABEL_REF || SYMBOL_REF_P (X) \ 1709 || CONST_INT_P (X) || GET_CODE (X) == CONST \ 1710 || GET_CODE (X) == HIGH) 1711 1712 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) 1713 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ 1714 && EASY_VECTOR_15((n) >> 1) \ 1715 && ((n) & 1) == 0) 1716 1717 #define EASY_VECTOR_MSB(n,mode) \ 1718 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \ 1719 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) 1720 1721 1722 #define FIND_BASE_TERM rs6000_find_base_term 1723 1724 /* The register number of the register used to address a table of 1725 static data addresses in memory. In some cases this register is 1726 defined by a processor's "application binary interface" (ABI). 1727 When this macro is defined, RTL is generated for this register 1728 once, as with the stack pointer and frame pointer registers. If 1729 this macro is not defined, it is up to the machine-dependent files 1730 to allocate such a register (if necessary). */ 1731 1732 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 1733 #define PIC_OFFSET_TABLE_REGNUM \ 1734 (TARGET_TOC ? TOC_REGISTER \ 1735 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \ 1736 : INVALID_REGNUM) 1737 1738 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) 1739 1740 /* Define this macro if the register defined by 1741 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define 1742 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ 1743 1744 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ 1745 1746 /* A C expression that is nonzero if X is a legitimate immediate 1747 operand on the target machine when generating position independent 1748 code. You can assume that X satisfies `CONSTANT_P', so you need 1749 not check this. You can also assume FLAG_PIC is true, so you need 1750 not check it either. You need not define this macro if all 1751 constants (including `SYMBOL_REF') can be immediate operands when 1752 generating position independent code. */ 1753 1754 /* #define LEGITIMATE_PIC_OPERAND_P (X) */ 1755 1756 /* Define as C expression which evaluates to nonzero if the tablejump 1757 instruction expects the table to contain offsets from the address of the 1758 table. 1759 Do not define this if the table should contain absolute addresses. */ 1760 #define CASE_VECTOR_PC_RELATIVE rs6000_relative_jumptables 1761 1762 /* Specify the machine mode that this machine uses 1763 for the index in the tablejump instruction. */ 1764 #define CASE_VECTOR_MODE (rs6000_relative_jumptables ? SImode : Pmode) 1765 1766 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1767 #define DEFAULT_SIGNED_CHAR 0 1768 1769 /* An integer expression for the size in bits of the largest integer machine 1770 mode that should actually be used. */ 1771 1772 /* Allow pairs of registers to be used, which is the intent of the default. */ 1773 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) 1774 1775 /* Max number of bytes we can move from memory to memory 1776 in one reasonably fast instruction. */ 1777 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) 1778 #define MAX_MOVE_MAX 8 1779 1780 /* Nonzero if access to memory by bytes is no faster than for words. 1781 Also nonzero if doing byte operations (specifically shifts) in registers 1782 is undesirable. */ 1783 #define SLOW_BYTE_ACCESS 1 1784 1785 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1786 will either zero-extend or sign-extend. The value of this macro should 1787 be the code that says which one of the two operations is implicitly 1788 done, UNKNOWN if none. */ 1789 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1790 1791 /* Define if loading short immediate values into registers sign extends. */ 1792 #define SHORT_IMMEDIATES_SIGN_EXTEND 1 1793 1794 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ 1795 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1796 ((VALUE) = GET_MODE_BITSIZE (MODE), 2) 1797 1798 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of 1799 zero. The hardware instructions added in Power9 and the sequences using 1800 popcount return 32 or 64. */ 1801 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1802 (TARGET_CTZ || TARGET_POPCNTD \ 1803 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \ 1804 : ((VALUE) = -1, 2)) 1805 1806 /* Specify the machine mode that pointers have. 1807 After generation of rtl, the compiler makes no further distinction 1808 between pointers and any other objects of this machine mode. */ 1809 extern scalar_int_mode rs6000_pmode; 1810 #define Pmode rs6000_pmode 1811 1812 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ 1813 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) 1814 1815 /* Mode of a function address in a call instruction (for indexing purposes). 1816 Doesn't matter on RS/6000. */ 1817 #define FUNCTION_MODE SImode 1818 1819 /* Define this if addresses of constant functions 1820 shouldn't be put through pseudo regs where they can be cse'd. 1821 Desirable on machines where ordinary constants are expensive 1822 but a CALL with constant address is cheap. */ 1823 #define NO_FUNCTION_CSE 1 1824 1825 /* Define this to be nonzero if shift instructions ignore all but the low-order 1826 few bits. 1827 1828 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED 1829 have been dropped from the PowerPC architecture. */ 1830 #define SHIFT_COUNT_TRUNCATED 0 1831 1832 /* Adjust the length of an INSN. LENGTH is the currently-computed length and 1833 should be adjusted to reflect any required changes. This macro is used when 1834 there is some systematic length adjustment required that would be difficult 1835 to express in the length attribute. 1836 1837 In the PowerPC, we use this to adjust the length of an instruction if one or 1838 more prefixed instructions are generated, using the attribute 1839 num_prefixed_insns. A prefixed instruction is 8 bytes instead of 4, but the 1840 hardware requires that a prefied instruciton does not cross a 64-byte 1841 boundary. This means the compiler has to assume the length of the first 1842 prefixed instruction is 12 bytes instead of 8 bytes. Since the length is 1843 already set for the non-prefixed instruction, we just need to udpate for the 1844 difference. */ 1845 1846 #define ADJUST_INSN_LENGTH(INSN,LENGTH) \ 1847 (LENGTH) = rs6000_adjust_insn_length ((INSN), (LENGTH)) 1848 1849 /* Given a comparison code (EQ, NE, etc.) and the first operand of a 1850 COMPARE, return the mode to be used for the comparison. For 1851 floating-point, CCFPmode should be used. CCUNSmode should be used 1852 for unsigned comparisons. CCEQmode should be used when we are 1853 doing an inequality comparison on the result of a 1854 comparison. CCmode should be used in all other cases. */ 1855 1856 #define SELECT_CC_MODE(OP,X,Y) \ 1857 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ 1858 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ 1859 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ 1860 ? CCEQmode : CCmode)) 1861 1862 /* Can the condition code MODE be safely reversed? This is safe in 1863 all cases on this port, because at present it doesn't use the 1864 trapping FP comparisons (fcmpo). */ 1865 #define REVERSIBLE_CC_MODE(MODE) 1 1866 1867 /* Given a condition code and a mode, return the inverse condition. */ 1868 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) 1869 1870 1871 /* Target cpu costs. */ 1872 1873 struct processor_costs { 1874 const int mulsi; /* cost of SImode multiplication. */ 1875 const int mulsi_const; /* cost of SImode multiplication by constant. */ 1876 const int mulsi_const9; /* cost of SImode mult by short constant. */ 1877 const int muldi; /* cost of DImode multiplication. */ 1878 const int divsi; /* cost of SImode division. */ 1879 const int divdi; /* cost of DImode division. */ 1880 const int fp; /* cost of simple SFmode and DFmode insns. */ 1881 const int dmul; /* cost of DFmode multiplication (and fmadd). */ 1882 const int sdiv; /* cost of SFmode division (fdivs). */ 1883 const int ddiv; /* cost of DFmode division (fdiv). */ 1884 const int cache_line_size; /* cache line size in bytes. */ 1885 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ 1886 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ 1887 const int simultaneous_prefetches; /* number of parallel prefetch 1888 operations. */ 1889 const int sfdf_convert; /* cost of SF->DF conversion. */ 1890 }; 1891 1892 extern const struct processor_costs *rs6000_cost; 1893 1894 /* Control the assembler format that we output. */ 1895 1896 /* A C string constant describing how to begin a comment in the target 1897 assembler language. The compiler assumes that the comment will end at 1898 the end of the line. */ 1899 #define ASM_COMMENT_START " #" 1900 1901 /* Flag to say the TOC is initialized */ 1902 extern int toc_initialized; 1903 1904 /* Macro to output a special constant pool entry. Go to WIN if we output 1905 it. Otherwise, it is written the usual way. 1906 1907 On the RS/6000, toc entries are handled this way. */ 1908 1909 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ 1910 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ 1911 { \ 1912 output_toc (FILE, X, LABELNO, MODE); \ 1913 goto WIN; \ 1914 } \ 1915 } 1916 1917 #ifdef HAVE_GAS_WEAK 1918 #define RS6000_WEAK 1 1919 #else 1920 #define RS6000_WEAK 0 1921 #endif 1922 1923 #if RS6000_WEAK 1924 /* Used in lieu of ASM_WEAKEN_LABEL. */ 1925 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ 1926 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL)) 1927 #endif 1928 1929 #if HAVE_GAS_WEAKREF 1930 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ 1931 do \ 1932 { \ 1933 fputs ("\t.weakref\t", (FILE)); \ 1934 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 1935 fputs (", ", (FILE)); \ 1936 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 1937 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 1938 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 1939 { \ 1940 fputs ("\n\t.weakref\t.", (FILE)); \ 1941 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 1942 fputs (", .", (FILE)); \ 1943 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 1944 } \ 1945 fputc ('\n', (FILE)); \ 1946 } while (0) 1947 #endif 1948 1949 /* This implements the `alias' attribute. */ 1950 #undef ASM_OUTPUT_DEF_FROM_DECLS 1951 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ 1952 do \ 1953 { \ 1954 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ 1955 const char *name = IDENTIFIER_POINTER (TARGET); \ 1956 if (TREE_CODE (DECL) == FUNCTION_DECL \ 1957 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 1958 { \ 1959 if (TREE_PUBLIC (DECL)) \ 1960 { \ 1961 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 1962 { \ 1963 fputs ("\t.globl\t.", FILE); \ 1964 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1965 putc ('\n', FILE); \ 1966 } \ 1967 } \ 1968 else if (TARGET_XCOFF) \ 1969 { \ 1970 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 1971 { \ 1972 fputs ("\t.lglobl\t.", FILE); \ 1973 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1974 putc ('\n', FILE); \ 1975 fputs ("\t.lglobl\t", FILE); \ 1976 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1977 putc ('\n', FILE); \ 1978 } \ 1979 } \ 1980 fputs ("\t.set\t.", FILE); \ 1981 RS6000_OUTPUT_BASENAME (FILE, alias); \ 1982 fputs (",.", FILE); \ 1983 RS6000_OUTPUT_BASENAME (FILE, name); \ 1984 fputc ('\n', FILE); \ 1985 } \ 1986 ASM_OUTPUT_DEF (FILE, alias, name); \ 1987 } \ 1988 while (0) 1989 1990 #define TARGET_ASM_FILE_START rs6000_file_start 1991 1992 /* Output to assembler file text saying following lines 1993 may contain character constants, extra white space, comments, etc. */ 1994 1995 #define ASM_APP_ON "" 1996 1997 /* Output to assembler file text saying following lines 1998 no longer contain unusual constructs. */ 1999 2000 #define ASM_APP_OFF "" 2001 2002 /* How to refer to registers in assembler output. 2003 This sequence is indexed by compiler's hard-register-number (see above). */ 2004 2005 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ 2006 2007 #define REGISTER_NAMES \ 2008 { \ 2009 &rs6000_reg_names[ 0][0], /* r0 */ \ 2010 &rs6000_reg_names[ 1][0], /* r1 */ \ 2011 &rs6000_reg_names[ 2][0], /* r2 */ \ 2012 &rs6000_reg_names[ 3][0], /* r3 */ \ 2013 &rs6000_reg_names[ 4][0], /* r4 */ \ 2014 &rs6000_reg_names[ 5][0], /* r5 */ \ 2015 &rs6000_reg_names[ 6][0], /* r6 */ \ 2016 &rs6000_reg_names[ 7][0], /* r7 */ \ 2017 &rs6000_reg_names[ 8][0], /* r8 */ \ 2018 &rs6000_reg_names[ 9][0], /* r9 */ \ 2019 &rs6000_reg_names[10][0], /* r10 */ \ 2020 &rs6000_reg_names[11][0], /* r11 */ \ 2021 &rs6000_reg_names[12][0], /* r12 */ \ 2022 &rs6000_reg_names[13][0], /* r13 */ \ 2023 &rs6000_reg_names[14][0], /* r14 */ \ 2024 &rs6000_reg_names[15][0], /* r15 */ \ 2025 &rs6000_reg_names[16][0], /* r16 */ \ 2026 &rs6000_reg_names[17][0], /* r17 */ \ 2027 &rs6000_reg_names[18][0], /* r18 */ \ 2028 &rs6000_reg_names[19][0], /* r19 */ \ 2029 &rs6000_reg_names[20][0], /* r20 */ \ 2030 &rs6000_reg_names[21][0], /* r21 */ \ 2031 &rs6000_reg_names[22][0], /* r22 */ \ 2032 &rs6000_reg_names[23][0], /* r23 */ \ 2033 &rs6000_reg_names[24][0], /* r24 */ \ 2034 &rs6000_reg_names[25][0], /* r25 */ \ 2035 &rs6000_reg_names[26][0], /* r26 */ \ 2036 &rs6000_reg_names[27][0], /* r27 */ \ 2037 &rs6000_reg_names[28][0], /* r28 */ \ 2038 &rs6000_reg_names[29][0], /* r29 */ \ 2039 &rs6000_reg_names[30][0], /* r30 */ \ 2040 &rs6000_reg_names[31][0], /* r31 */ \ 2041 \ 2042 &rs6000_reg_names[32][0], /* fr0 */ \ 2043 &rs6000_reg_names[33][0], /* fr1 */ \ 2044 &rs6000_reg_names[34][0], /* fr2 */ \ 2045 &rs6000_reg_names[35][0], /* fr3 */ \ 2046 &rs6000_reg_names[36][0], /* fr4 */ \ 2047 &rs6000_reg_names[37][0], /* fr5 */ \ 2048 &rs6000_reg_names[38][0], /* fr6 */ \ 2049 &rs6000_reg_names[39][0], /* fr7 */ \ 2050 &rs6000_reg_names[40][0], /* fr8 */ \ 2051 &rs6000_reg_names[41][0], /* fr9 */ \ 2052 &rs6000_reg_names[42][0], /* fr10 */ \ 2053 &rs6000_reg_names[43][0], /* fr11 */ \ 2054 &rs6000_reg_names[44][0], /* fr12 */ \ 2055 &rs6000_reg_names[45][0], /* fr13 */ \ 2056 &rs6000_reg_names[46][0], /* fr14 */ \ 2057 &rs6000_reg_names[47][0], /* fr15 */ \ 2058 &rs6000_reg_names[48][0], /* fr16 */ \ 2059 &rs6000_reg_names[49][0], /* fr17 */ \ 2060 &rs6000_reg_names[50][0], /* fr18 */ \ 2061 &rs6000_reg_names[51][0], /* fr19 */ \ 2062 &rs6000_reg_names[52][0], /* fr20 */ \ 2063 &rs6000_reg_names[53][0], /* fr21 */ \ 2064 &rs6000_reg_names[54][0], /* fr22 */ \ 2065 &rs6000_reg_names[55][0], /* fr23 */ \ 2066 &rs6000_reg_names[56][0], /* fr24 */ \ 2067 &rs6000_reg_names[57][0], /* fr25 */ \ 2068 &rs6000_reg_names[58][0], /* fr26 */ \ 2069 &rs6000_reg_names[59][0], /* fr27 */ \ 2070 &rs6000_reg_names[60][0], /* fr28 */ \ 2071 &rs6000_reg_names[61][0], /* fr29 */ \ 2072 &rs6000_reg_names[62][0], /* fr30 */ \ 2073 &rs6000_reg_names[63][0], /* fr31 */ \ 2074 \ 2075 &rs6000_reg_names[64][0], /* vr0 */ \ 2076 &rs6000_reg_names[65][0], /* vr1 */ \ 2077 &rs6000_reg_names[66][0], /* vr2 */ \ 2078 &rs6000_reg_names[67][0], /* vr3 */ \ 2079 &rs6000_reg_names[68][0], /* vr4 */ \ 2080 &rs6000_reg_names[69][0], /* vr5 */ \ 2081 &rs6000_reg_names[70][0], /* vr6 */ \ 2082 &rs6000_reg_names[71][0], /* vr7 */ \ 2083 &rs6000_reg_names[72][0], /* vr8 */ \ 2084 &rs6000_reg_names[73][0], /* vr9 */ \ 2085 &rs6000_reg_names[74][0], /* vr10 */ \ 2086 &rs6000_reg_names[75][0], /* vr11 */ \ 2087 &rs6000_reg_names[76][0], /* vr12 */ \ 2088 &rs6000_reg_names[77][0], /* vr13 */ \ 2089 &rs6000_reg_names[78][0], /* vr14 */ \ 2090 &rs6000_reg_names[79][0], /* vr15 */ \ 2091 &rs6000_reg_names[80][0], /* vr16 */ \ 2092 &rs6000_reg_names[81][0], /* vr17 */ \ 2093 &rs6000_reg_names[82][0], /* vr18 */ \ 2094 &rs6000_reg_names[83][0], /* vr19 */ \ 2095 &rs6000_reg_names[84][0], /* vr20 */ \ 2096 &rs6000_reg_names[85][0], /* vr21 */ \ 2097 &rs6000_reg_names[86][0], /* vr22 */ \ 2098 &rs6000_reg_names[87][0], /* vr23 */ \ 2099 &rs6000_reg_names[88][0], /* vr24 */ \ 2100 &rs6000_reg_names[89][0], /* vr25 */ \ 2101 &rs6000_reg_names[90][0], /* vr26 */ \ 2102 &rs6000_reg_names[91][0], /* vr27 */ \ 2103 &rs6000_reg_names[92][0], /* vr28 */ \ 2104 &rs6000_reg_names[93][0], /* vr29 */ \ 2105 &rs6000_reg_names[94][0], /* vr30 */ \ 2106 &rs6000_reg_names[95][0], /* vr31 */ \ 2107 \ 2108 &rs6000_reg_names[96][0], /* lr */ \ 2109 &rs6000_reg_names[97][0], /* ctr */ \ 2110 &rs6000_reg_names[98][0], /* ca */ \ 2111 &rs6000_reg_names[99][0], /* ap */ \ 2112 \ 2113 &rs6000_reg_names[100][0], /* cr0 */ \ 2114 &rs6000_reg_names[101][0], /* cr1 */ \ 2115 &rs6000_reg_names[102][0], /* cr2 */ \ 2116 &rs6000_reg_names[103][0], /* cr3 */ \ 2117 &rs6000_reg_names[104][0], /* cr4 */ \ 2118 &rs6000_reg_names[105][0], /* cr5 */ \ 2119 &rs6000_reg_names[106][0], /* cr6 */ \ 2120 &rs6000_reg_names[107][0], /* cr7 */ \ 2121 \ 2122 &rs6000_reg_names[108][0], /* vrsave */ \ 2123 &rs6000_reg_names[109][0], /* vscr */ \ 2124 \ 2125 &rs6000_reg_names[110][0] /* sfp */ \ 2126 } 2127 2128 /* Table of additional register names to use in user input. */ 2129 2130 #define ADDITIONAL_REGISTER_NAMES \ 2131 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ 2132 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ 2133 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ 2134 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ 2135 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ 2136 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ 2137 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ 2138 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ 2139 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ 2140 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ 2141 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ 2142 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ 2143 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ 2144 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ 2145 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ 2146 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ 2147 {"v0", 64}, {"v1", 65}, {"v2", 66}, {"v3", 67}, \ 2148 {"v4", 68}, {"v5", 69}, {"v6", 70}, {"v7", 71}, \ 2149 {"v8", 72}, {"v9", 73}, {"v10", 74}, {"v11", 75}, \ 2150 {"v12", 76}, {"v13", 77}, {"v14", 78}, {"v15", 79}, \ 2151 {"v16", 80}, {"v17", 81}, {"v18", 82}, {"v19", 83}, \ 2152 {"v20", 84}, {"v21", 85}, {"v22", 86}, {"v23", 87}, \ 2153 {"v24", 88}, {"v25", 89}, {"v26", 90}, {"v27", 91}, \ 2154 {"v28", 92}, {"v29", 93}, {"v30", 94}, {"v31", 95}, \ 2155 {"vrsave", 108}, {"vscr", 109}, \ 2156 /* no additional names for: lr, ctr, ap */ \ 2157 {"cr0", 100},{"cr1", 101},{"cr2", 102},{"cr3", 103}, \ 2158 {"cr4", 104},{"cr5", 105},{"cr6", 106},{"cr7", 107}, \ 2159 {"cc", 100},{"sp", 1}, {"toc", 2}, \ 2160 /* CA is only part of XER, but we do not model the other parts (yet). */ \ 2161 {"xer", 98}, \ 2162 /* VSX registers overlaid on top of FR, Altivec registers */ \ 2163 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ 2164 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ 2165 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ 2166 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ 2167 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ 2168 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ 2169 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ 2170 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ 2171 {"vs32", 64}, {"vs33", 65}, {"vs34", 66}, {"vs35", 67}, \ 2172 {"vs36", 68}, {"vs37", 69}, {"vs38", 70}, {"vs39", 71}, \ 2173 {"vs40", 72}, {"vs41", 73}, {"vs42", 74}, {"vs43", 75}, \ 2174 {"vs44", 76}, {"vs45", 77}, {"vs46", 78}, {"vs47", 79}, \ 2175 {"vs48", 80}, {"vs49", 81}, {"vs50", 82}, {"vs51", 83}, \ 2176 {"vs52", 84}, {"vs53", 85}, {"vs54", 86}, {"vs55", 87}, \ 2177 {"vs56", 88}, {"vs57", 89}, {"vs58", 90}, {"vs59", 91}, \ 2178 {"vs60", 92}, {"vs61", 93}, {"vs62", 94}, {"vs63", 95}, \ 2179 } 2180 2181 /* This is how to output an element of a case-vector that is relative. */ 2182 2183 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2184 do { char buf[100]; \ 2185 fputs ("\t.long ", FILE); \ 2186 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ 2187 assemble_name (FILE, buf); \ 2188 putc ('-', FILE); \ 2189 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ 2190 assemble_name (FILE, buf); \ 2191 putc ('\n', FILE); \ 2192 } while (0) 2193 2194 /* This is how to output an element of a case-vector 2195 that is non-relative. */ 2196 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2197 rs6000_output_addr_vec_elt ((FILE), (VALUE)) 2198 2199 /* This is how to output an assembler line 2200 that says to advance the location counter 2201 to a multiple of 2**LOG bytes. */ 2202 2203 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2204 if ((LOG) != 0) \ 2205 fprintf (FILE, "\t.align %d\n", (LOG)) 2206 2207 /* How to align the given loop. */ 2208 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL) 2209 2210 /* Alignment guaranteed by __builtin_malloc. */ 2211 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT. 2212 However, specifying the stronger guarantee currently leads to 2213 a regression in SPEC CPU2006 437.leslie3d. The stronger 2214 guarantee should be implemented here once that's fixed. */ 2215 #define MALLOC_ABI_ALIGNMENT (64) 2216 2217 /* Pick up the return address upon entry to a procedure. Used for 2218 dwarf2 unwind information. This also enables the table driven 2219 mechanism. */ 2220 2221 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) 2222 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) 2223 2224 /* Describe how we implement __builtin_eh_return. */ 2225 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) 2226 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) 2227 2228 /* Print operand X (an rtx) in assembler syntax to file FILE. 2229 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2230 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2231 2232 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2233 2234 /* Define which CODE values are valid. */ 2235 2236 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&') 2237 2238 /* Print a memory address as an operand to reference that memory location. */ 2239 2240 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2241 2242 /* For switching between functions with different target attributes. */ 2243 #define SWITCHABLE_TARGET 1 2244 2245 /* uncomment for disabling the corresponding default options */ 2246 /* #define MACHINE_no_sched_interblock */ 2247 /* #define MACHINE_no_sched_speculative */ 2248 /* #define MACHINE_no_sched_speculative_load */ 2249 2250 /* General flags. */ 2251 extern int frame_pointer_needed; 2252 2253 /* Classification of the builtin functions as to which switches enable the 2254 builtin, and what attributes it should have. We used to use the target 2255 flags macros, but we've run out of bits, so we now map the options into new 2256 settings used here. */ 2257 2258 /* Builtin operand count. */ 2259 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */ 2260 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */ 2261 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */ 2262 #define RS6000_BTC_QUATERNARY 0x00000004 /* normal quaternary 2263 function. */ 2264 #define RS6000_BTC_QUINARY 0x00000005 /* normal quinary function. */ 2265 #define RS6000_BTC_SENARY 0x00000006 /* normal senary function. */ 2266 #define RS6000_BTC_OPND_MASK 0x00000007 /* Mask to isolate operands. */ 2267 2268 /* Builtin attributes. */ 2269 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */ 2270 #define RS6000_BTC_PREDICATE 0x00000008 /* predicate function. */ 2271 #define RS6000_BTC_ABS 0x00000010 /* Altivec/VSX ABS 2272 function. */ 2273 #define RS6000_BTC_DST 0x00000020 /* Altivec DST function. */ 2274 2275 #define RS6000_BTC_TYPE_MASK 0x0000003f /* Mask to isolate types */ 2276 2277 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */ 2278 #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor 2279 modifies global state. */ 2280 #define RS6000_BTC_PURE 0x00000200 /* reads global 2281 state/mem and does 2282 not modify global state. */ 2283 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */ 2284 #define RS6000_BTC_QUAD 0x00000800 /* Uses a register quad. */ 2285 #define RS6000_BTC_PAIR 0x00001000 /* Uses a register pair. */ 2286 #define RS6000_BTC_QUADPAIR 0x00001800 /* Uses a quad and a pair. */ 2287 #define RS6000_BTC_ATTR_MASK 0x00001f00 /* Mask of the attributes. */ 2288 2289 /* Miscellaneous information. */ 2290 #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */ 2291 #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */ 2292 #define RS6000_BTC_CR 0x04000000 /* function references a CR. */ 2293 #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */ 2294 #define RS6000_BTC_GIMPLE 0x10000000 /* function should be expanded 2295 into gimple. */ 2296 #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */ 2297 2298 /* Convenience macros to document the instruction type. */ 2299 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ 2300 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */ 2301 2302 /* Builtin targets. For now, we reuse the masks for those options that are in 2303 target flags, and pick a random bit for ldbl128, which isn't in 2304 target_flags. */ 2305 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ 2306 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ 2307 #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ 2308 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ 2309 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ 2310 #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ 2311 #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ 2312 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ 2313 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ 2314 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ 2315 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ 2316 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ 2317 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ 2318 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ 2319 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ 2320 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ 2321 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ 2322 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ 2323 #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ 2324 #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */ 2325 #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */ 2326 #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */ 2327 #define RS6000_BTM_MMA MASK_MMA /* ISA 3.1 MMA. */ 2328 #define RS6000_BTM_P10 MASK_POWER10 2329 2330 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ 2331 | RS6000_BTM_VSX \ 2332 | RS6000_BTM_P8_VECTOR \ 2333 | RS6000_BTM_P9_VECTOR \ 2334 | RS6000_BTM_P9_MISC \ 2335 | RS6000_BTM_MODULO \ 2336 | RS6000_BTM_CRYPTO \ 2337 | RS6000_BTM_FRE \ 2338 | RS6000_BTM_FRES \ 2339 | RS6000_BTM_FRSQRTE \ 2340 | RS6000_BTM_FRSQRTES \ 2341 | RS6000_BTM_HTM \ 2342 | RS6000_BTM_POPCNTD \ 2343 | RS6000_BTM_CELL \ 2344 | RS6000_BTM_DFP \ 2345 | RS6000_BTM_HARD_FLOAT \ 2346 | RS6000_BTM_LDBL128 \ 2347 | RS6000_BTM_POWERPC64 \ 2348 | RS6000_BTM_FLOAT128 \ 2349 | RS6000_BTM_FLOAT128_HW \ 2350 | RS6000_BTM_MMA \ 2351 | RS6000_BTM_P10) 2352 2353 enum rs6000_builtin_type_index 2354 { 2355 RS6000_BTI_NOT_OPAQUE, 2356 RS6000_BTI_opaque_V4SI, 2357 RS6000_BTI_V16QI, /* __vector signed char */ 2358 RS6000_BTI_V1TI, 2359 RS6000_BTI_V2DI, 2360 RS6000_BTI_V2DF, 2361 RS6000_BTI_V4HI, 2362 RS6000_BTI_V4SI, 2363 RS6000_BTI_V4SF, 2364 RS6000_BTI_V8HI, 2365 RS6000_BTI_unsigned_V16QI, /* __vector unsigned char */ 2366 RS6000_BTI_unsigned_V1TI, 2367 RS6000_BTI_unsigned_V8HI, 2368 RS6000_BTI_unsigned_V4SI, 2369 RS6000_BTI_unsigned_V2DI, 2370 RS6000_BTI_bool_char, /* __bool char */ 2371 RS6000_BTI_bool_short, /* __bool short */ 2372 RS6000_BTI_bool_int, /* __bool int */ 2373 RS6000_BTI_bool_long_long, /* __bool long long */ 2374 RS6000_BTI_pixel, /* __pixel (16 bits arranged as 4 2375 channels of 1, 5, 5, and 5 bits 2376 respectively as packed with the 2377 vpkpx insn. __pixel is only 2378 meaningful as a vector type. 2379 There is no corresponding scalar 2380 __pixel data type.) */ 2381 RS6000_BTI_bool_V16QI, /* __vector __bool char */ 2382 RS6000_BTI_bool_V8HI, /* __vector __bool short */ 2383 RS6000_BTI_bool_V4SI, /* __vector __bool int */ 2384 RS6000_BTI_bool_V2DI, /* __vector __bool long */ 2385 RS6000_BTI_bool_V1TI, /* __vector __bool 128-bit */ 2386 RS6000_BTI_pixel_V8HI, /* __vector __pixel */ 2387 RS6000_BTI_long, /* long_integer_type_node */ 2388 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ 2389 RS6000_BTI_long_long, /* long_long_integer_type_node */ 2390 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ 2391 RS6000_BTI_INTQI, /* (signed) intQI_type_node */ 2392 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ 2393 RS6000_BTI_INTHI, /* intHI_type_node */ 2394 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ 2395 RS6000_BTI_INTSI, /* intSI_type_node (signed) */ 2396 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ 2397 RS6000_BTI_INTDI, /* intDI_type_node */ 2398 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ 2399 RS6000_BTI_INTTI, /* intTI_type_node */ 2400 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ 2401 RS6000_BTI_float, /* float_type_node */ 2402 RS6000_BTI_double, /* double_type_node */ 2403 RS6000_BTI_long_double, /* long_double_type_node */ 2404 RS6000_BTI_dfloat64, /* dfloat64_type_node */ 2405 RS6000_BTI_dfloat128, /* dfloat128_type_node */ 2406 RS6000_BTI_void, /* void_type_node */ 2407 RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */ 2408 RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */ 2409 RS6000_BTI_const_str, /* pointer to const char * */ 2410 RS6000_BTI_vector_pair, /* unsigned 256-bit types (vector pair). */ 2411 RS6000_BTI_vector_quad, /* unsigned 512-bit types (vector quad). */ 2412 RS6000_BTI_const_ptr_void, /* const pointer to void */ 2413 RS6000_BTI_ptr_V16QI, 2414 RS6000_BTI_ptr_V1TI, 2415 RS6000_BTI_ptr_V2DI, 2416 RS6000_BTI_ptr_V2DF, 2417 RS6000_BTI_ptr_V4SI, 2418 RS6000_BTI_ptr_V4SF, 2419 RS6000_BTI_ptr_V8HI, 2420 RS6000_BTI_ptr_unsigned_V16QI, 2421 RS6000_BTI_ptr_unsigned_V1TI, 2422 RS6000_BTI_ptr_unsigned_V8HI, 2423 RS6000_BTI_ptr_unsigned_V4SI, 2424 RS6000_BTI_ptr_unsigned_V2DI, 2425 RS6000_BTI_ptr_bool_V16QI, 2426 RS6000_BTI_ptr_bool_V8HI, 2427 RS6000_BTI_ptr_bool_V4SI, 2428 RS6000_BTI_ptr_bool_V2DI, 2429 RS6000_BTI_ptr_bool_V1TI, 2430 RS6000_BTI_ptr_pixel_V8HI, 2431 RS6000_BTI_ptr_INTQI, 2432 RS6000_BTI_ptr_UINTQI, 2433 RS6000_BTI_ptr_INTHI, 2434 RS6000_BTI_ptr_UINTHI, 2435 RS6000_BTI_ptr_INTSI, 2436 RS6000_BTI_ptr_UINTSI, 2437 RS6000_BTI_ptr_INTDI, 2438 RS6000_BTI_ptr_UINTDI, 2439 RS6000_BTI_ptr_INTTI, 2440 RS6000_BTI_ptr_UINTTI, 2441 RS6000_BTI_ptr_long_integer, 2442 RS6000_BTI_ptr_long_unsigned, 2443 RS6000_BTI_ptr_float, 2444 RS6000_BTI_ptr_double, 2445 RS6000_BTI_ptr_long_double, 2446 RS6000_BTI_ptr_dfloat64, 2447 RS6000_BTI_ptr_dfloat128, 2448 RS6000_BTI_ptr_vector_pair, 2449 RS6000_BTI_ptr_vector_quad, 2450 RS6000_BTI_ptr_long_long, 2451 RS6000_BTI_ptr_long_long_unsigned, 2452 RS6000_BTI_MAX 2453 }; 2454 2455 2456 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) 2457 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) 2458 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) 2459 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) 2460 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) 2461 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) 2462 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) 2463 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) 2464 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) 2465 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) 2466 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI]) 2467 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) 2468 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) 2469 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) 2470 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) 2471 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) 2472 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) 2473 #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long]) 2474 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) 2475 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) 2476 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) 2477 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) 2478 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) 2479 #define bool_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V1TI]) 2480 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) 2481 2482 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) 2483 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) 2484 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) 2485 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) 2486 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) 2487 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) 2488 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) 2489 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) 2490 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) 2491 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) 2492 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) 2493 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) 2494 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI]) 2495 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) 2496 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) 2497 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) 2498 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) 2499 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) 2500 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) 2501 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) 2502 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float]) 2503 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float]) 2504 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str]) 2505 #define vector_pair_type_node (rs6000_builtin_types[RS6000_BTI_vector_pair]) 2506 #define vector_quad_type_node (rs6000_builtin_types[RS6000_BTI_vector_quad]) 2507 #define pcvoid_type_node (rs6000_builtin_types[RS6000_BTI_const_ptr_void]) 2508 #define ptr_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V16QI]) 2509 #define ptr_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V1TI]) 2510 #define ptr_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V2DI]) 2511 #define ptr_V2DF_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V2DF]) 2512 #define ptr_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V4SI]) 2513 #define ptr_V4SF_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V4SF]) 2514 #define ptr_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_V8HI]) 2515 #define ptr_unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V16QI]) 2516 #define ptr_unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V1TI]) 2517 #define ptr_unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V8HI]) 2518 #define ptr_unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V4SI]) 2519 #define ptr_unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_unsigned_V2DI]) 2520 #define ptr_bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V16QI]) 2521 #define ptr_bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V8HI]) 2522 #define ptr_bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V4SI]) 2523 #define ptr_bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V2DI]) 2524 #define ptr_bool_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_bool_V1TI]) 2525 #define ptr_pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_pixel_V8HI]) 2526 #define ptr_intQI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTQI]) 2527 #define ptr_uintQI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTQI]) 2528 #define ptr_intHI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTHI]) 2529 #define ptr_uintHI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTHI]) 2530 #define ptr_intSI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTSI]) 2531 #define ptr_uintSI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTSI]) 2532 #define ptr_intDI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTDI]) 2533 #define ptr_uintDI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTDI]) 2534 #define ptr_intTI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_INTTI]) 2535 #define ptr_uintTI_type_node (rs6000_builtin_types[RS6000_BTI_ptr_UINTTI]) 2536 #define ptr_long_integer_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_integer]) 2537 #define ptr_long_unsigned_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_unsigned]) 2538 #define ptr_float_type_node (rs6000_builtin_types[RS6000_BTI_ptr_float]) 2539 #define ptr_double_type_node (rs6000_builtin_types[RS6000_BTI_ptr_double]) 2540 #define ptr_long_double_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_double]) 2541 #define ptr_dfloat64_type_node (rs6000_builtin_types[RS6000_BTI_ptr_dfloat64]) 2542 #define ptr_dfloat128_type_node (rs6000_builtin_types[RS6000_BTI_ptr_dfloat128]) 2543 #define ptr_vector_pair_type_node (rs6000_builtin_types[RS6000_BTI_ptr_vector_pair]) 2544 #define ptr_vector_quad_type_node (rs6000_builtin_types[RS6000_BTI_ptr_vector_quad]) 2545 #define ptr_long_long_integer_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_long]) 2546 #define ptr_long_long_unsigned_type_node (rs6000_builtin_types[RS6000_BTI_ptr_long_long_unsigned]) 2547 2548 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; 2549 2550 #ifndef USED_FOR_TARGET 2551 extern GTY(()) tree altivec_builtin_mask_for_load; 2552 extern GTY(()) section *toc_section; 2553 2554 /* A C structure for machine-specific, per-function data. 2555 This is added to the cfun structure. */ 2556 typedef struct GTY(()) machine_function 2557 { 2558 /* Flags if __builtin_return_address (n) with n >= 1 was used. */ 2559 int ra_needs_full_frame; 2560 /* Flags if __builtin_return_address (0) was used. */ 2561 int ra_need_lr; 2562 /* Cache lr_save_p after expansion of builtin_eh_return. */ 2563 int lr_save_state; 2564 /* Whether we need to save the TOC to the reserved stack location in the 2565 function prologue. */ 2566 bool save_toc_in_prologue; 2567 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4 2568 varargs save area. */ 2569 HOST_WIDE_INT varargs_save_offset; 2570 /* Alternative internal arg pointer for -fsplit-stack. */ 2571 rtx split_stack_arg_pointer; 2572 bool split_stack_argp_used; 2573 /* Flag if r2 setup is needed with ELFv2 ABI. */ 2574 bool r2_setup_needed; 2575 /* The number of components we use for separate shrink-wrapping. */ 2576 int n_components; 2577 /* The components already handled by separate shrink-wrapping, which should 2578 not be considered by the prologue and epilogue. */ 2579 bool gpr_is_wrapped_separately[32]; 2580 bool fpr_is_wrapped_separately[32]; 2581 bool lr_is_wrapped_separately; 2582 bool toc_is_wrapped_separately; 2583 bool mma_return_type_error; 2584 } machine_function; 2585 #endif 2586 2587 2588 #define TARGET_SUPPORTS_WIDE_INT 1 2589 2590 #if (GCC_VERSION >= 3000) 2591 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128 2592 #endif 2593 2594 /* Whether a given VALUE is a valid 16 or 34-bit signed integer. */ 2595 #define SIGNED_INTEGER_NBIT_P(VALUE, N) \ 2596 IN_RANGE ((VALUE), \ 2597 -(HOST_WIDE_INT_1 << ((N)-1)), \ 2598 (HOST_WIDE_INT_1 << ((N)-1)) - 1) 2599 2600 #define SIGNED_INTEGER_16BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 16) 2601 #define SIGNED_INTEGER_34BIT_P(VALUE) SIGNED_INTEGER_NBIT_P (VALUE, 34) 2602 2603 /* Like SIGNED_INTEGER_16BIT_P and SIGNED_INTEGER_34BIT_P, but with an extra 2604 argument that gives a length to validate a range of addresses, to allow for 2605 splitting insns into several insns, each of which has an offsettable 2606 address. */ 2607 #define SIGNED_16BIT_OFFSET_EXTRA_P(VALUE, EXTRA) \ 2608 IN_RANGE ((VALUE), \ 2609 -(HOST_WIDE_INT_1 << 15), \ 2610 (HOST_WIDE_INT_1 << 15) - 1 - (EXTRA)) 2611 2612 #define SIGNED_34BIT_OFFSET_EXTRA_P(VALUE, EXTRA) \ 2613 IN_RANGE ((VALUE), \ 2614 -(HOST_WIDE_INT_1 << 33), \ 2615 (HOST_WIDE_INT_1 << 33) - 1 - (EXTRA)) 2616 2617 /* Define this if some processing needs to be done before outputting the 2618 assembler code. On the PowerPC, we remember if the current insn is a normal 2619 prefixed insn where we need to emit a 'p' before the insn. */ 2620 #define FINAL_PRESCAN_INSN(INSN, OPERANDS, NOPERANDS) \ 2621 do \ 2622 { \ 2623 if (TARGET_PREFIXED) \ 2624 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS); \ 2625 } \ 2626 while (0) 2627 2628 /* Do anything special before emitting an opcode. We use it to emit a 'p' for 2629 prefixed insns that is set in FINAL_PRESCAN_INSN. */ 2630 #define ASM_OUTPUT_OPCODE(STREAM, OPCODE) \ 2631 do \ 2632 { \ 2633 if (TARGET_PREFIXED) \ 2634 rs6000_asm_output_opcode (STREAM); \ 2635 } \ 2636 while (0) 2637 2638 /* Disable generation of scalar modulo instructions due to performance issues 2639 with certain input values. This can be removed in the future when the 2640 issues have been resolved. */ 2641 #define RS6000_DISABLE_SCALAR_MODULO 1 2642 2643