1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991-2022 Free Software Foundation, Inc. 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 4 and Martin Simmons (@harleqn.co.uk). 5 More major hacks by Richard Earnshaw (rearnsha@arm.com) 6 Minor hacks by Nick Clifton (nickc@cygnus.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 Under Section 7 of GPL version 3, you are granted additional 21 permissions described in the GCC Runtime Library Exception, version 22 3.1, as published by the Free Software Foundation. 23 24 You should have received a copy of the GNU General Public License and 25 a copy of the GCC Runtime Library Exception along with this program; 26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 27 <http://www.gnu.org/licenses/>. */ 28 29 #ifndef GCC_ARM_H 30 #define GCC_ARM_H 31 32 /* We can't use machine_mode inside a generator file because it 33 hasn't been created yet; we shouldn't be using any code that 34 needs the real definition though, so this ought to be safe. */ 35 #ifdef GENERATOR_FILE 36 #define MACHMODE int 37 #else 38 #include "insn-modes.h" 39 #define MACHMODE machine_mode 40 #endif 41 42 #include "config/vxworks-dummy.h" 43 44 /* The architecture define. */ 45 extern char arm_arch_name[]; 46 47 /* Target CPU builtins. */ 48 #define TARGET_CPU_CPP_BUILTINS() arm_cpu_cpp_builtins (pfile) 49 50 #include "config/arm/arm-opts.h" 51 52 /* The processor for which instructions should be scheduled. */ 53 extern enum processor_type arm_tune; 54 55 typedef enum arm_cond_code 56 { 57 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 58 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 59 } 60 arm_cc; 61 62 extern arm_cc arm_current_cc; 63 64 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 65 66 /* The maximum number of instructions that is beneficial to 67 conditionally execute. */ 68 #undef MAX_CONDITIONAL_EXECUTE 69 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () 70 71 extern int arm_target_label; 72 extern int arm_ccfsm_state; 73 extern GTY(()) rtx arm_target_insn; 74 /* Callback to output language specific object attributes. */ 75 extern void (*arm_lang_output_object_attributes_hook)(void); 76 77 /* This type is the user-visible __fp16. We need it in a few places in 78 the backend. Defined in arm-builtins.cc. */ 79 extern tree arm_fp16_type_node; 80 81 /* This type is the user-visible __bf16. We need it in a few places in 82 the backend. Defined in arm-builtins.cc. */ 83 extern tree arm_bf16_type_node; 84 extern tree arm_bf16_ptr_type_node; 85 86 87 #undef CPP_SPEC 88 #define CPP_SPEC "%(subtarget_cpp_spec)" 89 90 #ifndef CC1_SPEC 91 #define CC1_SPEC "" 92 #endif 93 94 /* This macro defines names of additional specifications to put in the specs 95 that can be used in various specifications like CC1_SPEC. Its definition 96 is an initializer with a subgrouping for each command option. 97 98 Each subgrouping contains a string constant, that defines the 99 specification name, and a string constant that used by the GCC driver 100 program. 101 102 Do not define this macro if it does not need to do anything. */ 103 #define EXTRA_SPECS \ 104 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 105 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 106 SUBTARGET_EXTRA_SPECS 107 108 #ifndef SUBTARGET_EXTRA_SPECS 109 #define SUBTARGET_EXTRA_SPECS 110 #endif 111 112 #ifndef SUBTARGET_CPP_SPEC 113 #define SUBTARGET_CPP_SPEC "" 114 #endif 115 116 /* Tree Target Specification. */ 117 #define TARGET_ARM_P(flags) (!TARGET_THUMB_P (flags)) 118 #define TARGET_THUMB1_P(flags) (TARGET_THUMB_P (flags) && !arm_arch_thumb2) 119 #define TARGET_THUMB2_P(flags) (TARGET_THUMB_P (flags) && arm_arch_thumb2) 120 #define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags)) 121 122 /* Run-time Target Specification. */ 123 /* Use hardware floating point instructions. -mgeneral-regs-only prevents 124 the use of floating point instructions and registers but does not prevent 125 emission of floating point pcs attributes. */ 126 #define TARGET_HARD_FLOAT_SUB (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 127 && bitmap_bit_p (arm_active_target.isa, \ 128 isa_bit_vfpv2) \ 129 && TARGET_32BIT) 130 131 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_SUB \ 132 && !TARGET_GENERAL_REGS_ONLY) 133 134 #define TARGET_SOFT_FLOAT (!TARGET_HARD_FLOAT_SUB) 135 /* User has permitted use of FP instructions, if they exist for this 136 target. */ 137 #define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 138 /* Use hardware floating point calling convention. */ 139 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 140 #define TARGET_IWMMXT (arm_arch_iwmmxt) 141 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) 142 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT \ 143 && !TARGET_GENERAL_REGS_ONLY) 144 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT \ 145 && !TARGET_GENERAL_REGS_ONLY) 146 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 147 #define TARGET_ARM (! TARGET_THUMB) 148 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 149 #define TARGET_BACKTRACE (crtl->is_leaf \ 150 ? TARGET_TPCS_LEAF_FRAME \ 151 : TARGET_TPCS_FRAME) 152 #define TARGET_AAPCS_BASED \ 153 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 154 155 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 156 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 157 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 158 159 /* Only 16-bit thumb code. */ 160 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 161 /* Arm or Thumb-2 32-bit code. */ 162 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 163 /* 32-bit Thumb-2 code. */ 164 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 165 /* Thumb-1 only. */ 166 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 167 168 #define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \ 169 && !TARGET_THUMB1) 170 171 #define TARGET_CRC32 (arm_arch_crc) 172 173 /* Thumb-2 but also has some conditional arithmetic instructions like csinc, 174 csinv, etc. */ 175 #define TARGET_COND_ARITH (arm_arch8_1m_main) 176 177 /* The following two macros concern the ability to execute coprocessor 178 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 179 only ever tested when we know we are generating for VFP hardware; we need 180 to be more careful with TARGET_NEON as noted below. */ 181 182 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 183 #define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32)) 184 185 /* FPU supports VFPv3 instructions. */ 186 #define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv3)) 187 188 /* FPU supports FPv5 instructions. */ 189 #define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_fpv5)) 190 191 /* FPU only supports VFP single-precision instructions. */ 192 #define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE) 193 194 /* FPU supports VFP double-precision instructions. */ 195 #define TARGET_VFP_DOUBLE (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_dbl)) 196 197 /* FPU supports half-precision floating-point with NEON element load/store. */ 198 #define TARGET_NEON_FP16 \ 199 (bitmap_bit_p (arm_active_target.isa, isa_bit_neon) \ 200 && bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 201 202 /* FPU supports VFP half-precision floating-point conversions. */ 203 #define TARGET_FP16 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 204 205 /* FPU supports converting between HFmode and DFmode in a single hardware 206 step. */ 207 #define TARGET_FP16_TO_DOUBLE \ 208 (TARGET_HARD_FLOAT && TARGET_FP16 && TARGET_VFP5 && TARGET_VFP_DOUBLE) 209 210 /* FPU supports fused-multiply-add operations. */ 211 #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv4)) 212 213 /* FPU supports Crypto extensions. */ 214 #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto)) 215 216 /* FPU supports Neon instructions. The setting of this macro gets 217 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 218 and TARGET_HARD_FLOAT to ensure that NEON instructions are 219 available. */ 220 #define TARGET_NEON \ 221 (TARGET_32BIT && TARGET_HARD_FLOAT \ 222 && bitmap_bit_p (arm_active_target.isa, isa_bit_neon)) 223 224 /* FPU supports ARMv8.1 Adv.SIMD extensions. */ 225 #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1) 226 227 /* Supports the Dot Product AdvSIMD extensions. */ 228 #define TARGET_DOTPROD (TARGET_NEON && TARGET_VFP5 \ 229 && bitmap_bit_p (arm_active_target.isa, \ 230 isa_bit_dotprod) \ 231 && arm_arch8_2) 232 233 /* Supports the Armv8.3-a Complex number AdvSIMD extensions. */ 234 #define TARGET_COMPLEX (TARGET_NEON && arm_arch8_3) 235 236 /* FPU supports the floating point FP16 instructions for ARMv8.2-A 237 and later. */ 238 #define TARGET_VFP_FP16INST \ 239 (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst) 240 241 /* Target supports the floating point FP16 instructions from ARMv8.2-A 242 and later. */ 243 #define TARGET_FP16FML (TARGET_NEON \ 244 && bitmap_bit_p (arm_active_target.isa, \ 245 isa_bit_fp16fml) \ 246 && arm_arch8_2) 247 248 /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later. */ 249 #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA) 250 251 /* FPU supports 8-bit Integer Matrix Multiply (I8MM) AdvSIMD extensions. */ 252 #define TARGET_I8MM (TARGET_NEON && arm_arch8_2 && arm_arch_i8mm) 253 254 /* FPU supports Brain half-precision floating-point (BFloat16) extension. */ 255 #define TARGET_BF16_FP (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 \ 256 && arm_arch8_2 && arm_arch_bf16) 257 #define TARGET_BF16_SIMD (TARGET_NEON && TARGET_VFP5 \ 258 && arm_arch8_2 && arm_arch_bf16) 259 260 /* Q-bit is present. */ 261 #define TARGET_ARM_QBIT \ 262 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7)) 263 /* Saturation operation, e.g. SSAT. */ 264 #define TARGET_ARM_SAT \ 265 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) 266 /* "DSP" multiply instructions, eg. SMULxy. */ 267 #define TARGET_DSP_MULTIPLY \ 268 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7em)) 269 /* Integer SIMD instructions, and extend-accumulate instructions. */ 270 #define TARGET_INT_SIMD \ 271 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 272 273 /* Should MOVW/MOVT be used in preference to a constant pool. */ 274 #define TARGET_USE_MOVT \ 275 (TARGET_HAVE_MOVT \ 276 && (arm_disable_literal_pool \ 277 || (!optimize_size && !current_tune->prefer_constant_pool))) 278 279 /* Nonzero if this chip provides the DMB instruction. */ 280 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) 281 282 /* Nonzero if this chip implements a memory barrier via CP15. */ 283 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ 284 && ! TARGET_THUMB1) 285 286 /* Nonzero if this chip implements a memory barrier instruction. */ 287 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 288 289 /* Nonzero if this chip supports ldrex and strex */ 290 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) \ 291 || arm_arch7 \ 292 || (arm_arch8 && !arm_arch_notm)) 293 294 /* Nonzero if this chip supports LPAE. */ 295 #define TARGET_HAVE_LPAE (arm_arch_lpae) 296 297 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ 298 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \ 299 || arm_arch7 \ 300 || (arm_arch8 && !arm_arch_notm)) 301 302 /* Nonzero if this chip supports ldrexd and strexd. */ 303 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \ 304 || arm_arch7) && arm_arch_notm) 305 306 /* Nonzero if this chip supports load-acquire and store-release. */ 307 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) 308 309 /* Nonzero if this chip supports LDAEXD and STLEXD. */ 310 #define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \ 311 && TARGET_32BIT \ 312 && arm_arch_notm) 313 314 /* Nonzero if this chip provides the MOVW and MOVT instructions. */ 315 #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) 316 317 /* Nonzero if this chip provides the CBZ and CBNZ instructions. */ 318 #define TARGET_HAVE_CBZ (arm_arch_thumb2 || arm_arch8) 319 320 /* Nonzero if this chip provides Armv8.1-M Mainline Security extensions 321 instructions (most are floating-point related). */ 322 #define TARGET_HAVE_FPCXT_CMSE (arm_arch8_1m_main) 323 324 #define TARGET_HAVE_MVE (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 325 && bitmap_bit_p (arm_active_target.isa, \ 326 isa_bit_mve) \ 327 && !TARGET_GENERAL_REGS_ONLY) 328 329 #define TARGET_HAVE_MVE_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 330 && bitmap_bit_p (arm_active_target.isa, \ 331 isa_bit_mve_float) \ 332 && !TARGET_GENERAL_REGS_ONLY) 333 334 /* MVE have few common instructions as VFP, like VLDM alias VPOP, VLDR, VSTM 335 alia VPUSH, VSTR and VMOV, VMSR and VMRS. In the same manner it updates few 336 registers such as FPCAR, FPCCR, FPDSCR, FPSCR, MVFR0, MVFR1 and MVFR2. All 337 the VFP instructions, RTL patterns and register are guarded by 338 TARGET_HARD_FLOAT. But the common instructions, RTL pattern and registers 339 between MVE and VFP will be guarded by the following macro TARGET_VFP_BASE 340 hereafter. */ 341 342 #define TARGET_VFP_BASE (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 343 && bitmap_bit_p (arm_active_target.isa, \ 344 isa_bit_vfp_base) \ 345 && !TARGET_GENERAL_REGS_ONLY) 346 347 /* Nonzero if integer division instructions supported. */ 348 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 349 || (TARGET_THUMB && arm_arch_thumb_hwdiv)) 350 351 /* Nonzero if disallow volatile memory access in IT block. */ 352 #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) 353 354 /* Nonzero if chip supports the Custom Datapath Extension. */ 355 #define TARGET_CDE (arm_arch_cde && arm_arch8 && !arm_arch_notm) 356 357 /* Should constant I be slplit for OP. */ 358 #define DONT_EARLY_SPLIT_CONSTANT(i, op) \ 359 ((optimize >= 2) \ 360 && can_create_pseudo_p () \ 361 && !const_ok_for_op (i, op)) 362 363 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 364 then TARGET_AAPCS_BASED must be true -- but the converse does not 365 hold. TARGET_BPABI implies the use of the BPABI runtime library, 366 etc., in addition to just the AAPCS calling conventions. */ 367 #ifndef TARGET_BPABI 368 #define TARGET_BPABI false 369 #endif 370 371 /* Transform lane numbers on big endian targets. This is used to allow for the 372 endianness difference between NEON architectural lane numbers and those 373 used in RTL */ 374 #define NEON_ENDIAN_LANE_N(mode, n) \ 375 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) 376 377 /* Support for a compile-time default CPU, et cetera. The rules are: 378 --with-arch is ignored if -march or -mcpu are specified. 379 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 380 by --with-arch. 381 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 382 by -march). 383 --with-float is ignored if -mfloat-abi is specified. 384 --with-fpu is ignored if -mfpu is specified. 385 --with-abi is ignored if -mabi is specified. 386 --with-tls is ignored if -mtls-dialect is specified. 387 Note: --with-mode is not handled here, that has a special rule 388 TARGET_MODE_CHECK that also takes into account the selected CPU and 389 architecture. */ 390 #define OPTION_DEFAULT_SPECS \ 391 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 392 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 393 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 394 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ 395 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 396 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 397 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 398 399 extern const struct arm_fpu_desc 400 { 401 const char *name; 402 enum isa_feature isa_bits[isa_num_bits]; 403 } all_fpus[]; 404 405 /* Which floating point hardware to schedule for. */ 406 extern int arm_fpu_attr; 407 408 #ifndef TARGET_DEFAULT_FLOAT_ABI 409 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 410 #endif 411 412 #ifndef ARM_DEFAULT_ABI 413 #define ARM_DEFAULT_ABI ARM_ABI_APCS 414 #endif 415 416 /* AAPCS based ABIs use short enums by default. */ 417 #ifndef ARM_DEFAULT_SHORT_ENUMS 418 #define ARM_DEFAULT_SHORT_ENUMS \ 419 (TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX) 420 #endif 421 422 /* Map each of the micro-architecture variants to their corresponding 423 major architecture revision. */ 424 425 enum base_architecture 426 { 427 BASE_ARCH_0 = 0, 428 BASE_ARCH_2 = 2, 429 BASE_ARCH_3 = 3, 430 BASE_ARCH_3M = 3, 431 BASE_ARCH_4 = 4, 432 BASE_ARCH_4T = 4, 433 BASE_ARCH_5T = 5, 434 BASE_ARCH_5TE = 5, 435 BASE_ARCH_5TEJ = 5, 436 BASE_ARCH_6 = 6, 437 BASE_ARCH_6J = 6, 438 BASE_ARCH_6KZ = 6, 439 BASE_ARCH_6K = 6, 440 BASE_ARCH_6T2 = 6, 441 BASE_ARCH_6M = 6, 442 BASE_ARCH_6Z = 6, 443 BASE_ARCH_7 = 7, 444 BASE_ARCH_7A = 7, 445 BASE_ARCH_7R = 7, 446 BASE_ARCH_7M = 7, 447 BASE_ARCH_7EM = 7, 448 BASE_ARCH_8A = 8, 449 BASE_ARCH_8M_BASE = 8, 450 BASE_ARCH_8M_MAIN = 8, 451 BASE_ARCH_8R = 8, 452 BASE_ARCH_9A = 9 453 }; 454 455 /* The major revision number of the ARM Architecture implemented by the target. */ 456 extern enum base_architecture arm_base_arch; 457 458 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 459 extern int arm_arch4; 460 461 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 462 extern int arm_arch4t; 463 464 /* Nonzero if this chip supports the ARM Architecture 5T extensions. */ 465 extern int arm_arch5t; 466 467 /* Nonzero if this chip supports the ARM Architecture 5TE extensions. */ 468 extern int arm_arch5te; 469 470 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 471 extern int arm_arch6; 472 473 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 474 extern int arm_arch6k; 475 476 /* Nonzero if instructions present in ARMv6-M can be used. */ 477 extern int arm_arch6m; 478 479 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 480 extern int arm_arch7; 481 482 /* Nonzero if instructions not present in the 'M' profile can be used. */ 483 extern int arm_arch_notm; 484 485 /* Nonzero if instructions present in ARMv7E-M can be used. */ 486 extern int arm_arch7em; 487 488 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ 489 extern int arm_arch8; 490 491 /* Nonzero if this chip supports the ARM Architecture 8.1 extensions. */ 492 extern int arm_arch8_1; 493 494 /* Nonzero if this chip supports the ARM Architecture 8.2 extensions. */ 495 extern int arm_arch8_2; 496 497 /* Nonzero if this chip supports the ARM Architecture 8.3 extensions. */ 498 extern int arm_arch8_3; 499 500 /* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */ 501 extern int arm_arch8_4; 502 503 /* Nonzero if this chip supports the ARM Architecture 8.1-M Mainline 504 extensions. */ 505 extern int arm_arch8_1m_main; 506 507 /* Nonzero if this chip supports the FP16 instructions extension of ARM 508 Architecture 8.2. */ 509 extern int arm_fp16_inst; 510 511 /* Nonzero if this chip can benefit from load scheduling. */ 512 extern int arm_ld_sched; 513 514 /* Nonzero if this chip is a StrongARM. */ 515 extern int arm_tune_strongarm; 516 517 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 518 extern int arm_arch_iwmmxt; 519 520 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ 521 extern int arm_arch_iwmmxt2; 522 523 /* Nonzero if this chip is an XScale. */ 524 extern int arm_arch_xscale; 525 526 /* Nonzero if tuning for XScale. */ 527 extern int arm_tune_xscale; 528 529 /* Nonzero if tuning for stores via the write buffer. */ 530 extern int arm_tune_wbuf; 531 532 /* Nonzero if tuning for Cortex-A9. */ 533 extern int arm_tune_cortex_a9; 534 535 /* Nonzero if we should define __THUMB_INTERWORK__ in the 536 preprocessor. 537 XXX This is a bit of a hack, it's intended to help work around 538 problems in GLD which doesn't understand that armv5t code is 539 interworking clean. */ 540 extern int arm_cpp_interwork; 541 542 /* Nonzero if chip supports Thumb 1. */ 543 extern int arm_arch_thumb1; 544 545 /* Nonzero if chip supports Thumb 2. */ 546 extern int arm_arch_thumb2; 547 548 /* Nonzero if chip supports integer division instruction in ARM mode. */ 549 extern int arm_arch_arm_hwdiv; 550 551 /* Nonzero if chip supports integer division instruction in Thumb mode. */ 552 extern int arm_arch_thumb_hwdiv; 553 554 /* Nonzero if chip disallows volatile memory access in IT block. */ 555 extern int arm_arch_no_volatile_ce; 556 557 /* Nonzero if we shouldn't use literal pools. */ 558 #ifndef USED_FOR_TARGET 559 extern bool arm_disable_literal_pool; 560 #endif 561 562 /* Nonzero if chip supports the ARMv8 CRC instructions. */ 563 extern int arm_arch_crc; 564 565 /* Nonzero if chip supports the ARMv8-M Security Extensions. */ 566 extern int arm_arch_cmse; 567 568 /* Nonzero if chip supports the I8MM instructions. */ 569 extern int arm_arch_i8mm; 570 571 /* Nonzero if chip supports the BFloat16 instructions. */ 572 extern int arm_arch_bf16; 573 574 /* Nonzero if chip supports the Custom Datapath Extension. */ 575 extern int arm_arch_cde; 576 extern int arm_arch_cde_coproc; 577 extern const int arm_arch_cde_coproc_bits[]; 578 #define ARM_CDE_CONST_COPROC 7 579 #define ARM_CCDE_CONST_1 ((1 << 13) - 1) 580 #define ARM_CCDE_CONST_2 ((1 << 9 ) - 1) 581 #define ARM_CCDE_CONST_3 ((1 << 6 ) - 1) 582 #define ARM_VCDE_CONST_1 ((1 << 11) - 1) 583 #define ARM_VCDE_CONST_2 ((1 << 6 ) - 1) 584 #define ARM_VCDE_CONST_3 ((1 << 3 ) - 1) 585 #define ARM_MVE_CDE_CONST_1 ((1 << 12) - 1) 586 #define ARM_MVE_CDE_CONST_2 ((1 << 7 ) - 1) 587 #define ARM_MVE_CDE_CONST_3 ((1 << 4 ) - 1) 588 589 #ifndef TARGET_DEFAULT 590 #define TARGET_DEFAULT (MASK_APCS_FRAME) 591 #endif 592 593 /* Nonzero if PIC code requires explicit qualifiers to generate 594 PLT and GOT relocs rather than the assembler doing so implicitly. 595 Subtargets can override these if required. */ 596 #ifndef NEED_GOT_RELOC 597 #define NEED_GOT_RELOC 0 598 #endif 599 #ifndef NEED_PLT_RELOC 600 #define NEED_PLT_RELOC 0 601 #endif 602 603 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 604 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 605 #endif 606 607 /* Nonzero if we need to refer to the GOT with a PC-relative 608 offset. In other words, generate 609 610 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 611 612 rather than 613 614 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 615 616 The default is true, which matches NetBSD. Subtargets can 617 override this if required. */ 618 #ifndef GOT_PCREL 619 #define GOT_PCREL 1 620 #endif 621 622 /* Target machine storage Layout. */ 623 624 /* Nonzero if this chip provides Armv8.1-M Mainline 625 LOB (low overhead branch features) extension instructions. */ 626 #define TARGET_HAVE_LOB (arm_arch8_1m_main) 627 628 /* Define this macro if it is advisable to hold scalars in registers 629 in a wider mode than that declared by the program. In such cases, 630 the value is constrained to be within the bounds of the declared 631 type, but kept valid in the wider mode. The signedness of the 632 extension may differ from that of the type. */ 633 634 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 635 if (GET_MODE_CLASS (MODE) == MODE_INT \ 636 && GET_MODE_SIZE (MODE) < 4) \ 637 { \ 638 (MODE) = SImode; \ 639 } 640 641 /* Define this if most significant bit is lowest numbered 642 in instructions that operate on numbered bit-fields. */ 643 #define BITS_BIG_ENDIAN 0 644 645 /* Define this if most significant byte of a word is the lowest numbered. 646 Most ARM processors are run in little endian mode, so that is the default. 647 If you want to have it run-time selectable, change the definition in a 648 cover file to be TARGET_BIG_ENDIAN. */ 649 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 650 651 /* Define this if most significant word of a multiword number is the lowest 652 numbered. */ 653 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 654 655 #define UNITS_PER_WORD 4 656 657 /* True if natural alignment is used for doubleword types. */ 658 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 659 660 #define DOUBLEWORD_ALIGNMENT 64 661 662 #define PARM_BOUNDARY 32 663 664 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 665 666 #define PREFERRED_STACK_BOUNDARY \ 667 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 668 669 #define FUNCTION_BOUNDARY_P(flags) (TARGET_THUMB_P (flags) ? 16 : 32) 670 #define FUNCTION_BOUNDARY (FUNCTION_BOUNDARY_P (target_flags)) 671 672 /* The lowest bit is used to indicate Thumb-mode functions, so the 673 vbit must go into the delta field of pointers to member 674 functions. */ 675 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 676 677 #define EMPTY_FIELD_BOUNDARY 32 678 679 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 680 681 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 682 683 /* XXX Blah -- this macro is used directly by libobjc. Since it 684 supports no vector modes, cut out the complexity and fall back 685 on BIGGEST_FIELD_ALIGNMENT. */ 686 #ifdef IN_TARGET_LIBS 687 #define BIGGEST_FIELD_ALIGNMENT 64 688 #endif 689 690 /* Align definitions of arrays, unions and structures so that 691 initializations and copies can be made more efficient. This is not 692 ABI-changing, so it only affects places where we can see the 693 definition. Increasing the alignment tends to introduce padding, 694 so don't do this when optimizing for size/conserving stack space. */ 695 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 696 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 697 && (TREE_CODE (EXP) == ARRAY_TYPE \ 698 || TREE_CODE (EXP) == UNION_TYPE \ 699 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 700 701 /* Align global data. */ 702 #define DATA_ALIGNMENT(EXP, ALIGN) \ 703 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 704 705 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 706 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 707 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 708 709 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 710 value set in previous versions of this toolchain was 8, which produces more 711 compact structures. The command line option -mstructure_size_boundary=<n> 712 can be used to change this value. For compatibility with the ARM SDK 713 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 714 0020D) page 2-20 says "Structures are aligned on word boundaries". 715 The AAPCS specifies a value of 8. */ 716 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 717 718 /* This is the value used to initialize arm_structure_size_boundary. If a 719 particular arm target wants to change the default value it should change 720 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 721 for an example of this. */ 722 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 723 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 724 #endif 725 726 /* Nonzero if move instructions will actually fail to work 727 when given unaligned data. */ 728 #define STRICT_ALIGNMENT 1 729 730 /* wchar_t is unsigned under the AAPCS. */ 731 #ifndef WCHAR_TYPE 732 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 733 734 #define WCHAR_TYPE_SIZE BITS_PER_WORD 735 #endif 736 737 /* Sized for fixed-point types. */ 738 739 #define SHORT_FRACT_TYPE_SIZE 8 740 #define FRACT_TYPE_SIZE 16 741 #define LONG_FRACT_TYPE_SIZE 32 742 #define LONG_LONG_FRACT_TYPE_SIZE 64 743 744 #define SHORT_ACCUM_TYPE_SIZE 16 745 #define ACCUM_TYPE_SIZE 32 746 #define LONG_ACCUM_TYPE_SIZE 64 747 #define LONG_LONG_ACCUM_TYPE_SIZE 64 748 749 #define MAX_FIXED_MODE_SIZE 64 750 751 #ifndef SIZE_TYPE 752 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 753 #endif 754 755 #ifndef PTRDIFF_TYPE 756 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 757 #endif 758 759 /* AAPCS requires that structure alignment is affected by bitfields. */ 760 #ifndef PCC_BITFIELD_TYPE_MATTERS 761 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 762 #endif 763 764 /* The maximum size of the sync library functions supported. */ 765 #ifndef MAX_SYNC_LIBFUNC_SIZE 766 #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD) 767 #endif 768 769 770 /* Standard register usage. */ 771 772 /* Register allocation in ARM Procedure Call Standard 773 (S - saved over call, F - Frame-related). 774 775 r0 * argument word/integer result 776 r1-r3 argument word 777 778 r4-r8 S register variable 779 r9 S (rfp) register variable (real frame pointer) 780 781 r10 F S (sl) stack limit (used by -mapcs-stack-check) 782 r11 F S (fp) argument pointer 783 r12 (ip) temp workspace 784 r13 F S (sp) lower end of current stack frame 785 r14 (lr) link address/workspace 786 r15 F (pc) program counter 787 788 cc This is NOT a real register, but is used internally 789 to represent things that use or set the condition 790 codes. 791 sfp This isn't either. It is used during rtl generation 792 since the offset between the frame pointer and the 793 auto's isn't known until after register allocation. 794 afp Nor this, we only need this because of non-local 795 goto. Without it fp appears to be used and the 796 elimination code won't get rid of sfp. It tracks 797 fp exactly at all times. 798 apsrq Nor this, it is used to track operations on the Q bit 799 of APSR by ACLE saturating intrinsics. 800 apsrge Nor this, it is used to track operations on the GE bits 801 of APSR by ACLE SIMD32 intrinsics 802 803 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 804 805 /* s0-s15 VFP scratch (aka d0-d7). 806 s16-s31 S VFP variable (aka d8-d15). 807 vfpcc Not a real register. Represents the VFP condition 808 code flags. 809 vpr Used to represent MVE VPR predication. */ 810 811 /* The stack backtrace structure is as follows: 812 fp points to here: | save code pointer | [fp] 813 | return link value | [fp, #-4] 814 | return sp value | [fp, #-8] 815 | return fp value | [fp, #-12] 816 [| saved r10 value |] 817 [| saved r9 value |] 818 [| saved r8 value |] 819 [| saved r7 value |] 820 [| saved r6 value |] 821 [| saved r5 value |] 822 [| saved r4 value |] 823 [| saved r3 value |] 824 [| saved r2 value |] 825 [| saved r1 value |] 826 [| saved r0 value |] 827 r0-r3 are not normally saved in a C function. */ 828 829 /* 1 for registers that have pervasive standard uses 830 and are not available for the register allocator. */ 831 #define FIXED_REGISTERS \ 832 { \ 833 /* Core regs. */ \ 834 0,0,0,0,0,0,0,0, \ 835 0,0,0,0,0,1,0,1, \ 836 /* VFP regs. */ \ 837 1,1,1,1,1,1,1,1, \ 838 1,1,1,1,1,1,1,1, \ 839 1,1,1,1,1,1,1,1, \ 840 1,1,1,1,1,1,1,1, \ 841 1,1,1,1,1,1,1,1, \ 842 1,1,1,1,1,1,1,1, \ 843 1,1,1,1,1,1,1,1, \ 844 1,1,1,1,1,1,1,1, \ 845 /* IWMMXT regs. */ \ 846 1,1,1,1,1,1,1,1, \ 847 1,1,1,1,1,1,1,1, \ 848 1,1,1,1, \ 849 /* Specials. */ \ 850 1,1,1,1,1,1,1 \ 851 } 852 853 /* 1 for registers not available across function calls. 854 These must include the FIXED_REGISTERS and also any 855 registers that can be used without being saved. 856 The latter must include the registers where values are returned 857 and the register where structure-value addresses are passed. 858 Aside from that, you can include as many other registers as you like. 859 The CC is not preserved over function calls on the ARM 6, so it is 860 easier to assume this for all. SFP is preserved, since FP is. */ 861 #define CALL_USED_REGISTERS \ 862 { \ 863 /* Core regs. */ \ 864 1,1,1,1,0,0,0,0, \ 865 0,0,0,0,1,1,1,1, \ 866 /* VFP Regs. */ \ 867 1,1,1,1,1,1,1,1, \ 868 1,1,1,1,1,1,1,1, \ 869 1,1,1,1,1,1,1,1, \ 870 1,1,1,1,1,1,1,1, \ 871 1,1,1,1,1,1,1,1, \ 872 1,1,1,1,1,1,1,1, \ 873 1,1,1,1,1,1,1,1, \ 874 1,1,1,1,1,1,1,1, \ 875 /* IWMMXT regs. */ \ 876 1,1,1,1,1,1,1,1, \ 877 1,1,1,1,1,1,1,1, \ 878 1,1,1,1, \ 879 /* Specials. */ \ 880 1,1,1,1,1,1,1 \ 881 } 882 883 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 884 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 885 #endif 886 887 /* These are a couple of extensions to the formats accepted 888 by asm_fprintf: 889 %@ prints out ASM_COMMENT_START 890 %r prints out REGISTER_PREFIX reg_names[arg] */ 891 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 892 case '@': \ 893 fputs (ASM_COMMENT_START, FILE); \ 894 break; \ 895 \ 896 case 'r': \ 897 fputs (REGISTER_PREFIX, FILE); \ 898 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 899 break; 900 901 /* Round X up to the nearest word. */ 902 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 903 904 /* Convert fron bytes to ints. */ 905 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 906 907 /* The number of (integer) registers required to hold a quantity of type MODE. 908 Also used for VFP registers. */ 909 #define ARM_NUM_REGS(MODE) \ 910 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 911 912 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 913 #define ARM_NUM_REGS2(MODE, TYPE) \ 914 ARM_NUM_INTS ((MODE) == BLKmode ? \ 915 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 916 917 /* The number of (integer) argument register available. */ 918 #define NUM_ARG_REGS 4 919 920 /* And similarly for the VFP. */ 921 #define NUM_VFP_ARG_REGS 16 922 923 /* Return the register number of the N'th (integer) argument. */ 924 #define ARG_REGISTER(N) (N - 1) 925 926 /* Specify the registers used for certain standard purposes. 927 The values of these macros are register numbers. */ 928 929 /* The number of the last argument register. */ 930 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 931 932 /* The numbers of the Thumb register ranges. */ 933 #define FIRST_LO_REGNUM 0 934 #define LAST_LO_REGNUM 7 935 #define FIRST_HI_REGNUM 8 936 #define LAST_HI_REGNUM 11 937 938 /* Overridden by config/arm/bpabi.h. */ 939 #ifndef ARM_UNWIND_INFO 940 #define ARM_UNWIND_INFO 0 941 #endif 942 943 /* Overriden by config/arm/netbsd-eabi.h. */ 944 #ifndef ARM_DWARF_UNWIND_TABLES 945 #define ARM_DWARF_UNWIND_TABLES 0 946 #endif 947 948 /* Use r0 and r1 to pass exception handling information. */ 949 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 950 951 /* The register that holds the return address in exception handlers. */ 952 #define ARM_EH_STACKADJ_REGNUM 2 953 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 954 955 #ifndef ARM_TARGET2_DWARF_FORMAT 956 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel 957 #endif 958 959 #if ARM_DWARF_UNWIND_TABLES 960 /* DWARF unwinding uses the normal indirect/pcrel vs absptr format 961 for 32bit platforms. */ 962 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 963 (flag_pic ? (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 964 : DW_EH_PE_absptr) 965 #else 966 /* ttype entries (the only interesting data references used) 967 use TARGET2 relocations. */ 968 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 969 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ 970 : DW_EH_PE_absptr) 971 #endif 972 973 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 974 as an invisible last argument (possible since varargs don't exist in 975 Pascal), so the following is not true. */ 976 #define STATIC_CHAIN_REGNUM 12 977 978 /* r9 is the FDPIC register (base register for GOT and FUNCDESC accesses). */ 979 #define FDPIC_REGNUM 9 980 981 /* Define this to be where the real frame pointer is if it is not possible to 982 work out the offset between the frame pointer and the automatic variables 983 until after register allocation has taken place. FRAME_POINTER_REGNUM 984 should point to a special register that we will make sure is eliminated. 985 986 For the Thumb we have another problem. The TPCS defines the frame pointer 987 as r11, and GCC believes that it is always possible to use the frame pointer 988 as base register for addressing purposes. (See comments in 989 find_reloads_address()). But - the Thumb does not allow high registers, 990 including r11, to be used as base address registers. Hence our problem. 991 992 The solution used here, and in the old thumb port is to use r7 instead of 993 r11 as the hard frame pointer and to have special code to generate 994 backtrace structures on the stack (if required to do so via a command line 995 option) using r11. This is the only 'user visible' use of r11 as a frame 996 pointer. */ 997 #define ARM_HARD_FRAME_POINTER_REGNUM 11 998 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 999 1000 #define HARD_FRAME_POINTER_REGNUM \ 1001 (TARGET_ARM \ 1002 ? ARM_HARD_FRAME_POINTER_REGNUM \ 1003 : THUMB_HARD_FRAME_POINTER_REGNUM) 1004 1005 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 1006 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 1007 1008 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 1009 1010 /* Register to use for pushing function arguments. */ 1011 #define STACK_POINTER_REGNUM SP_REGNUM 1012 1013 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) 1014 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) 1015 1016 /* Need to sync with WCGR in iwmmxt.md. */ 1017 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) 1018 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) 1019 1020 #define IS_IWMMXT_REGNUM(REGNUM) \ 1021 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 1022 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 1023 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 1024 1025 /* Base register for access to local variables of the function. */ 1026 #define FRAME_POINTER_REGNUM 102 1027 1028 /* Base register for access to arguments of the function. */ 1029 #define ARG_POINTER_REGNUM 103 1030 1031 #define FIRST_VFP_REGNUM 16 1032 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) 1033 #define LAST_VFP_REGNUM \ 1034 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 1035 1036 #define IS_VFP_REGNUM(REGNUM) \ 1037 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 1038 1039 /* VFP registers are split into two types: those defined by VFP versions < 3 1040 have D registers overlaid on consecutive pairs of S registers. VFP version 3 1041 defines 16 new D registers (d16-d31) which, for simplicity and correctness 1042 in various parts of the backend, we implement as "fake" single-precision 1043 registers (which would be S32-S63, but cannot be used in that way). The 1044 following macros define these ranges of registers. */ 1045 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) 1046 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) 1047 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) 1048 1049 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 1050 ((REGNUM) <= LAST_LO_VFP_REGNUM) 1051 1052 /* DFmode values are only valid in even register pairs. */ 1053 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 1054 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 1055 1056 /* Neon Quad values must start at a multiple of four registers. */ 1057 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 1058 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 1059 1060 /* Neon structures of vectors must be in even register pairs and there 1061 must be enough registers available. Because of various patterns 1062 requiring quad registers, we require them to start at a multiple of 1063 four. */ 1064 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 1065 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 1066 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 1067 1068 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP 1069 + 1 APSRQ + 1 APSRGE + 1 VPR. */ 1070 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1071 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ 1072 #define FIRST_PSEUDO_REGISTER 107 1073 1074 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1075 1076 /* Value should be nonzero if functions must have frame pointers. 1077 Zero means the frame pointer need not be set up (and parms may be accessed 1078 via the stack pointer) in functions that seem suitable. 1079 If we have to have a frame pointer we might as well make use of it. 1080 APCS says that the frame pointer does not need to be pushed in leaf 1081 functions, or simple tail call functions. */ 1082 1083 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1084 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1085 #endif 1086 1087 #define VALID_IWMMXT_REG_MODE(MODE) \ 1088 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1089 1090 /* Modes valid for Neon D registers. */ 1091 #define VALID_NEON_DREG_MODE(MODE) \ 1092 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1093 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode \ 1094 || (MODE) == V4BFmode) 1095 1096 /* Modes valid for Neon Q registers. */ 1097 #define VALID_NEON_QREG_MODE(MODE) \ 1098 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1099 || (MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DImode \ 1100 || (MODE) == V8BFmode) 1101 1102 #define VALID_MVE_MODE(MODE) \ 1103 ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ 1104 || (MODE) == V16QImode || (MODE) == V8HFmode || (MODE) == V4SFmode \ 1105 || (MODE) == V2DFmode) 1106 1107 #define VALID_MVE_SI_MODE(MODE) \ 1108 ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ 1109 || (MODE) == V16QImode) 1110 1111 /* Modes used in MVE's narrowing stores or widening loads. */ 1112 #define MVE_STN_LDW_MODE(MODE) \ 1113 ((MODE) == V4QImode || (MODE) == V8QImode || (MODE) == V4HImode) 1114 1115 #define VALID_MVE_SF_MODE(MODE) \ 1116 ((MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DFmode) 1117 1118 /* Structure modes valid for Neon registers. */ 1119 #define VALID_NEON_STRUCT_MODE(MODE) \ 1120 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1121 || (MODE) == CImode || (MODE) == XImode) 1122 1123 #define VALID_MVE_STRUCT_MODE(MODE) \ 1124 ((MODE) == TImode || (MODE) == OImode || (MODE) == XImode) 1125 1126 /* The conditions under which vector modes are supported for general 1127 arithmetic using Neon. */ 1128 1129 #define ARM_HAVE_NEON_V8QI_ARITH TARGET_NEON 1130 #define ARM_HAVE_NEON_V4HI_ARITH TARGET_NEON 1131 #define ARM_HAVE_NEON_V2SI_ARITH TARGET_NEON 1132 1133 #define ARM_HAVE_NEON_V16QI_ARITH TARGET_NEON 1134 #define ARM_HAVE_NEON_V8HI_ARITH TARGET_NEON 1135 #define ARM_HAVE_NEON_V4SI_ARITH TARGET_NEON 1136 #define ARM_HAVE_NEON_V2DI_ARITH TARGET_NEON 1137 1138 /* HF operations have their own flush-to-zero control (FPSCR.FZ16). */ 1139 #define ARM_HAVE_NEON_V4HF_ARITH TARGET_NEON_FP16INST 1140 #define ARM_HAVE_NEON_V8HF_ARITH TARGET_NEON_FP16INST 1141 1142 /* SF operations always flush to zero, regardless of FPSCR.FZ, so we can 1143 only use them for general arithmetic when -funsafe-math-optimizations 1144 is in effect. */ 1145 #define ARM_HAVE_NEON_V2SF_ARITH \ 1146 (TARGET_NEON && flag_unsafe_math_optimizations) 1147 #define ARM_HAVE_NEON_V4SF_ARITH ARM_HAVE_NEON_V2SF_ARITH 1148 1149 /* The conditions under which vector modes are supported for general 1150 arithmetic by any vector extension. */ 1151 1152 #define ARM_HAVE_V8QI_ARITH (ARM_HAVE_NEON_V8QI_ARITH || TARGET_REALLY_IWMMXT) 1153 #define ARM_HAVE_V4HI_ARITH (ARM_HAVE_NEON_V4HI_ARITH || TARGET_REALLY_IWMMXT) 1154 #define ARM_HAVE_V2SI_ARITH (ARM_HAVE_NEON_V2SI_ARITH || TARGET_REALLY_IWMMXT) 1155 1156 #define ARM_HAVE_V16QI_ARITH (ARM_HAVE_NEON_V16QI_ARITH || TARGET_HAVE_MVE) 1157 #define ARM_HAVE_V8HI_ARITH (ARM_HAVE_NEON_V8HI_ARITH || TARGET_HAVE_MVE) 1158 #define ARM_HAVE_V4SI_ARITH (ARM_HAVE_NEON_V4SI_ARITH || TARGET_HAVE_MVE) 1159 #define ARM_HAVE_V2DI_ARITH ARM_HAVE_NEON_V2DI_ARITH 1160 1161 #define ARM_HAVE_V4HF_ARITH ARM_HAVE_NEON_V4HF_ARITH 1162 #define ARM_HAVE_V2SF_ARITH ARM_HAVE_NEON_V2SF_ARITH 1163 1164 #define ARM_HAVE_V8HF_ARITH (ARM_HAVE_NEON_V8HF_ARITH || TARGET_HAVE_MVE_FLOAT) 1165 #define ARM_HAVE_V4SF_ARITH (ARM_HAVE_NEON_V4SF_ARITH || TARGET_HAVE_MVE_FLOAT) 1166 1167 /* The conditions under which vector modes are supported by load/store 1168 instructions using Neon. */ 1169 1170 #define ARM_HAVE_NEON_V8QI_LDST TARGET_NEON 1171 #define ARM_HAVE_NEON_V16QI_LDST TARGET_NEON 1172 #define ARM_HAVE_NEON_V4HI_LDST TARGET_NEON 1173 #define ARM_HAVE_NEON_V8HI_LDST TARGET_NEON 1174 #define ARM_HAVE_NEON_V2SI_LDST TARGET_NEON 1175 #define ARM_HAVE_NEON_V4SI_LDST TARGET_NEON 1176 #define ARM_HAVE_NEON_V4HF_LDST TARGET_NEON_FP16INST 1177 #define ARM_HAVE_NEON_V8HF_LDST TARGET_NEON_FP16INST 1178 #define ARM_HAVE_NEON_V4BF_LDST TARGET_BF16_SIMD 1179 #define ARM_HAVE_NEON_V8BF_LDST TARGET_BF16_SIMD 1180 #define ARM_HAVE_NEON_V2SF_LDST TARGET_NEON 1181 #define ARM_HAVE_NEON_V4SF_LDST TARGET_NEON 1182 #define ARM_HAVE_NEON_DI_LDST TARGET_NEON 1183 #define ARM_HAVE_NEON_V2DI_LDST TARGET_NEON 1184 1185 /* The conditions under which vector modes are supported by load/store 1186 instructions by any vector extension. */ 1187 1188 #define ARM_HAVE_V8QI_LDST (ARM_HAVE_NEON_V8QI_LDST || TARGET_REALLY_IWMMXT) 1189 #define ARM_HAVE_V4HI_LDST (ARM_HAVE_NEON_V4HI_LDST || TARGET_REALLY_IWMMXT) 1190 #define ARM_HAVE_V2SI_LDST (ARM_HAVE_NEON_V2SI_LDST || TARGET_REALLY_IWMMXT) 1191 1192 #define ARM_HAVE_V16QI_LDST (ARM_HAVE_NEON_V16QI_LDST || TARGET_HAVE_MVE) 1193 #define ARM_HAVE_V8HI_LDST (ARM_HAVE_NEON_V8HI_LDST || TARGET_HAVE_MVE) 1194 #define ARM_HAVE_V4SI_LDST (ARM_HAVE_NEON_V4SI_LDST || TARGET_HAVE_MVE) 1195 #define ARM_HAVE_DI_LDST ARM_HAVE_NEON_DI_LDST 1196 #define ARM_HAVE_V2DI_LDST ARM_HAVE_NEON_V2DI_LDST 1197 1198 #define ARM_HAVE_V4HF_LDST ARM_HAVE_NEON_V4HF_LDST 1199 #define ARM_HAVE_V2SF_LDST ARM_HAVE_NEON_V2SF_LDST 1200 1201 #define ARM_HAVE_V4BF_LDST ARM_HAVE_NEON_V4BF_LDST 1202 #define ARM_HAVE_V8BF_LDST ARM_HAVE_NEON_V8BF_LDST 1203 1204 #define ARM_HAVE_V8HF_LDST (ARM_HAVE_NEON_V8HF_LDST || TARGET_HAVE_MVE_FLOAT) 1205 #define ARM_HAVE_V4SF_LDST (ARM_HAVE_NEON_V4SF_LDST || TARGET_HAVE_MVE_FLOAT) 1206 1207 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1208 extern int arm_regs_in_sequence[]; 1209 1210 /* The order in which register should be allocated. It is good to use ip 1211 since no saving is required (though calls clobber it) and it never contains 1212 function parameters. It is quite good to use lr since other calls may 1213 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1214 least likely to contain a function parameter; in addition results are 1215 returned in r0. 1216 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1217 then D8-D15. The reason for doing this is to attempt to reduce register 1218 pressure when both single- and double-precision registers are used in a 1219 function. */ 1220 1221 #define VREG(X) (FIRST_VFP_REGNUM + (X)) 1222 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) 1223 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) 1224 1225 #define REG_ALLOC_ORDER \ 1226 { \ 1227 /* General registers. */ \ 1228 3, 2, 1, 0, 12, 14, 4, 5, \ 1229 6, 7, 8, 9, 10, 11, \ 1230 /* High VFP registers. */ \ 1231 VREG(32), VREG(33), VREG(34), VREG(35), \ 1232 VREG(36), VREG(37), VREG(38), VREG(39), \ 1233 VREG(40), VREG(41), VREG(42), VREG(43), \ 1234 VREG(44), VREG(45), VREG(46), VREG(47), \ 1235 VREG(48), VREG(49), VREG(50), VREG(51), \ 1236 VREG(52), VREG(53), VREG(54), VREG(55), \ 1237 VREG(56), VREG(57), VREG(58), VREG(59), \ 1238 VREG(60), VREG(61), VREG(62), VREG(63), \ 1239 /* VFP argument registers. */ \ 1240 VREG(15), VREG(14), VREG(13), VREG(12), \ 1241 VREG(11), VREG(10), VREG(9), VREG(8), \ 1242 VREG(7), VREG(6), VREG(5), VREG(4), \ 1243 VREG(3), VREG(2), VREG(1), VREG(0), \ 1244 /* VFP call-saved registers. */ \ 1245 VREG(16), VREG(17), VREG(18), VREG(19), \ 1246 VREG(20), VREG(21), VREG(22), VREG(23), \ 1247 VREG(24), VREG(25), VREG(26), VREG(27), \ 1248 VREG(28), VREG(29), VREG(30), VREG(31), \ 1249 /* IWMMX registers. */ \ 1250 WREG(0), WREG(1), WREG(2), WREG(3), \ 1251 WREG(4), WREG(5), WREG(6), WREG(7), \ 1252 WREG(8), WREG(9), WREG(10), WREG(11), \ 1253 WREG(12), WREG(13), WREG(14), WREG(15), \ 1254 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ 1255 /* Registers not for general use. */ \ 1256 CC_REGNUM, VFPCC_REGNUM, \ 1257 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 1258 SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \ 1259 APSRGE_REGNUM, VPR_REGNUM \ 1260 } 1261 1262 #define IS_VPR_REGNUM(REGNUM) \ 1263 ((REGNUM) == VPR_REGNUM) 1264 1265 /* Use different register alloc ordering for Thumb. */ 1266 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1267 1268 /* Tell IRA to use the order we define when optimizing for size. */ 1269 #define HONOR_REG_ALLOC_ORDER optimize_function_for_size_p (cfun) 1270 1271 /* Interrupt functions can only use registers that have already been 1272 saved by the prologue, even if they would normally be 1273 call-clobbered. */ 1274 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1275 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1276 df_regs_ever_live_p (DST)) 1277 1278 /* Register and constant classes. */ 1279 1280 /* Register classes. */ 1281 enum reg_class 1282 { 1283 NO_REGS, 1284 LO_REGS, 1285 STACK_REG, 1286 BASE_REGS, 1287 HI_REGS, 1288 CALLER_SAVE_REGS, 1289 EVEN_REG, 1290 GENERAL_REGS, 1291 CORE_REGS, 1292 VFP_D0_D7_REGS, 1293 VFP_LO_REGS, 1294 VFP_HI_REGS, 1295 VFP_REGS, 1296 IWMMXT_REGS, 1297 IWMMXT_GR_REGS, 1298 CC_REG, 1299 VFPCC_REG, 1300 SFP_REG, 1301 AFP_REG, 1302 VPR_REG, 1303 GENERAL_AND_VPR_REGS, 1304 ALL_REGS, 1305 LIM_REG_CLASSES 1306 }; 1307 1308 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1309 1310 /* Give names of register classes as strings for dump file. */ 1311 #define REG_CLASS_NAMES \ 1312 { \ 1313 "NO_REGS", \ 1314 "LO_REGS", \ 1315 "STACK_REG", \ 1316 "BASE_REGS", \ 1317 "HI_REGS", \ 1318 "CALLER_SAVE_REGS", \ 1319 "EVEN_REG", \ 1320 "GENERAL_REGS", \ 1321 "CORE_REGS", \ 1322 "VFP_D0_D7_REGS", \ 1323 "VFP_LO_REGS", \ 1324 "VFP_HI_REGS", \ 1325 "VFP_REGS", \ 1326 "IWMMXT_REGS", \ 1327 "IWMMXT_GR_REGS", \ 1328 "CC_REG", \ 1329 "VFPCC_REG", \ 1330 "SFP_REG", \ 1331 "AFP_REG", \ 1332 "VPR_REG", \ 1333 "GENERAL_AND_VPR_REGS", \ 1334 "ALL_REGS" \ 1335 } 1336 1337 /* Define which registers fit in which classes. 1338 This is an initializer for a vector of HARD_REG_SET 1339 of length N_REG_CLASSES. */ 1340 #define REG_CLASS_CONTENTS \ 1341 { \ 1342 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1343 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1344 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1345 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1346 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1347 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ 1348 { 0x00005555, 0x00000000, 0x00000000, 0x00000000 }, /* EVEN_REGS. */ \ 1349 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1350 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1351 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1352 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ 1353 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ 1354 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ 1355 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ 1356 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ 1357 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ 1358 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ 1359 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ 1360 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ 1361 { 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \ 1362 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000400 }, /* GENERAL_AND_VPR_REGS. */ \ 1363 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000040F } /* ALL_REGS. */ \ 1364 } 1365 1366 #define FP_SYSREGS \ 1367 DEF_FP_SYSREG (FPSCR) \ 1368 DEF_FP_SYSREG (FPSCR_nzcvqc) \ 1369 DEF_FP_SYSREG (VPR) \ 1370 DEF_FP_SYSREG (P0) \ 1371 DEF_FP_SYSREG (FPCXTNS) \ 1372 DEF_FP_SYSREG (FPCXTS) 1373 1374 #define DEF_FP_SYSREG(reg) reg ## _ENUM, 1375 enum vfp_sysregs_encoding { 1376 FP_SYSREGS 1377 NB_FP_SYSREGS 1378 }; 1379 #undef DEF_FP_SYSREG 1380 extern const char *fp_sysreg_names[NB_FP_SYSREGS]; 1381 1382 /* Any of the VFP register classes. */ 1383 #define IS_VFP_CLASS(X) \ 1384 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1385 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1386 1387 /* The same information, inverted: 1388 Return the class number of the smallest class containing 1389 reg number REGNO. This could be a conditional expression 1390 or could index an array. */ 1391 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1392 1393 /* The class value for index registers, and the one for base regs. */ 1394 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1395 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1396 1397 /* For the Thumb the high registers cannot be used as base registers 1398 when addressing quantities in QI or HI mode; if we don't know the 1399 mode, then we must be conservative. For MVE we need to load from 1400 memory to low regs based on given modes i.e [Rn], Rn <= LO_REGS. */ 1401 #define MODE_BASE_REG_CLASS(MODE) \ 1402 (TARGET_HAVE_MVE ? arm_mode_base_reg_class (MODE) \ 1403 :(TARGET_32BIT ? CORE_REGS \ 1404 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ 1405 : LO_REGS)) 1406 1407 /* For Thumb we cannot support SP+reg addressing, so we return LO_REGS 1408 instead of BASE_REGS. */ 1409 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1410 1411 /* When this hook returns true for MODE, the compiler allows 1412 registers explicitly used in the rtl to be used as spill registers 1413 but prevents the compiler from extending the lifetime of these 1414 registers. */ 1415 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1416 arm_small_register_classes_for_mode_p 1417 1418 /* Must leave BASE_REGS reloads alone */ 1419 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1420 (lra_in_progress ? NO_REGS \ 1421 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1422 ? ((true_regnum (X) == -1 ? LO_REGS \ 1423 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ 1424 : NO_REGS)) \ 1425 : NO_REGS)) 1426 1427 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1428 (lra_in_progress ? NO_REGS \ 1429 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1430 ? ((true_regnum (X) == -1 ? LO_REGS \ 1431 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ 1432 : NO_REGS)) \ 1433 : NO_REGS) 1434 1435 /* Return the register class of a scratch register needed to copy IN into 1436 or out of a register in CLASS in MODE. If it can be done directly, 1437 NO_REGS is returned. */ 1438 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1439 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1440 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1441 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1442 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1443 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1444 : TARGET_32BIT \ 1445 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1446 ? GENERAL_REGS : NO_REGS) \ 1447 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1448 1449 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1450 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1451 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1452 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1453 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1454 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1455 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1456 (TARGET_32BIT ? \ 1457 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1458 && CONSTANT_P (X)) \ 1459 ? GENERAL_REGS : \ 1460 (((MODE) == HImode && ! arm_arch4 \ 1461 && (MEM_P (X) \ 1462 || ((REG_P (X) || GET_CODE (X) == SUBREG) \ 1463 && true_regnum (X) == -1))) \ 1464 ? GENERAL_REGS : NO_REGS) \ 1465 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1466 1467 /* Return the maximum number of consecutive registers 1468 needed to represent mode MODE in a register of class CLASS. 1469 ARM regs are UNITS_PER_WORD bits. 1470 FIXME: Is this true for iWMMX? */ 1471 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1472 (CLASS == VPR_REG) \ 1473 ? CEIL (GET_MODE_SIZE (MODE), 2) \ 1474 : (ARM_NUM_REGS (MODE)) 1475 1476 /* If defined, gives a class of registers that cannot be used as the 1477 operand of a SUBREG that changes the mode of the object illegally. */ 1478 1479 /* Stack layout; function entry, exit and calling. */ 1480 1481 /* Define this if pushing a word on the stack 1482 makes the stack pointer a smaller address. */ 1483 #define STACK_GROWS_DOWNWARD 1 1484 1485 /* Define this to nonzero if the nominal address of the stack frame 1486 is at the high-address end of the local variables; 1487 that is, each additional local variable allocated 1488 goes at a more negative offset in the frame. */ 1489 #define FRAME_GROWS_DOWNWARD 1 1490 1491 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1492 When present, it is one word in size, and sits at the top of the frame, 1493 between the soft frame pointer and either r7 or r11. 1494 1495 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1496 and only then if some outgoing arguments are passed on the stack. It would 1497 be tempting to also check whether the stack arguments are passed by indirect 1498 calls, but there seems to be no reason in principle why a post-reload pass 1499 couldn't convert a direct call into an indirect one. */ 1500 #define CALLER_INTERWORKING_SLOT_SIZE \ 1501 (TARGET_CALLER_INTERWORKING \ 1502 && maybe_ne (crtl->outgoing_args_size, 0) \ 1503 ? UNITS_PER_WORD : 0) 1504 1505 /* If we generate an insn to push BYTES bytes, 1506 this says how many the stack pointer really advances by. */ 1507 /* The push insns do not do this rounding implicitly. 1508 So don't define this. */ 1509 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1510 1511 /* Define this if the maximum size of all the outgoing args is to be 1512 accumulated and pushed during the prologue. The amount can be 1513 found in the variable crtl->outgoing_args_size. */ 1514 #define ACCUMULATE_OUTGOING_ARGS 1 1515 1516 /* Offset of first parameter from the argument pointer register value. */ 1517 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1518 1519 /* Amount of memory needed for an untyped call to save all possible return 1520 registers. */ 1521 #define APPLY_RESULT_SIZE arm_apply_result_size() 1522 1523 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1524 values must be in memory. On the ARM, they need only do so if larger 1525 than a word, or if they contain elements offset from zero in the struct. */ 1526 #define DEFAULT_PCC_STRUCT_RETURN 0 1527 1528 /* These bits describe the different types of function supported 1529 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1530 normal function and an interworked function, for example. Knowing the 1531 type of a function is important for determining its prologue and 1532 epilogue sequences. 1533 Note value 7 is currently unassigned. Also note that the interrupt 1534 function types all have bit 2 set, so that they can be tested for easily. 1535 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1536 machine_function structure is initialized (to zero) func_type will 1537 default to unknown. This will force the first use of arm_current_func_type 1538 to call arm_compute_func_type. */ 1539 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1540 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1541 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1542 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1543 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1544 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1545 1546 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1547 1548 /* In addition functions can have several type modifiers, 1549 outlined by these bit masks: */ 1550 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1551 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1552 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1553 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1554 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1555 #define ARM_FT_CMSE_ENTRY (1 << 7) /* ARMv8-M non-secure entry function. */ 1556 1557 /* Some macros to test these flags. */ 1558 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1559 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1560 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1561 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1562 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1563 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1564 #define IS_CMSE_ENTRY(t) (t & ARM_FT_CMSE_ENTRY) 1565 1566 1567 /* Structure used to hold the function stack frame layout. Offsets are 1568 relative to the stack pointer on function entry. Positive offsets are 1569 in the direction of stack growth. 1570 Only soft_frame is used in thumb mode. */ 1571 1572 typedef struct GTY(()) arm_stack_offsets 1573 { 1574 int saved_args; /* ARG_POINTER_REGNUM. */ 1575 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1576 int saved_regs; 1577 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1578 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1579 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1580 unsigned int saved_regs_mask; 1581 } 1582 arm_stack_offsets; 1583 1584 #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET) 1585 /* A C structure for machine-specific, per-function data. 1586 This is added to the cfun structure. */ 1587 typedef struct GTY(()) machine_function 1588 { 1589 /* Additional stack adjustment in __builtin_eh_throw. */ 1590 rtx eh_epilogue_sp_ofs; 1591 /* Records if LR has to be saved for far jumps. */ 1592 int far_jump_used; 1593 /* Records if ARG_POINTER was ever live. */ 1594 int arg_pointer_live; 1595 /* Records if the save of LR has been eliminated. */ 1596 int lr_save_eliminated; 1597 /* The size of the stack frame. Only valid after reload. */ 1598 arm_stack_offsets stack_offsets; 1599 /* Records the type of the current function. */ 1600 unsigned long func_type; 1601 /* Record if the function has a variable argument list. */ 1602 int uses_anonymous_args; 1603 /* Records if sibcalls are blocked because an argument 1604 register is needed to preserve stack alignment. */ 1605 int sibcall_blocked; 1606 /* The PIC register for this function. This might be a pseudo. */ 1607 rtx pic_reg; 1608 /* Labels for per-function Thumb call-via stubs. One per potential calling 1609 register. We can never call via LR or PC. We can call via SP if a 1610 trampoline happens to be on the top of the stack. */ 1611 rtx call_via[14]; 1612 /* Set to 1 when a return insn is output, this means that the epilogue 1613 is not needed. */ 1614 int return_used_this_function; 1615 /* When outputting Thumb-1 code, record the last insn that provides 1616 information about condition codes, and the comparison operands. */ 1617 rtx thumb1_cc_insn; 1618 rtx thumb1_cc_op0; 1619 rtx thumb1_cc_op1; 1620 /* Also record the CC mode that is supported. */ 1621 machine_mode thumb1_cc_mode; 1622 /* Set to 1 after arm_reorg has started. */ 1623 int after_arm_reorg; 1624 /* The number of bytes used to store the static chain register on the 1625 stack, above the stack frame. */ 1626 int static_chain_stack_bytes; 1627 } 1628 machine_function; 1629 #endif 1630 1631 #define ARM_Q_BIT_READ (arm_q_bit_access ()) 1632 #define ARM_GE_BITS_READ (arm_ge_bits_access ()) 1633 1634 /* As in the machine_function, a global set of call-via labels, for code 1635 that is in text_section. */ 1636 extern GTY(()) rtx thumb_call_via_label[14]; 1637 1638 /* The number of potential ways of assigning to a co-processor. */ 1639 #define ARM_NUM_COPROC_SLOTS 1 1640 1641 /* Enumeration of procedure calling standard variants. We don't really 1642 support all of these yet. */ 1643 enum arm_pcs 1644 { 1645 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1646 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1647 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1648 /* This must be the last AAPCS variant. */ 1649 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1650 ARM_PCS_ATPCS, /* ATPCS. */ 1651 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1652 ARM_PCS_UNKNOWN 1653 }; 1654 1655 /* Default procedure calling standard of current compilation unit. */ 1656 extern enum arm_pcs arm_pcs_default; 1657 1658 #if !defined (USED_FOR_TARGET) 1659 /* A C type for declaring a variable that is used as the first argument of 1660 `FUNCTION_ARG' and other related values. */ 1661 typedef struct 1662 { 1663 /* This is the number of registers of arguments scanned so far. */ 1664 int nregs; 1665 /* This is the number of iWMMXt register arguments scanned so far. */ 1666 int iwmmxt_nregs; 1667 int named_count; 1668 int nargs; 1669 /* Which procedure call variant to use for this call. */ 1670 enum arm_pcs pcs_variant; 1671 1672 /* AAPCS related state tracking. */ 1673 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1674 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1675 this argument, or -1 if using core 1676 registers. */ 1677 int aapcs_ncrn; 1678 int aapcs_next_ncrn; 1679 rtx aapcs_reg; /* Register assigned to this argument. */ 1680 int aapcs_partial; /* How many bytes are passed in regs (if 1681 split between core regs and stack. 1682 Zero otherwise. */ 1683 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1684 int can_split; /* Argument can be split between core regs 1685 and the stack. */ 1686 /* Private data for tracking VFP register allocation */ 1687 unsigned aapcs_vfp_regs_free; 1688 unsigned aapcs_vfp_reg_alloc; 1689 int aapcs_vfp_rcount; 1690 MACHMODE aapcs_vfp_rmode; 1691 } CUMULATIVE_ARGS; 1692 #endif 1693 1694 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1695 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) 1696 1697 /* For AAPCS, padding should never be below the argument. For other ABIs, 1698 * mimic the default. */ 1699 #define PAD_VARARGS_DOWN \ 1700 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1701 1702 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1703 for a call to a function whose data type is FNTYPE. 1704 For a library call, FNTYPE is 0. 1705 On the ARM, the offset starts at 0. */ 1706 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1707 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1708 1709 /* 1 if N is a possible register number for function argument passing. 1710 On the ARM, r0-r3 are used to pass args. */ 1711 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1712 (IN_RANGE ((REGNO), 0, 3) \ 1713 || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \ 1714 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1715 || (TARGET_IWMMXT_ABI \ 1716 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1717 1718 1719 /* If your target environment doesn't prefix user functions with an 1720 underscore, you may wish to re-define this to prevent any conflicts. */ 1721 #ifndef ARM_MCOUNT_NAME 1722 #define ARM_MCOUNT_NAME "*mcount" 1723 #endif 1724 1725 /* Call the function profiler with a given profile label. The Acorn 1726 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1727 On the ARM the full profile code will look like: 1728 .data 1729 LP1 1730 .word 0 1731 .text 1732 mov ip, lr 1733 bl mcount 1734 .word LP1 1735 1736 profile_function() in final.cc outputs the .data section, FUNCTION_PROFILER 1737 will output the .text section. 1738 1739 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1740 ``prof'' doesn't seem to mind about this! 1741 1742 Note - this version of the code is designed to work in both ARM and 1743 Thumb modes. */ 1744 #ifndef ARM_FUNCTION_PROFILER 1745 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1746 { \ 1747 char temp[20]; \ 1748 rtx sym; \ 1749 \ 1750 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1751 IP_REGNUM, LR_REGNUM); \ 1752 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1753 fputc ('\n', STREAM); \ 1754 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1755 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1756 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1757 } 1758 #endif 1759 1760 #ifdef THUMB_FUNCTION_PROFILER 1761 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1762 if (TARGET_ARM) \ 1763 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1764 else \ 1765 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1766 #else 1767 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1768 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1769 #endif 1770 1771 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1772 the stack pointer does not matter. The value is tested only in 1773 functions that have frame pointers. 1774 No definition is equivalent to always zero. 1775 1776 On the ARM, the function epilogue recovers the stack pointer from the 1777 frame. */ 1778 #define EXIT_IGNORE_STACK 1 1779 1780 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) 1781 1782 /* Determine if the epilogue should be output as RTL. 1783 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1784 #define USE_RETURN_INSN(ISCOND) \ 1785 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1786 1787 /* Definitions for register eliminations. 1788 1789 This is an array of structures. Each structure initializes one pair 1790 of eliminable registers. The "from" register number is given first, 1791 followed by "to". Eliminations of the same "from" register are listed 1792 in order of preference. 1793 1794 We have two registers that can be eliminated on the ARM. First, the 1795 arg pointer register can often be eliminated in favor of the stack 1796 pointer register. Secondly, the pseudo frame pointer register can always 1797 be eliminated; it is replaced with either the stack or the real frame 1798 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1799 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1800 1801 #define ELIMINABLE_REGS \ 1802 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1803 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1804 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1805 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1806 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1807 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1808 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1809 1810 /* Define the offset between two registers, one to be eliminated, and the 1811 other its replacement, at the start of a routine. */ 1812 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1813 if (TARGET_ARM) \ 1814 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1815 else \ 1816 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1817 1818 /* Special case handling of the location of arguments passed on the stack. */ 1819 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1820 1821 /* Initialize data used by insn expanders. This is called from insn_emit, 1822 once for every function before code is generated. */ 1823 #define INIT_EXPANDERS arm_init_expanders () 1824 1825 /* Length in units of the trampoline for entering a nested function. */ 1826 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : (TARGET_32BIT ? 16 : 20)) 1827 1828 /* Alignment required for a trampoline in bits. */ 1829 #define TRAMPOLINE_ALIGNMENT 32 1830 1831 /* Addressing modes, and classification of registers for them. */ 1832 #define HAVE_POST_INCREMENT 1 1833 #define HAVE_PRE_INCREMENT TARGET_32BIT 1834 #define HAVE_POST_DECREMENT TARGET_32BIT 1835 #define HAVE_PRE_DECREMENT TARGET_32BIT 1836 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1837 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1838 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1839 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1840 1841 enum arm_auto_incmodes 1842 { 1843 ARM_POST_INC, 1844 ARM_PRE_INC, 1845 ARM_POST_DEC, 1846 ARM_PRE_DEC 1847 }; 1848 1849 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ 1850 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) 1851 #define USE_LOAD_POST_INCREMENT(mode) \ 1852 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) 1853 #define USE_LOAD_PRE_INCREMENT(mode) \ 1854 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) 1855 #define USE_LOAD_POST_DECREMENT(mode) \ 1856 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) 1857 #define USE_LOAD_PRE_DECREMENT(mode) \ 1858 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) 1859 1860 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) 1861 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) 1862 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1863 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1864 1865 /* Macros to check register numbers against specific register classes. */ 1866 1867 /* These assume that REGNO is a hard or pseudo reg number. 1868 They give nonzero only if REGNO is a hard reg of the suitable class 1869 or a pseudo reg currently allocated to a suitable hard reg. */ 1870 #define TEST_REGNO(R, TEST, VALUE) \ 1871 ((R TEST VALUE) \ 1872 || (reg_renumber && ((unsigned) reg_renumber[R] TEST VALUE))) 1873 1874 /* Don't allow the pc to be used. */ 1875 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1876 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1877 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1878 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1879 1880 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1881 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1882 || (GET_MODE_SIZE (MODE) >= 4 \ 1883 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1884 1885 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1886 (TARGET_THUMB1 \ 1887 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1888 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1889 1890 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1891 For Thumb, we cannot use SP + reg, so reject SP. */ 1892 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1893 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1894 1895 /* For ARM code, we don't care about the mode, but for Thumb, the index 1896 must be suitable for use in a QImode load. */ 1897 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1898 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1899 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1900 1901 /* Maximum number of registers that can appear in a valid memory address. 1902 Shifts in addresses can't be by a register. */ 1903 #define MAX_REGS_PER_ADDRESS 2 1904 1905 /* Recognize any constant value that is a valid address. */ 1906 /* XXX We can address any constant, eventually... */ 1907 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1908 #define CONSTANT_ADDRESS_P(X) \ 1909 (GET_CODE (X) == SYMBOL_REF \ 1910 && (CONSTANT_POOL_ADDRESS_P (X) \ 1911 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1912 1913 /* True if SYMBOL + OFFSET constants must refer to something within 1914 SYMBOL's section. */ 1915 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1916 1917 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1918 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1919 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1920 #endif 1921 1922 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1923 #define SUBTARGET_NAME_ENCODING_LENGTHS 1924 #endif 1925 1926 /* This is a C fragment for the inside of a switch statement. 1927 Each case label should return the number of characters to 1928 be stripped from the start of a function's name, if that 1929 name starts with the indicated character. */ 1930 #define ARM_NAME_ENCODING_LENGTHS \ 1931 case '*': return 1; \ 1932 SUBTARGET_NAME_ENCODING_LENGTHS 1933 1934 /* This is how to output a reference to a user-level label named NAME. 1935 `assemble_name' uses this. */ 1936 #undef ASM_OUTPUT_LABELREF 1937 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1938 arm_asm_output_labelref (FILE, NAME) 1939 1940 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1941 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1942 if (TARGET_THUMB2) \ 1943 thumb2_asm_output_opcode (STREAM); 1944 1945 /* The EABI specifies that constructors should go in .init_array. 1946 Other targets use .ctors for compatibility. */ 1947 #ifndef ARM_EABI_CTORS_SECTION_OP 1948 #define ARM_EABI_CTORS_SECTION_OP \ 1949 "\t.section\t.init_array,\"aw\",%init_array" 1950 #endif 1951 #ifndef ARM_EABI_DTORS_SECTION_OP 1952 #define ARM_EABI_DTORS_SECTION_OP \ 1953 "\t.section\t.fini_array,\"aw\",%fini_array" 1954 #endif 1955 #define ARM_CTORS_SECTION_OP \ 1956 "\t.section\t.ctors,\"aw\",%progbits" 1957 #define ARM_DTORS_SECTION_OP \ 1958 "\t.section\t.dtors,\"aw\",%progbits" 1959 1960 /* Define CTORS_SECTION_ASM_OP. */ 1961 #undef CTORS_SECTION_ASM_OP 1962 #undef DTORS_SECTION_ASM_OP 1963 #ifndef IN_LIBGCC2 1964 # define CTORS_SECTION_ASM_OP \ 1965 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1966 # define DTORS_SECTION_ASM_OP \ 1967 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1968 #else /* !defined (IN_LIBGCC2) */ 1969 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1970 so we cannot use the definition above. */ 1971 # ifdef __ARM_EABI__ 1972 /* The .ctors section is not part of the EABI, so we do not define 1973 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1974 from trying to use it. We do define it when doing normal 1975 compilation, as .init_array can be used instead of .ctors. */ 1976 /* There is no need to emit begin or end markers when using 1977 init_array; the dynamic linker will compute the size of the 1978 array itself based on special symbols created by the static 1979 linker. However, we do need to arrange to set up 1980 exception-handling here. */ 1981 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1982 # define CTOR_LIST_END /* empty */ 1983 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1984 # define DTOR_LIST_END /* empty */ 1985 # else /* !defined (__ARM_EABI__) */ 1986 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1987 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1988 # endif /* !defined (__ARM_EABI__) */ 1989 #endif /* !defined (IN_LIBCC2) */ 1990 1991 /* True if the operating system can merge entities with vague linkage 1992 (e.g., symbols in COMDAT group) during dynamic linking. */ 1993 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 1994 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 1995 #endif 1996 1997 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 1998 1999 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2000 and check its validity for a certain class. 2001 We have two alternate definitions for each of them. 2002 The usual definition accepts all pseudo regs; the other rejects 2003 them unless they have been allocated suitable hard regs. 2004 The symbol REG_OK_STRICT causes the latter definition to be used. 2005 Thumb-2 has the same restrictions as arm. */ 2006 #ifndef REG_OK_STRICT 2007 2008 #define ARM_REG_OK_FOR_BASE_P(X) \ 2009 (REGNO (X) <= LAST_ARM_REGNUM \ 2010 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2011 || REGNO (X) == FRAME_POINTER_REGNUM \ 2012 || REGNO (X) == ARG_POINTER_REGNUM) 2013 2014 #define ARM_REG_OK_FOR_INDEX_P(X) \ 2015 ((REGNO (X) <= LAST_ARM_REGNUM \ 2016 && REGNO (X) != STACK_POINTER_REGNUM) \ 2017 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2018 || REGNO (X) == FRAME_POINTER_REGNUM \ 2019 || REGNO (X) == ARG_POINTER_REGNUM) 2020 2021 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2022 (REGNO (X) <= LAST_LO_REGNUM \ 2023 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2024 || (GET_MODE_SIZE (MODE) >= 4 \ 2025 && (REGNO (X) == STACK_POINTER_REGNUM \ 2026 || (X) == hard_frame_pointer_rtx \ 2027 || (X) == arg_pointer_rtx))) 2028 2029 #define REG_STRICT_P 0 2030 2031 #else /* REG_OK_STRICT */ 2032 2033 #define ARM_REG_OK_FOR_BASE_P(X) \ 2034 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 2035 2036 #define ARM_REG_OK_FOR_INDEX_P(X) \ 2037 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 2038 2039 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2040 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 2041 2042 #define REG_STRICT_P 1 2043 2044 #endif /* REG_OK_STRICT */ 2045 2046 /* Now define some helpers in terms of the above. */ 2047 2048 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2049 (TARGET_THUMB1 \ 2050 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 2051 : ARM_REG_OK_FOR_BASE_P (X)) 2052 2053 /* For 16-bit Thumb, a valid index register is anything that can be used in 2054 a byte load instruction. */ 2055 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 2056 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 2057 2058 /* Nonzero if X is a hard reg that can be used as an index 2059 or if it is a pseudo reg. On the Thumb, the stack pointer 2060 is not suitable. */ 2061 #define REG_OK_FOR_INDEX_P(X) \ 2062 (TARGET_THUMB1 \ 2063 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 2064 : ARM_REG_OK_FOR_INDEX_P (X)) 2065 2066 /* Nonzero if X can be the base register in a reg+reg addressing mode. 2067 For Thumb, we cannot use SP + reg, so reject SP. */ 2068 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 2069 REG_OK_FOR_INDEX_P (X) 2070 2071 #define ARM_BASE_REGISTER_RTX_P(X) \ 2072 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) 2073 2074 #define ARM_INDEX_REGISTER_RTX_P(X) \ 2075 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) 2076 2077 /* Specify the machine mode that this machine uses 2078 for the index in the tablejump instruction. */ 2079 #define CASE_VECTOR_MODE Pmode 2080 2081 #define CASE_VECTOR_PC_RELATIVE ((TARGET_THUMB2 \ 2082 || (TARGET_THUMB1 \ 2083 && (optimize_size || flag_pic))) \ 2084 && (!target_pure_code)) 2085 2086 2087 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 2088 (TARGET_THUMB1 \ 2089 ? (min >= 0 && max < 512 \ 2090 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 2091 : min >= -256 && max < 256 \ 2092 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 2093 : min >= 0 && max < 8192 \ 2094 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 2095 : min >= -4096 && max < 4096 \ 2096 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 2097 : SImode) \ 2098 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ 2099 : (max >= 0x200) ? HImode \ 2100 : QImode)) 2101 2102 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 2103 unsigned is probably best, but may break some code. */ 2104 #ifndef DEFAULT_SIGNED_CHAR 2105 #define DEFAULT_SIGNED_CHAR 0 2106 #endif 2107 2108 /* Max number of bytes we can move from memory to memory 2109 in one reasonably fast instruction. */ 2110 #define MOVE_MAX 4 2111 2112 #undef MOVE_RATIO 2113 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 2114 2115 /* Define if operations between registers always perform the operation 2116 on the full register even if a narrower mode is specified. */ 2117 #define WORD_REGISTER_OPERATIONS 1 2118 2119 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2120 will either zero-extend or sign-extend. The value of this macro should 2121 be the code that says which one of the two operations is implicitly 2122 done, UNKNOWN if none. */ 2123 #define LOAD_EXTEND_OP(MODE) \ 2124 (TARGET_THUMB ? ZERO_EXTEND : \ 2125 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2126 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 2127 2128 /* Nonzero if access to memory by bytes is slow and undesirable. */ 2129 #define SLOW_BYTE_ACCESS 0 2130 2131 /* Immediate shift counts are truncated by the output routines (or was it 2132 the assembler?). Shift counts in a register are truncated by ARM. Note 2133 that the native compiler puts too large (> 32) immediate shift counts 2134 into a register and shifts by the register, letting the ARM decide what 2135 to do instead of doing that itself. */ 2136 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2137 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2138 On the arm, Y in a register is used modulo 256 for the shift. Only for 2139 rotates is modulo 32 used. */ 2140 /* #define SHIFT_COUNT_TRUNCATED 1 */ 2141 2142 /* Calling from registers is a massive pain. */ 2143 #define NO_FUNCTION_CSE 1 2144 2145 /* The machine modes of pointers and functions */ 2146 #define Pmode SImode 2147 #define FUNCTION_MODE Pmode 2148 2149 #define ARM_FRAME_RTX(X) \ 2150 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2151 || (X) == arg_pointer_rtx) 2152 2153 /* Try to generate sequences that don't involve branches, we can then use 2154 conditional instructions. */ 2155 #define BRANCH_COST(speed_p, predictable_p) \ 2156 ((arm_branch_cost != -1) ? arm_branch_cost : \ 2157 (current_tune->branch_cost (speed_p, predictable_p))) 2158 2159 /* False if short circuit operation is preferred. */ 2160 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 2161 ((optimize_size) \ 2162 ? (TARGET_THUMB ? false : true) \ 2163 : TARGET_THUMB ? static_cast<bool> (current_tune->logical_op_non_short_circuit_thumb) \ 2164 : static_cast<bool> (current_tune->logical_op_non_short_circuit_arm)) 2165 2166 2167 /* Position Independent Code. */ 2168 /* We decide which register to use based on the compilation options and 2169 the assembler in use; this is more general than the APCS restriction of 2170 using sb (r9) all the time. */ 2171 extern unsigned arm_pic_register; 2172 2173 /* The register number of the register used to address a table of static 2174 data addresses in memory. */ 2175 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2176 2177 /* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT 2178 entries would need to handle saving and restoring it). */ 2179 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC 2180 2181 /* We can't directly access anything that contains a symbol, 2182 nor can we indirect via the constant pool. One exception is 2183 UNSPEC_TLS, which is always PIC. */ 2184 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2185 (!(symbol_mentioned_p (X) \ 2186 || label_mentioned_p (X) \ 2187 || (GET_CODE (X) == SYMBOL_REF \ 2188 && CONSTANT_POOL_ADDRESS_P (X) \ 2189 && (symbol_mentioned_p (get_pool_constant (X)) \ 2190 || label_mentioned_p (get_pool_constant (X))))) \ 2191 || tls_mentioned_p (X)) 2192 2193 /* We may want to save the PIC register if it is a dedicated one. */ 2194 #define PIC_REGISTER_MAY_NEED_SAVING \ 2195 (flag_pic \ 2196 && !TARGET_SINGLE_PIC_BASE \ 2197 && !TARGET_FDPIC \ 2198 && arm_pic_register != INVALID_REGNUM) 2199 2200 /* We need to know when we are making a constant pool; this determines 2201 whether data needs to be in the GOT or can be referenced via a GOT 2202 offset. */ 2203 extern int making_const_table; 2204 2205 /* Handle pragmas for compatibility with Intel's compilers. */ 2206 /* Also abuse this to register additional C specific EABI attributes. */ 2207 #define REGISTER_TARGET_PRAGMAS() do { \ 2208 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2209 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2210 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2211 arm_lang_object_attributes_init(); \ 2212 arm_register_target_pragmas(); \ 2213 } while (0) 2214 2215 /* Condition code information. */ 2216 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2217 return the mode to be used for the comparison. */ 2218 2219 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2220 2221 #define REVERSIBLE_CC_MODE(MODE) 1 2222 2223 #define REVERSE_CONDITION(CODE,MODE) \ 2224 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2225 ? reverse_condition_maybe_unordered (code) \ 2226 : reverse_condition (code)) 2227 2228 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2229 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2230 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2231 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2232 2233 #define CC_STATUS_INIT \ 2234 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2235 2236 #undef ASM_APP_ON 2237 #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \ 2238 "\t.syntax divided\n") 2239 2240 #undef ASM_APP_OFF 2241 #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax unified\n" : \ 2242 "\t.thumb\n\t.syntax unified\n") 2243 2244 /* Output a push or a pop instruction (only used when profiling). 2245 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2246 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2247 that r7 isn't used by the function profiler, so we can use it as a 2248 scratch reg. WARNING: This isn't safe in the general case! It may be 2249 sensitive to future changes in final.cc:profile_function. */ 2250 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2251 do \ 2252 { \ 2253 if (TARGET_THUMB1 \ 2254 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2255 { \ 2256 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2257 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2258 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2259 } \ 2260 else \ 2261 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2262 } while (0) 2263 2264 2265 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2266 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2267 do \ 2268 { \ 2269 if (TARGET_THUMB1 \ 2270 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2271 { \ 2272 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2273 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2274 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2275 } \ 2276 else \ 2277 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2278 } while (0) 2279 2280 #define ADDR_VEC_ALIGN(JUMPTABLE) \ 2281 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) 2282 2283 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the 2284 default alignment from elfos.h. */ 2285 #undef ASM_OUTPUT_BEFORE_CASE_LABEL 2286 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ 2287 2288 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 2289 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 2290 ? 1 : 0) 2291 2292 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2293 arm_declare_function_name ((STREAM), (NAME), (DECL)); 2294 2295 /* For aliases of functions we use .thumb_set instead. */ 2296 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2297 do \ 2298 { \ 2299 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2300 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2301 \ 2302 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2303 { \ 2304 fprintf (FILE, "\t.thumb_set "); \ 2305 assemble_name (FILE, LABEL1); \ 2306 fprintf (FILE, ","); \ 2307 assemble_name (FILE, LABEL2); \ 2308 fprintf (FILE, "\n"); \ 2309 } \ 2310 else \ 2311 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2312 } \ 2313 while (0) 2314 2315 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2316 /* To support -falign-* switches we need to use .p2align so 2317 that alignment directives in code sections will be padded 2318 with no-op instructions, rather than zeroes. */ 2319 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2320 if ((LOG) != 0) \ 2321 { \ 2322 if ((MAX_SKIP) == 0) \ 2323 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2324 else \ 2325 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2326 (int) (LOG), (int) (MAX_SKIP)); \ 2327 } 2328 #endif 2329 2330 /* Add two bytes to the length of conditionally executed Thumb-2 2331 instructions for the IT instruction. */ 2332 #define ADJUST_INSN_LENGTH(insn, length) \ 2333 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2334 length += 2; 2335 2336 /* Only perform branch elimination (by making instructions conditional) if 2337 we're optimizing. For Thumb-2 check if any IT instructions need 2338 outputting. */ 2339 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2340 if (TARGET_ARM && optimize) \ 2341 arm_final_prescan_insn (INSN); \ 2342 else if (TARGET_THUMB2) \ 2343 thumb2_final_prescan_insn (INSN); \ 2344 else if (TARGET_THUMB1) \ 2345 thumb1_final_prescan_insn (INSN) 2346 2347 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2348 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2349 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2350 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2351 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2352 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2353 : 0)))) 2354 2355 /* A C expression whose value is RTL representing the value of the return 2356 address for the frame COUNT steps up from the current frame. */ 2357 2358 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2359 arm_return_addr (COUNT, FRAME) 2360 2361 /* Mask of the bits in the PC that contain the real return address 2362 when running in 26-bit mode. */ 2363 #define RETURN_ADDR_MASK26 (0x03fffffc) 2364 2365 /* Pick up the return address upon entry to a procedure. Used for 2366 dwarf2 unwind information. This also enables the table driven 2367 mechanism. */ 2368 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2369 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2370 2371 /* Used to mask out junk bits from the return address, such as 2372 processor state, interrupt status, condition codes and the like. */ 2373 #define MASK_RETURN_ADDR \ 2374 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2375 in 26 bit mode, the condition codes must be masked out of the \ 2376 return address. This does not apply to ARM6 and later processors \ 2377 when running in 32 bit mode. */ \ 2378 ((arm_arch4 || TARGET_THUMB) \ 2379 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2380 : arm_gen_return_addr_mask ()) 2381 2382 2383 /* Do not emit .note.GNU-stack by default. */ 2384 #ifndef NEED_INDICATE_EXEC_STACK 2385 #define NEED_INDICATE_EXEC_STACK 0 2386 #endif 2387 2388 #define TARGET_ARM_ARCH \ 2389 (arm_base_arch) \ 2390 2391 /* The highest Thumb instruction set version supported by the chip. */ 2392 #define TARGET_ARM_ARCH_ISA_THUMB \ 2393 (arm_arch_thumb2 ? 2 : (arm_arch_thumb1 ? 1 : 0)) 2394 2395 /* Expands to an upper-case char of the target's architectural 2396 profile. */ 2397 #define TARGET_ARM_ARCH_PROFILE \ 2398 (arm_active_target.profile) 2399 2400 /* Bit-field indicating what size LDREX/STREX loads/stores are available. 2401 Bit 0 for bytes, up to bit 3 for double-words. */ 2402 #define TARGET_ARM_FEATURE_LDREX \ 2403 ((TARGET_HAVE_LDREX ? 4 : 0) \ 2404 | (TARGET_HAVE_LDREXBH ? 3 : 0) \ 2405 | (TARGET_HAVE_LDREXD ? 8 : 0)) 2406 2407 /* Set as a bit mask indicating the available widths of hardware floating 2408 point types. Where bit 1 indicates 16-bit support, bit 2 indicates 2409 32-bit support, bit 3 indicates 64-bit support. */ 2410 #define TARGET_ARM_FP \ 2411 (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \ 2412 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \ 2413 : 0) 2414 2415 2416 /* Set as a bit mask indicating the available widths of floating point 2417 types for hardware NEON floating point. This is the same as 2418 TARGET_ARM_FP without the 64-bit bit set. */ 2419 #define TARGET_NEON_FP \ 2420 (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ 2421 : 0) 2422 2423 /* Name of the automatic fpu-selection option. */ 2424 #define FPUTYPE_AUTO "auto" 2425 2426 /* The maximum number of parallel loads or stores we support in an ldm/stm 2427 instruction. */ 2428 #define MAX_LDM_STM_OPS 4 2429 2430 extern const char *arm_rewrite_mcpu (int argc, const char **argv); 2431 extern const char *arm_rewrite_march (int argc, const char **argv); 2432 extern const char *arm_asm_auto_mfpu (int argc, const char **argv); 2433 #define ASM_CPU_SPEC_FUNCTIONS \ 2434 { "rewrite_mcpu", arm_rewrite_mcpu }, \ 2435 { "rewrite_march", arm_rewrite_march }, \ 2436 { "asm_auto_mfpu", arm_asm_auto_mfpu }, 2437 2438 #define ASM_CPU_SPEC \ 2439 " %{mfpu=auto:%<mfpu=auto %:asm_auto_mfpu(%{march=*: arch %*})}" \ 2440 " %{mcpu=generic-*:-march=%:rewrite_march(%{mcpu=generic-*:%*});" \ 2441 " march=*:-march=%:rewrite_march(%{march=*:%*});" \ 2442 " mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})" \ 2443 " }" 2444 2445 extern const char *arm_target_mode (int argc, const char **argv); 2446 #define TARGET_MODE_SPEC_FUNCTIONS \ 2447 { "target_mode_check", arm_target_mode }, 2448 2449 /* -mcpu=native handling only makes sense with compiler running on 2450 an ARM chip. */ 2451 #if defined(__arm__) && defined(__linux__) 2452 extern const char *host_detect_local_cpu (int argc, const char **argv); 2453 #define HAVE_LOCAL_CPU_DETECT 2454 # define MCPU_MTUNE_NATIVE_FUNCTIONS \ 2455 { "local_cpu_detect", host_detect_local_cpu }, 2456 # define MCPU_MTUNE_NATIVE_SPECS \ 2457 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 2458 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 2459 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2460 #else 2461 # define MCPU_MTUNE_NATIVE_FUNCTIONS 2462 # define MCPU_MTUNE_NATIVE_SPECS "" 2463 #endif 2464 2465 const char *arm_canon_arch_option (int argc, const char **argv); 2466 const char *arm_canon_arch_multilib_option (int argc, const char **argv); 2467 2468 #define CANON_ARCH_SPEC_FUNCTION \ 2469 { "canon_arch", arm_canon_arch_option }, 2470 2471 #define CANON_ARCH_MULTILIB_SPEC_FUNCTION \ 2472 { "canon_arch_multilib", arm_canon_arch_multilib_option }, 2473 2474 const char *arm_be8_option (int argc, const char **argv); 2475 #define BE8_SPEC_FUNCTION \ 2476 { "be8_linkopt", arm_be8_option }, 2477 2478 # define EXTRA_SPEC_FUNCTIONS \ 2479 MCPU_MTUNE_NATIVE_FUNCTIONS \ 2480 ASM_CPU_SPEC_FUNCTIONS \ 2481 CANON_ARCH_SPEC_FUNCTION \ 2482 CANON_ARCH_MULTILIB_SPEC_FUNCTION \ 2483 TARGET_MODE_SPEC_FUNCTIONS \ 2484 BE8_SPEC_FUNCTION 2485 2486 /* Automatically add -mthumb for Thumb-only targets if mode isn't specified 2487 via the configuration option --with-mode or via the command line. The 2488 function target_mode_check is called to do the check with either: 2489 - an array of -march values if any is given; 2490 - an array of -mcpu values if any is given; 2491 - an empty array. */ 2492 #define TARGET_MODE_SPECS \ 2493 " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:arch %*;mcpu=*:cpu %*;:})}}" 2494 2495 /* Generate a canonical string to represent the architecture selected. */ 2496 #define ARCH_CANONICAL_SPECS \ 2497 " -march=%:canon_arch(%{mcpu=*: cpu %*} " \ 2498 " %{march=*: arch %*} " \ 2499 " %{mfpu=*: fpu %*} " \ 2500 " %{mfloat-abi=*: abi %*}" \ 2501 " %<march=*) " 2502 2503 /* Generate a canonical string to represent the architecture selected ignoring 2504 the options not required for multilib linking. */ 2505 #define MULTILIB_ARCH_CANONICAL_SPECS \ 2506 "-mlibarch=%:canon_arch_multilib(%{mcpu=*: cpu %*} " \ 2507 " %{march=*: arch %*} " \ 2508 " %{mfpu=*: fpu %*} " \ 2509 " %{mfloat-abi=*: abi %*}" \ 2510 " %<mlibarch=*) " 2511 2512 /* Complete set of specs for the driver. Commas separate the 2513 individual rules so that any option suppression (%<opt...)is 2514 completed before starting subsequent rules. */ 2515 #define DRIVER_SELF_SPECS \ 2516 MCPU_MTUNE_NATIVE_SPECS, \ 2517 TARGET_MODE_SPECS, \ 2518 MULTILIB_ARCH_CANONICAL_SPECS, \ 2519 ARCH_CANONICAL_SPECS 2520 2521 #define TARGET_SUPPORTS_WIDE_INT 1 2522 2523 /* For switching between functions with different target attributes. */ 2524 #define SWITCHABLE_TARGET 1 2525 2526 /* Define SECTION_ARM_PURECODE as the ARM specific section attribute 2527 representation for SHF_ARM_PURECODE in GCC. */ 2528 #define SECTION_ARM_PURECODE SECTION_MACH_DEP 2529 2530 #endif /* ! GCC_ARM_H */ 2531