| /llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRewritePartialRegUses.cpp | 139 mutable SmallDenseMap<std::pair<unsigned, unsigned>, unsigned> SubRegs; global() member in __anonb2bec34b0111::GCNRewritePartialRegUses
424 SubRegMap SubRegs; rewriteReg() local
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| H A D | AMDGPUInstructionSelector.cpp | 556 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8); selectG_MERGE_VALUES() local
601 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8); selectG_UNMERGE_VALUES() local
3037 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize); computeIndirectRegIndex() local
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| H A D | SIInstrInfo.cpp | 6057 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32; readlaneVGPRToSGPR() local
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| /llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 115 uint32_t SubRegs; // Sub-register set, described above member
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| /llvm-project/llvm/utils/TableGen/Common/ |
| H A D | CodeGenRegisters.h | 299 SubRegMap SubRegs; variable
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| H A D | CodeGenRegisters.cpp | 631 ListInit *SubRegs = Def->getValueAsListInit("SubRegs"); expand() local
2172 const SubRegMap &SubRegs = Register.getSubRegs(); computeRegUnitLaneMasks() local
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| /llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1436 return createTuple(Regs, RegClassIDs, SubRegs); in createTuple() argument
1397 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, createDTuple() local
1406 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, createQTuple() local
1416 static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1, createZTuple() local
1429 static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1, createZMulTuple() local
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| /llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 700 createTuple(ArrayRef<Register> Regs,const unsigned RegClassIDs[],const unsigned SubRegs[],MachineIRBuilder & MIB) createTuple() argument
721 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, createDTuple() local
730 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, createQTuple() local
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| /llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2938 uint16_t SubRegs[2] = {ARM::gsub_0, ARM::gsub_1}; SelectCDE_CXxD() local
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| H A D | ARMBaseInstrInfo.cpp | 936 unsigned SubRegs = 0; in copyPhysReg() local
[all...] |