| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRewritePartialRegUses.cpp | 139 mutable SmallDenseMap<std::pair<unsigned, unsigned>, unsigned> SubRegs; member in __anone5c5202a0111::GCNRewritePartialRegUses
424 SubRegMap SubRegs; rewriteReg() local
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| H A D | AMDGPUInstructionSelector.cpp | 562 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES() local
607 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8); selectG_UNMERGE_VALUES() local
3079 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize); computeIndirectRegIndex() local
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| H A D | SIInstrInfo.cpp | 5946 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32; readlaneVGPRToSGPR() local
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| /freebsd-src/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 111 uint32_t SubRegs; // Sub-register set, described above global() member
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| /freebsd-src/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | |
| H A D | CodeGenRegisters.cpp | |
| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1376 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, createDTuple() local
1385 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, createQTuple() local
1395 static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1, createZTuple() local
1408 static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1, createZMulTuple() local
1415 createTuple(ArrayRef<SDValue> Regs,const unsigned RegClassIDs[],const unsigned SubRegs[]) createTuple() argument
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 690 createTuple(ArrayRef<Register> Regs,const unsigned RegClassIDs[],const unsigned SubRegs[],MachineIRBuilder & MIB) createTuple() argument
711 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, createDTuple() local
720 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, createQTuple() local
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| /freebsd-src/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 2932 uint16_t SubRegs[2] = {ARM::gsub_0, ARM::gsub_1}; SelectCDE_CXxD() local
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| H A D | ARMBaseInstrInfo.cpp | 935 unsigned SubRegs = 0; copyPhysReg() local
[all...] |