/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | RenameIndependentSubregs.cpp | 182 unsigned SubRegIdx = MO.getSubReg(); in findComponents() local 226 unsigned SubRegIdx = MO.getSubReg(); in rewriteOperands() local 348 unsigned SubRegIdx = MO.getSubReg(); in computeMainRangesFixFlags() local
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H A D | RegisterPressure.cpp | 535 unsigned SubRegIdx = MO.getSubReg(); in collectOperandLanes() local 553 void pushRegLanes(Register Reg, unsigned SubRegIdx, in pushRegLanes() 1235 unsigned SubRegIdx = MO.getSubReg(); in findUseBetween() local
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H A D | VirtRegMap.cpp | 380 unsigned SubRegIdx = MO.getSubReg(); in readsUndefSubreg() local
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H A D | StackMaps.cpp | 251 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg()); in parseOperand() local
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H A D | MachineVerifier.cpp | 2197 unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local 2295 unsigned SubRegIdx = MO->getSubReg(); in checkLiveness() local
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H A D | RegisterCoalescer.cpp | 1693 MachineOperand &MO, unsigned SubRegIdx) { in addUndefFlag() 1847 unsigned SubRegIdx = MO.getSubReg(); in setUndefOnPrunedSubRegUses() local
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H A D | RegAllocFast.cpp | 835 unsigned SubRegIdx = MO.getSubReg(); in allocVirtRegUndef() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
H A D | RISCVExpandPseudoInsts.cpp | 297 unsigned SubRegIdx = RISCV::sub_vrm1_0; in expandVSPILL() local 342 unsigned SubRegIdx = RISCV::sub_vrm1_0; in expandVRELOAD() local
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H A D | RISCVISelDAGToDAG.cpp | 195 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLSEG() local 238 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLSEGFF() local 286 unsigned SubRegIdx = RISCVTargetLowering::getSubregIndexByMVT(VT, I); in selectVLXSEG() local 1058 unsigned SubRegIdx; in Select() local 1111 unsigned SubRegIdx; in Select() local
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H A D | RISCVInstrInfo.cpp | 136 unsigned SubRegIdx = RISCV::sub_vrm1_0; in copyPhysReg() local
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H A D | RISCVISelLowering.cpp | 1132 unsigned SubRegIdx = RISCV::NoSubRegister; in decomposeSubvectorInsertExtractToSubRegs() local 3744 unsigned SubRegIdx, RemIdx; in lowerINSERT_SUBVECTOR() local 3893 unsigned SubRegIdx, RemIdx; in lowerEXTRACT_SUBVECTOR() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
H A D | VEInstrInfo.cpp | 330 const unsigned *SubRegIdx, in copyPhysSubRegs() 393 const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd}; in copyPhysReg() local 399 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd}; in copyPhysReg() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86FixupBWInsts.cpp | 194 const auto SubRegIdx = TRI->getSubRegIndex(SuperDestReg, OrigDestReg); in getSuperRegDestIfDead() local
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H A D | X86InstrInfo.cpp | 8394 if (unsigned SubRegIdx = TRI->getSubRegIndex(DestReg, DescribedReg)) { in describeMOVrrLoadedValue() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
H A D | SILoadStoreOptimizer.cpp | 1295 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeSBufferLoadImmPair() local 1356 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeBufferLoadPair() local 1422 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeTBufferLoadPair() local 1453 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeTBufferStorePair() local 1608 std::pair<unsigned, unsigned> SubRegIdx = getSubRegIdxs(CI, Paired); in mergeBufferStorePair() local
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H A D | AMDGPUISelDAGToDAG.cpp | 589 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue(); in getOperandRegClass() local
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
H A D | InstructionSelectorImpl.h | 890 int64_t SubRegIdx = MatchTable[CurrentIdx++]; in executeMatchTable() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 1965 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in ExtendToInt64() local 1979 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_32, dl, MVT::i32); in TruncateToInt32() local 3053 SDValue SubRegIdx = in addExtOrTrunc() local 3063 SDValue SubRegIdx = in addExtOrTrunc() local 5018 SDValue SubRegIdx = CurDAG->getTargetConstant(PPC::sub_eq, dl, MVT::i32); in Select() local
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/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 472 CodeGenSubRegIndex *SubRegIdx; in computeSecondarySubRegs() local 494 if (CodeGenSubRegIndex *SubRegIdx = getSubRegIndex(SubReg)) { in computeSecondarySubRegs() local
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H A D | GlobalISelEmitter.cpp | 2810 const CodeGenSubRegIndex *SubRegIdx; member in __anon332dbd1e0111::TempRegRenderer 2876 const CodeGenSubRegIndex *SubRegIdx; member in __anon332dbd1e0111::SubRegIndexRenderer
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 1171 unsigned SubRegIdx = in loadVectorConstant() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 1370 unsigned SubRegIdx) { in SelectLoad() 1399 unsigned Opc, unsigned SubRegIdx) { in SelectPostLoad()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 4532 SDValue SubRegIdx = in Select() local 4545 SDValue SubRegIdx = in Select() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 3340 unsigned SubRegIdx = Subtarget.isABI_N64() ? Mips::sub_32 : 0; in emitINSERT_DF_VIDX() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/LiveDebugValues/ |
H A D | InstrRefBasedImpl.cpp | 1831 unsigned SubRegIdx = SRI.getSubRegIndex(); in performCopy() local
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